A82DL32X4T AMICC | Alldatasheet

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A82DL32x4T(U) Series Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL32x4T(U) 32 Megabit (4Mx8 Bit/2Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash Memory and 4M (256Kx16 Bit) Static RAM Preliminary PRELIMINARY (August, 2005, Version 0.0) AMIC Technology, Corp. Document Title Stacked Multi-Chip Package (MCP) Flash Memo ry and SRAM, A82DL32x4T(U) 32 Megabit (4Mx8 Bit/2Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash Memory and 4M (256Kx16 Bit) Static RAM

Revision History

Rev. No. History Issue Date Remark

0.0 Initial issue August 21, 2005 Preliminary

A82DL32x4T(U) Series Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL32x4T(U) 32 Megabit (4Mx8 Bit/2Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash Memory and 4M (256Kx16 Bit) Static RAM Preliminary PRELIMINARY (August, 2005, Version 0.0) 1 AMIC Technology, Corp. DISTINCTIVE CHARACTERISTICS MCP Features „ Single power supply operation 2.7 to 3.6 volt „ High Performance - Access time as fast as 70ns „ Package 69-Ball TFBGA (8x11x1.4 mm) „ Industrial operating temperature range: -40 °C to 85 °C for –U; -25°C to 85°C for –I Flash Features ARCHITECTURAL ADVANTAGES „ Simultaneous Read/Write operations - Data can be continuously read from one bank while executing erase/program functions in other bank - Zero latency between read and write operations „ Multiple bank architectures - Three devices available with different bank sizes (refer to Table 2) „ Package - 69-Ball TFBGA (8x11x1.4 mm) „ Top or bottom boot block „ Manufactured on 0.18 µm process technology - Compatible with AM42DL32x4G devices „ Compatible with JEDEC standards - Pinout and software compatible with single-power-supply flash standard PERFORMANCE CHARACTERISTICS „ High performance - Access time as fast as 70ns - Program time: 7µs/word typical utilizing Accelerate function „ Ultra low power consumption (typical values) - 2mA active read current at 1MHz - 10mA active read current at 5MHz - 200nA in standby or automatic sleep mode „ Minimum 1 million write cycles guaranteed per sector „ 20 Year data retention at 125°C - Reliable operation for the life of the system SOFTWARE FEATURES „ Supports Common Flash Memory Interface (CFI) „ Erase Suspend/Erase Resume - Suspends erase operations to allow programming in same bank Data Polling and Toggle Bit - Provides a software method of detecting the status of program or erase cycles „ Unlock Bypass Program command - Reduces overall programming time when issuing multiple program command sequences HARDWARE FEATURES „ Any combination of sectors can be erased „ Ready/Busy output (RY/BY) - Hardware method for detecting program or erase cycle completion „ Hardware reset pin (RESET) - Hardware method of resetting the internal state machine to reading array data „ WP /ACC input pin - Write protect ( WP ) function allows protection of two outermost boot sectors, r egardless of sector protect status - Acceleration (ACC) functi on accelerates program timing „ Sector protection - Hardware method of locking a sector, either in-system or using programming equipment, to prevent any program or erase operation within that sector - Temporary Sector Unprotect allows changing data in protected sectors in-system LP SRAM Features „ Power supply range: 2.7V to 3.6V „ Access times: 70 ns (max.) „ Current: Very low power version: Operating: 35mA(max.) Standby: 10uA (max.) „ Full static operation, no clock or refreshing required „ All inputs and outputs are directly TTL-compatible „ Common I/O using three-state output „ Output enable and two chips enable inputs for easy application „ Data retention voltage: 2.0V (min.)

A82DL32x4T(U) Series PRELIMINARY (August, 2005, Version 0.0) 2 AMIC Technology, Corp. GENERAL DESCRIPTION The A82DL32x4T(U) family consists of 32 megabit, 3.0 volt- only flash memory devices, organized as 2,097,152 words of 16 bits each or 4,194,304 bytes of 8 bits each. Word mode data appears on I/O 0–I/O15; byte mode data appears on I/O0– I/O7. The device is designed to be programmed in-system with the standard 3.0 volt VCC supply, and can also be programmed in standard EPROM programmers. The device is available with an access time of 70ns. The devices are offered in 69- ball Fine-pitch BGA. Standard control pins—chip enable ( CE_F ), write enable ( WE ), and output enable ( OE )—control normal read and write operations, and avoid bus contention issues. The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provid ed for the program and erase operations. Simultaneous Read/Write Operations with Zero Latency The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into two banks. The device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from the other bank, with zero latency. This releases the system from waiting for the completion of program or erase operations. The A82DL32x4T(U) devices uses multiple bank archi- tectures to provide flexibility for different applications. Three devices are available with these bank sizes: Device Bank 1 Bank 2 DL3224 4 Mb 28 Mb DL3234 8 Mb 24 Mb DL3244 16 Mb 16 Mb A82DL32x4T(U) Features The device offers complete compatibility with the JEDEC single-power-supply Flash command set standard . Commands are written to the command register using standard microprocessor write timings. Reading data out of the device is similar to readin g from other Flash or EPROM devices. The host system can detect w hether a program or erase operation is complete by using the device status bits: RY/ BY pin, I/O 7 ( Data Polling) and I/O 6/I/O2 (toggle bits). After a program or erase cycle has been completed, the device automatically returns to reading array data. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. T he device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically i nhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved in-s y s t e m or via programming equipment. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode . The system can also place the device into the standby mode . Power consumption is greatly reduced in both modes.

A82DL32x4T(U) Series PRELIMINARY (August, 2005, Version 0.0) 3 AMIC Technology, Corp. Pin Configurations „ 69-Ball TFBGA Top View A5 A6 A10 B3 B4 B5 B6 B7 B8 C3 C4 C5 C6 C7 C8 C9 D4 D4 D5 D6 D7 D8 D9 E3 E4 E7 E8 E9 E10 F3 F4 F7 F8 F9 F10 NC NC NC A7 LB_S WP/ACC WE A8 A11 A6 UB_S RESET CE2_S A19 A12 A15 A5 A18 RY/BY NC A9 A13 NC A4 A17 A10 A14 NC NC VSS I/O1 I/O6 NC A16 NC Flash only SRAM only Shared E1 E2 F1 F2 NC NC NC A1 NC A0 G3 G4 G5 G6 G7 G8 G9 H3 H4 H5 H6 H7 H8 H9 I/O9 I/O3 I/O4 I/O13 I/O15(A-1) BYTE_F I/O0 I/O10 VCC_F VCC_S I/O12 I/O7 VSS CE_F OE CE1_S J3 J4 J5 J6 J7 J8 K5 K6 K10 I/O8 I/O2 I/O11 NC I/O5 I/O14 NC NC NC NC Special Handling Instructions for TFBGA Package Special handling is required for Flash Memory products in TFBGA packages. Flash memory devices in TFBGA packages may be damaged if ex posed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time

A82DL32x4T(U) Series PRELIMINARY (August, 2005, Version 0.0) 4 AMIC Technology, Corp. Product Information Guide Part Number A82DL32x4T(U) Speed Options Standard Voltage Range: VCC_F/VCC_S=2.7-3.6V 70 Max Access Time (ns) 70 CE_F /CE_S Access (ns) 70 OE Access (ns) 40 MCP Block Diagram 32M Bit Flash Memory 4M Bit Static RAM VCC_S VSS VCC_F VSS A20 to A0 RY/BY I/O15 (A-1) to I/O0 I/O15 (A-1) to I/O0 I/O15 (A-1) to I/O0 A17 to A0 A20 to A0 BYTE_F WP/ACC CE_F CE1_S CE2_S RESET UB_S LB_S OE WE

A82DL32x4T(U) Series PRELIMINARY (August, 2005, Version 0.0) 5 AMIC Technology, Corp. Flash Block Diagram A0-A20 A0-A19 A0-A19 STATE CONTROL COMMAND REGISTER I/O0-I/O15 A0-A20 A0-A20 RESET WE CE_F WP/ACC RY/BY Status Control BYTE_F OE BYTE_F Upper Bank Address Lower Bank Address I/O0-I/O15 Upper Bank X-Decoder Y-Decoder Latches and Control Logic Upper Bank X-Decoder Y-Decoder Latches and Control Logic I/O0-I/O15 I/O0-I/O15 VCC_F VSS OE BYTE_F

A82DL32x4T(U) Series PRELIMINARY (August, 2005, Version 0.0) 6 AMIC Technology, Corp. Pin Descriptions Pin No. Description A0 – A20 Address Inputs I/O0 - I/O14 Data Inputs/Outputs I/O15 Data Input/Out put, Word Mode I/O15 (A-1) A-1 LSB Address Input, Byte Mode CE_F Chip Enable (Flash) CE_S Chip Enable (SRAM) WE Write Enable OE Output Enable WP /ACC Hardware Write Protect/Acceleration Pin RESET Hardware Reset Pin, Active Low BYTE_F Selects 8-bit or 16-bit Mode RY/BY Ready/BUSY Output VSS Ground VCC_F Power Supply (Flash) VCC_S Power Supply (SRAM) NC Pin Not Connected Internally Logic Symbol A0-A20 CE_F OE WE RESET BYTE_F RY/BY I/O0-I/O15(A-1) 16 or 8 WP/ACC CE_S

A82DL32x4T(U) Series PRELIMINARY (August, 2005, Version 0.0) 7 AMIC Technology, Corp. SRAM Block Diagram DECODER

512 X 8192

VCC_S VSS I/O0 A17 A16 WE INPUT DATA CIRCUIT I/O8 I/O15 OE I/O7 CE1_S CE2_S UB_S LB_S

A82DL32x4T(U) Series PRELIMINARY (August, 2005, Version 0.0) 8 AMIC Technology, Corp. DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that st ore the commands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The appropriate device bus operations table lists the inputs and control levels required, and the resulting output. The following subsections describe each of these operations in further detail. Table 1-1. Device Bus Operations – Flash Byte Mode (BYTE_F = VIH) Operation (Notes 1, 2) CE_F E1_SC CE2_S OE WE A0- A20 LB_S (Note3) UB_S (Note3) RESET WP/ACC (Note 4) I/O7– I/O0 I/O15– I/O0 H X Read from Flash L X L L H A IN X X H L/H I OUT I OUT H X Write to Flash L X L H L A IN X X H (Note 4) I IN I IN H X Standby VCC ±

0.3 V X L

X X X X X VCC ±

0.3 V H High-Z High-Z

Output Disable L L H H H X X L H L/H High-Z High-Z H X X L Flash Hardware Reset X H X X X X X X L L/H High-Z High-Z X L Sector Protect (Notes) L H X H L SA, A6 = L, A1 = H, A0 = L X X V ID L/H I IN X Sector Unprotect (Note 5) L X L H L SA, A6 = H, A1 = H, A0 = L X X V ID (Note 6) I IN X H X IIN High-Z Temporary Sector Unprotect X X L X X A IN X X V ID (Note 6) IOUT IOUT H L High-Z I OUT L H I OUT High-Z Read from SRAM H L H L H A IN L L H X IIN I IN H L High-Z I IN Write to SRAM H L H X L A IN L H H X IIN High-Z Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 8.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address, AIN = Address In, IIN = Data In, IOUT = Data Out Notes: 1.Other operations except for those indicated in this column are inhibited. 2.Do not apply CE_F = VIL, CE1_S = VIL and CE2_S = VIH at the same time. 3.Don’t care or open LB_S or UB_S . 4.The sector protect and sect or unprotect functions may also be implem ented via programming equipment. See the “Sector/Sector Block Protection and Unprotection” section. 5. If WP /ACC = V IL, the two outermost boot sect ors remain protected. If WP /ACC = V IH, the two outermost boot sector protection depends on whether they were last protected or unprotect ed using the method described in “Sector/Sector Block Protection and Unprotection”. If WP /ACC = VHH, all sectors will be unprotected.

A82DL32x4T(U) Series PRELIMINARY (August, 2005, Version 0.0) 9 AMIC Technology, Corp. Table 1-2. Device Bus Operations – Flash Byte Mode (BYTE_F = VIL) Operation (Notes 1, 2) CE_F E1_SC CE2_S OE WE A0-A20 LB_S (Note3) UB_S (Note3) RESET WP/ACC (Note 4) I/O7– I/O0 I/O15– I/O8 H X Read from Flash L X L L H A IN X X H L/H I OUT High-Z H X Write to Flash L X L H L A IN X X H (Note 3) I IN I/O14–8 =Hi-Z; I/O15=A-1 H X Standby VCC ± X X X X X VCC_F ± X X X X X L L/H High-Z High-Z H X Sector Protect (Notes) L X L H L SA, A6 = L, A1 = H, A0 = L X X V ID L/H I IN X H X Sector Unprotect (Note 5) L X L H L SA, A6 = H, A1 = H, A0 = L X X V ID (Note 6) I IN X H X Temporary Sector Unprotect X X L X X A IN X X V ID (Note 6) I IN High-Z H L I OUT I OUT H L High-Z I OUT Read from SRAM H L H L H A IN L H H X IOUT High-Z H L I IN I IN L H High-Z I IN Write to SRAM H L H X L A IN L H H X IIN High-Z Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 8.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address, AIN = Address In (for Flash Byte Mode, I/O15=A-1), IIN = Data In, IOUT = Data Out Notes: 1.Other operations except for those indicated in this column are inhibited. 2.Do not apply CE_F = VIL, CE1_S = VIL and CE2_S = VIH at the same time. 3.Don’t care or open LB_S or UB_S . 4.The sector protect and sect or unprotect functions may also be implem ented via programming equipment. See the “Sector/Sector Block Protection and Unprotection” section. 5. If WP /ACC = V IL, the two outermost boot sect ors remain protected. If WP /ACC = V IH, the two outermost boot sector protection depends on whether they were last protected or unprotect ed using the method described in “Sector/Sector Block Protection and Unprotection”. If WP /ACC = VHH, all sectors will be unprotected.

A82DL32x4T(U) Series PRELIMINARY (August, 2005, Version 0.0) 10 AMIC Technology, Corp. Word/Byte Configuration The BYTE_F pin determines whether the I/O pins I/O 15-I/O0 operate in the byte or word configuration. If the BYTE_F pin is set at logic ”1”, the device is in word configuration, I/O 15- I/O0 are active and controlled by CE_F and OE . If the BYTE_F pin is set at logic “0”, the device is in byte configuration, and only I/O 0-I/O7 are active and controlled by CE_F and OE . I/O 8-I/O14 are tri-stated, and I/O 15 pin is used as an input for the LSB(A-1) address function. Requirements for Reading Array Data To read array data from the out puts, the system must drive the CE_F and OE pins to V IL. CE_F is the power control and selects the device. OE is the output control and gates array data to the output pins. WE should remain at VIH. The BYTE_F pin determines whether the device outputs array data in words or bytes. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the devi ce data outputs. Each bank remains enabled for read access until the command register contents are altered. See "Requirements for Reading Array Data" for more information. Refer to the AC Read-Only Operations table for timing specifications and to Figure 11 for the timing waveform, l CC1_F in the DC Characterist ics table represents the active current specification for reading array data. Writing Commands/Command Sequences To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE and CE_F to VIL, and OE to VIH. For program operations, the BYTE_F pin determines whether the device accepts program data in bytes or words, Refer to “Word/Byte Configuration” for more information. The device features an Unlock Bypass mode to facilitate faster programming. Once a bank enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The “Word / Byte Program Command Sequence” section has details on programming data to the device using both standard and Unlock Bypass command sequence. An erase operation can erase one sector, multiple sectors, or the entire device. The Sector Address Tables 3-4 indicate the address range that each sect or occupies. The device address space is divided into two banks: Bank 1 contains the boot/parameter sectors, and Bank 2 contains the larger, code sectors of uniform size. A “bank address” is the address bits required to uniquely select a bank. Similarly, a “sector address” is the address bits required to uniquely select a sector. ICC2_F in the DC Characteristics table represents the active current specification for the write mode. The "AC Characteristics" section contai ns timing specification tables and timing diagrams for write operations. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This is one of two functions provided by the WP /ACC pin. This function is primarily intended to allow faster manufacturing throughput at the factory. If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlo ck Bypass mode, temporarily unprotects any protected sect ors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing V HH from the WP /ACC pin returns the device to normal operation. Note that the WP /ACC pin must not be at VHH for operations other than accelerated program- ming, or device damage may result. In addition, the WP /ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Autoselect Functions If the system writes the autos elect command sequence, the device enters the autoselect m ode. The system can then read autoselect codes from the in ternal register (which is separate from the memory array) on I/O 7-I/O0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autoselect Command Sequence sections for more information. Simultaneous Read/Write Operations with Zero Latency This device is capable of r eading data from one bank of memory while programming or er asing in the other bank of memory. An erase operation may also be suspended to read from or program to another location within the same bank (except the sector being erased). Figure 18 shows how read and write cycles may be initiat ed for simultaneous operation with zero latency. I CC6_F and I CC7_F in the DC Characteristics table represent the current spec ifications for read-while-pro- gram and read-while-erase, respectively. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatl y reduced, and the outputs are placed in the high impedanc e state, indepen dent of the OE input. The device enters the CM OS standby mode when the CE_F & RESET pins are both held at VCC_F ± 0.3V. (Note that this is a more restricted voltage range than V IH.) If CE_F and RESET are held at V IH, but not within VCC_F ± 0.3V, the device will be in t he standby mode, but the standby current will be greater. The device requires the standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active curr ent until the operation is completed. ICC3_F in the DC Characteristics tables represent the standby current specification.

PRELIMINARY (August, 2005, Version 0.0) 11 AMIC Technology, Corp. automatic sleep mode current specification. Current is reduced fo r the duration of the RESET pulse. not within VSS ± 0.3V, the standby current will be greater. the RESET pin return to VIH. Table 2. A82DL32x4T(U) Device Bank Divisions

64 Kbyte/32 Kword

PRELIMINARY (August, 2005, Version 0.0) 12 AMIC Technology, Corp. Table 3. Sector Addresses for Top Boot Sector Devices

A82DL32x4T(U) Series PRELIMINARY (August, 2005, Version 0.0) 13 AMIC Technology, Corp. Table 3 Sector Addresses for Top Boot Sector Devices A29DL324T A29DL323T A29DL322T Sector Sector Address A20–A12 Sector Size (Kbytes/Kwords) (x8) Address Range (x16) Address Range SA48 000000xxx 64/32 300000h-30FFFFh 180000h–187FFFh SA49 000001xxx 64/32 310000h-31FFFFh 188000h–18FFFFh SA50 000010xxx 64/32 320000h-32FFFFh 190000h–197FFFh SA51 000011xxx 64/32 330000h-33FFFFh 198000h–19FFFFh SA52 000100xxx 64/32 340000h-34FFFFh 1A0000h–1A7FFFh SA53 000101xxx 64/32 350000h-35FFFFh 1A8000h–1AFFFFh SA54 000110xxx 64/32 360000h-36FFFFh 1B0000h–1B7FFFh Bank 2 SA55 000111xxx 64/32 370000h-37FFFFh 1B8000h–1BFFFFh SA56 001000xxx 64/32 380000h-38FFFFh 1C0000h–1C7FFFh SA57 001001xxx 64/32 390000h-39FFFFh 1C8000h–1CFFFFh SA58 001010xxx 64/32 3A0000h-3AFFFFh 1D0000h–1D7FFFh SA59 001011xxx 64/32 3B0000h-3BFFFFh 1D8000h–1DFFFFh SA60 001100xxx 64/32 3C0000h-3CFFFFh 1E0000h–1E7FFFh SA61 001101xxx 64/32 3D0000h-3DFFFFh 1E8000h–1EFFFFh SA62 001110xxx 64/32 3E0000h-3EFFFFh 1F 0000h–1F7FFFh SA63 001111xxx 8/4 3F0000h-3FFFFFh 1F8000h–1F8FFFh SA64 010000xxx 8/4 3F2000h-3F3FFFh 1F9000h–1F9FFFh SA65 010001xxx 8/4 3F4000h-3F5FFFh 1FA000h–1FAFFFh SA66 010010xxx 8/4 3F6000h-3F7FFFh 1FB000h–1FBFFFh SA67 010011xxx 8/4 3F8000h-3F9FFFh 1FC000h–1FCFFFh SA68 010100xxx 8/4 3FA000h-3FBFFFh 1FD000h–1FDFFFh SA69 010101xxx 8/4 3FC000h-3FDFFFh 1FE000h–1FEFFFh Bank 1 Bank 1 Bank 1 SA70 010110xxx 8/4 3FE000h-3FFFFFh 1FF000h–1FFFFFh Note: The address range is A20: A-1in byte mode ( BYTE_F =VIL) or A20:A0 in word mode ( BYTE_F =VIH). The bank address bits are A20-A18 for A29DL3224T, A20 and A19 for A29DL3234T, and A20 for A29DL3244T.

PRELIMINARY (August, 2005, Version 0.0) 14 AMIC Technology, Corp. Table 4. Sector Addresses for Bottom Boot Sector Devices

A82DL32x4T(U) Series PRELIMINARY (August, 2005, Version 0.0) 15 AMIC Technology, Corp. A29DL324U A29DL323U A29DL322U Sector Sector Address A20–A12 Sector Size (Kbytes/Kwords) (x8) Address Range (x16) Address Range SA48 101001XXX 64/32 290000h-29FFFFh 148000h-14FFFFh SA49 101010XXX 64/ 32 2A0000h-2AFFFFh 150000h-157FFFh SA50 101011XXX 64/ 32 2B0000h-2BFFFFh 158000h-15FFFFh SA51 101100XXX 64/32 2C0000h-2CFFFFh 160000h-167FFFh SA52 101101XXX 64/32 2D0000h-2DFFFFh 168000h-16FFFFh SA53 101110XXX 64/32 2E00 00h-2EFFFFh 170000h-177FFFh SA54 101111XXX 64/32 2F0000h-2FFFFFh 178000h-17FFFFh SA55 111000XXX 64/32 300000h-30FFFFh 180000h-187FFFh SA56 111001XXX 64/32 310000h-31FFFFh 188000h-18FFFFh SA57 110010XXX 64/32 320000h-32FFFFh 190000h-197FFFh SA58 110011XXX 64/32 330000h-33FFFFh 198000h-19FFFFh SA59 110100XXX 64/32 340000 h-34FFFFh 1A0000h-1A7FFFh SA60 110101XXX 64/32 350000 h-35FFFFh 1A8000h-1AFFFFh SA61 110110XXX 64/32 360000 h-36FFFFh 1B0000h-1B7FFFh SA62 110111XXX 64/32 370 000h-37FFFFh 1B8000h-1BFFFFh SA63 111000XXX 64/32 380000h-38FFFFh 1C0000h-1C7FFFh SA64 111001XXX 64/32 390000h-39FFFFh 1C8000h-1CFFFFh SA65 111010XXX 64/32 3A00 00h-3AFFFFh 1D0000h-1D7FFFh SA66 111011XXX 64/32 3B0000h-3BFFFFh 1D8000h-1DFFFFh SA67 111100XXX 64/32 3C0000 h-3CFFFFh 1E0000h-1E7FFFh SA68 111101XXX 64/32 3D00 00h-3DFFFFh 1E8000h-1EFFFFh SA69 111110XXX 64/32 3E00 00h-3EFFFFh 1F0000h-1F7FFFh Bank 2 Bank 2 Bank 2 SA70 111111XXX 64/32 3F0000h-3FFFFFh 1F8000h-1FFFFFh Note: The address range is A20: A-1in byte mode ( BYTE_F =VIL) or A20:A0 in word mode ( BYTE_F =VIH). The bank address bits are A20-A18 for A29DL3224U, A20 and A19 for A29DL3234U, and A20 for A29DL3244U.

PRELIMINARY (August, 2005, Version 0.0) 16 AMIC Technology, Corp. also be accessed in-system through the command register. must appear on the appropriate highest order address bits. corresponding identifier code on I/O7 - I/O0. Table 5. A82DL32x4T(U) Autoselect Codes (High Voltage Method) Note: The autoselect codes may also be accessed in-system via command sequences.

PRELIMINARY (August, 2005, Version 0.0) 17 AMIC Technology, Corp. unprotected at the same time (see Tables 6 and 7). Table 6. Top Boot Sector/Sector Block Addresses for Table 7. Bottom Boot Sector/Sector Block Addresses for

A82DL32x4T(U) Series PRELIMINARY (August, 2005, Version 0.0) 18 AMIC Technology, Corp. The hardware sector protec tion feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. Sector protection and unprotection can be implemented via two methods. The primary method requires V ID on the RESET pin only, and can be implemented either in-system or via programming equipment. Figure 2 shows the algorithms and Figure 23 shows the timing diagram. This method uses standard microprocessor bus cycle timing. For sector unprotect, all unprotected sector s must first be protected prior to the first sector unprotect write cycle. The sector unprotect algorith m unprotects all sectors in parallel. All previously protect ed sectors must be individually re-protected. To change data in protected sectors efficiently, the temporary sector unprotect function is available. See “Temporary Sector/Sector Block Unprotect”. The alternate method for protec tion and unprotection is by software temporary sector /sector block unprotect command. See Figure 2 for Command Flow. The device is shipped with all sectors unprotected. It is possible to determine whether a sector is protected or unprotected. See the Autoselect Mode section for details. Write Protect ( WP /ACC) The Write Protect function provides a hardware method of protecting certain boot sectors without using V ID. This function is one of two provided by the WP /ACC pin. If the system asserts V IL on the WP /ACC pin, the device disables program and erase func tions in the two “outermost”

8 Kbyte boot sectors independent ly of whether those sectors

were protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. The two outermost 8 Kbyte boot sectors are the two sectors containing the lowest addres ses in a bottom-boot-configured device, or the two sectors co ntaining the highest addresses in a top-boot-configured device. If the system asserts V IH on the WP /ACC pin, the device reverts to whether the two ou termost 8 Kbyte boot sectors were last set to be protected or unprotected. That is, sector protection or unprotection fo r these two sectors depends on whether they were last protec ted or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. Note that the WP /ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Temporary Sector/Sector Block Unprotect (Note: For the following discussion, the term “sector” applies to both sectors and sector blocks. A sector block consists of two or more adjacent sector s that are protected or unprotected at the same time (see Tables 6 and 7). This feature allows temporar y unprotection of previously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET pin to VID (8.5V-12.5V). During this m ode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once VID is removed from the RESET pin, all the previously protected sectors are protected again. Figure 1 shows the algorithm, and Figure 22 shows the timing diagrams, for this feature.

A82DL32x4T(U) Series PRELIMINARY (August, 2005, Version 0.0) 20 AMIC Technology, Corp. START PLSCNT=1 RESET=VID Wait 1 us First Write Cycle=60h? Set up sector address Sector Protect: Write 60h to sector address with A6=0, A1=1, A0=0 Wait 150 us Verify Sector Protect: Write 40h to sector address with A6=0, A1=1, A0=0 Read from sector address with A6=0, A1=1, A0=0 Data=01h? Protect another sector? Remove VID from RESET Write reset command Sector Protect complete Sector Protect Algorithm Temporary Sector Unprotect Mode Increment PLSCNT PLSCNT =25? Device failed No No No Yes Reset PLSCNT=1 Yes Yes No Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address START PLSCNT=1 Wait 1 us First Write Cycle=60h? No Temporary Sector Unprotect Mode Yes No All sectors protected? Set up first sector address Sector Unprotect: Write 60h to sector address with A6=1, A1=1, A0=0 Wait 15 ms Verify Sector Unprotect : Write 40h to sector address with A6=1, A1=1, A0=0 Read from sector address with A6=1, A1=1, A0=0 Data=00h? Last sector verified? Remove VID from RESET Write reset Command Sector Unprotect complete Yes Yes Set up next sector address No Yes Yes Sector Unprotect Algorithm Increment PLSCNT PLSCNT= 1000? Device failed Yes No No Figure 2-1. High Voltage Sector/Sector Block Protection and Unprotection Algorithms Note: The term “sector” in the figure applies to both sectors and sector blocks * No other command is allowed during this process ** Read access time is 200ns-300ns RESET=VID

A82DL32x4T(U) Series PRELIMINARY (August, 2005, Version 0.0) 21 AMIC Technology, Corp. START PLSCNT=1 555/AA + 2AA/55 + Wait 1 us First Write Cycle=60h? Set up sector address Sector Protect: Write 60h to sector address with A6=0, A1=1, A0=0 Wait 150 us Verify Sector Protect: Write 40h to sector address with A6=0, A1=1, A0=0 Read from sector address with A6=0, A1=1, A0=0 Data=01h? Protect another sector? Write reset command Sector Protect complete Sector Protect Algorithm Temporary Sector Unprotect Mode Increment PLSCNT PLSCNT =25? Device failed No No No Yes Reset PLSCNT=1 Yes Yes No Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address START PLSCNT=1 Wait 1 us First Write Cycle=60h? No Temporary Sector Unprotect Mode Yes No All sectors protected? Set up first sector address Sector Unprotect: Write 60h to sector address with A6=1, A1=1, A0=0 Wait 15 ms Verify Sector Unprotect : Write 40h to sector address with A6=1, A1=1, A0=0 Read from sector address with A6=1, A1=1, A0=0 Data=00h? Last sector verified? Write reset Command Sector Unprotect complete Yes Yes Set up next sector address No Yes Yes Sector Unprotect Algorithm Increment PLSCNT PLSCNT= 1000? Device failed Yes No No Figure 2-2. Software Sector/Sector Block Protection and Unprotection Algorithms Note: The term “sector” in the figure applies to both sectors and sector blocks * No other command is allowed during this process ** Access time is 200ns-300ns 555/AA + 2AA/55 +

PRELIMINARY (August, 2005, Version 0.0) 22 AMIC Technology, Corp. inadvertent writes (refer to Table 12 for command definitions). writes when VCC_F is greater than VLKO. WE do not initiate a write cycle. and WE must be a logical zero while OE is a logical one. device does not accept commands on the rising edge of WE . interfaces for long-term compatibility. reset command to return the device to the autoselect mode. Table 8. CFI Query Identification String

PRELIMINARY (August, 2005, Version 0.0) 23 AMIC Technology, Corp. Table 9. System Interface String

PRELIMINARY (August, 2005, Version 0.0) 24 AMIC Technology, Corp. Table 11. Primary Vendor-Specific Extended Query

A82DL32x4T(U) Series PRELIMINARY (August, 2005, Version 0.0) 25 AMIC Technology, Corp. COMMAND DEFINITIONS Writing specific address and data commands or sequences into the command register initiates device operations. Table 12 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. A reset command is then required to return the device to reading array data. All addresses are latched on the falling edge of WE or CE_F , whichever happens later. All data is latched on the rising edge of WE or CE_F , whichever happens first. Refer to the AC Characteristics section for timing diagrams. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the corresponding bank enters the erase-suspend-read mode, after which the system can read data from any non-erase- suspended sector within the same bank. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See the Erase Suspend/Erase Resume Commands section for more information. The system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if I/O 5 goes high during an active program or erase operation, or if the bank is in the autoselect mode. See the next section, Reset Command, for more information. See also Requirements for Reading Array Data in the Device Bus Operations section for more information. The Read-Only Operations table provides the read parameters, and Figure 11 shows the timing diagram. Reset Command Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the bank to which the system was writing to reading array data. Once er asure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the bank to which the system was writing to reading array data. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data. If a bank entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. If I/O 5 goes high during a program or erase operation, writing the reset command returns the banks to reading array data (or erase-suspend-read mode if that bank was in Erase Suspend). Autoselect Command Sequence The autoselect command sequenc e allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. Table 12 shows the address and data requirement s. This method is an alternative to that shown in Table 5, which is intended for PROM programmers and requires V ID on address pin A9. The autoselect command sequence may be written to an address wit h in a bank that is either in t he read or erase- suspend-read mode. The autoselect command may not be written while the device is actively programming or erasing in the other bank. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the bank address and the autoselect command. T he bank then enter s the autoselec t mode. The system may read at any address within the same bank any number of times without initiating another autoselect command sequence: „ A read cycle at address (BA)XX00h (where BA is the bank address) returns the manufacturer code. „ A read cycle at address (BA)XX01h in word mode (or (BA)XX02h in byte mode) returns the device code. „ A read cycle to an address containing a sector address (SA) within the same bank, and the address 02h on A7-A0 in word mode (or the address 04h on A6-A-1 in byte mode) returns 01h if the sector is protected, or 00h if it is unprotected. (Refer to Tabl es 3-4 for valid sector addresses). The system must write the reset command to return to reading array data (or erase-suspend-read mode if the bank was previously in Erase Suspend). Byte/Word Program Command Sequence The system may program the device by word or byte, depending on the state of the BYTE_F pin. Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table 12 shows the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, that bank then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using I/O 7, I/O6, or RY/ BY. Refer to the Write Operation Status section for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the progr am operation. The program command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from “0” back to a “1.” Attempting to do so may cause that bank to set I/O 5 = 1, or cause the I/O7 and I/O6 status bits to indicate the operation was successful. However, a succeeding read will show that the data is still “0.” Only erase operations can convert a “0” to a “1.”

PRELIMINARY (August, 2005, Version 0.0) 28 AMIC Technology, Corp.

  1. See Table 14 for erase command sequence.

Figure 4. Erase Operation

PRELIMINARY (August, 2005, Version 0.0) 29 AMIC Technology, Corp. Table 12. A82DL32x4T(U) Command Definitions

555 AAA AAA

55 SA 30

RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data latches on the rising edge of WE or CE_F pulse, whichever happens first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A20 - A12 select a unique sector. BA = Address of the bank that is being switched to autoselect mode, is in bypass mode, or is being erased.

  1. See Table 1 for description of bus operations.
  2. All values are in hexadecimal.
  3. Except for the read cycle and the four th cycle of the autoselect command sequence, all bus cycles are write cycles.

15-I/O8 are don’t care in command sequences. Except for RD and PD.

  1. Unless otherwise noted, address bits A20-A11 are don’t cares.
  2. No unlock or command cycles required when bank is reading array data.
  3. The Reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in Erase

5 goes high (while the bank is providing status information).

  1. The fourth cycle of the autoselect co mmand sequence is a read cycle. The system must provide the bank address to obtain

section for more information.

  1. The data is 00h for an unprotect ed sector/sector block and 01h for a protected sector/sector block.
  2. The Unlock Bypass command is required prior to the Unlock Bypass Program Command.
  3. The Unlock Bypass Reset command is required to return to reading array data when the bank is in the unlock bypass mode.
  4. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode.

The Erase Suspend command is valid only during a sector erase operation, and require the bank address.

  1. The Erase Resume command is valid only during the Erase.
  2. Command is valid when device is ready to read array data or when device is in autoselect mode.
  3. Once reset command is applied, software temporary unprotect is exit to return read array data. But under erase suspend

the software temporary unprotect command is useful only after the erase command is complete.

PRELIMINARY (August, 2005, Version 0.0) 30 AMIC Technology, Corp. program or erase operation: I/O 2, I/O 3, I/O 5, I/O 6, and I/O 7. program or erase command sequence. 7 the complement of the datum programmed to I/O 7. complete, the device outputs the datum programmed to I/O 7. erasure to read valid status information on I/O7. sectors, and ignores the selected sectors that are protected. protected sector, the status may not be valid.

  1. VA = Valid address for programming. During a sector

address is any non-protected sector address. I/O7 may change simultaneously with I/O5. Figure 5. Data Polling Algorithm

A82DL32x4T(U) Series PRELIMINARY (August, 2005, Version 0.0) 32 AMIC Technology, Corp. I/O2: Toggle Bit II The "Toggle Bit II" on I/O 2, when used with I/O 6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE pulse in the command sequence. I/O2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE or CE_F to control the read cycles.) But I/O 2 cannot distinguish whether the sect or is actively erasing or is erase-suspended. I/O6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required fo r sector and mode information. Refer to Table 8 to compare outputs for I/O2 and I/O6. Figure 6 shows the toggle bit algor ithm in flowchart form, and the section " I/O 2: Toggle Bit II" explains the algorithm. See also the " I/O 6: Toggle Bit I" subsection. Figure 20 shows the toggle bit timing diagram. Figure 21 shows the differences between I/O2 and I/O6 in graphical form. Reading Toggle Bits I/O6, I/O2 Refer to Figure 6 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read I/O7-I/O0 at least twice in a row to determine whether a toggle bit is toggling. Typically, a system would note and store the value of the toggle bit after the first read. After the second read, the system would compar e the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or eras e operation. The system can read array data on I/O7-I/O0 on the following read cycle. However, if after the initia l two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of I/O 5 is high (see the section on I/O 5). If it is, the system should then determine again whether the toggle bit is togg ling, since the toggle bit may have stopped toggling just as I/O 5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and I/O 5 has not gone high. The system may continue to monitor the toggle bit and I/O 5 through successive read cycles, determining the status as described in the previous paragr aph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 6). I/O5: Exceeded Timing Limits I/O5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions I/O5 produces a "1." This is a failure condition that indicates the program or erase cycle was not successfully completed. The device may output a “1” on I/O 5 if the system tries to program a “1” to a location that was previously programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the device halts the operation, and when the timing limit has been exceeded, I/O 5 produces a “1.” . Under both these conditions, the system must write the reset command to return to reading array data (or to the erase- suspend-read mode if a bank was previously in the erase- suspend-program mode). I/O3: Sector Erase Timer After writing a sector erase command sequence, the system may read I/O 3 to determine whether or not an erase operation has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entir e time-out also applies after each additional sector erase command. When the time-out is complete, I/O 3 switches from "0" to "1." The system may ignore I/O 3 if the system can guar antee that the time between additional sector erase commands will always be less than 50 µs. See also the "Sector Erase Command Sequence" section. After the sector erase command sequence is written, the system should read the status on I/O 7 ( Data Polling) or I/O6 (Toggle Bit 1) to ensure the device has accepted the command sequence, and then read I/O 3. If I/O 3 is "1", the internally controlled erase cycle has begun; all further commands (Except Erase Suspend) are ignored until the erase operation is complete. If I/O 3 is "0", the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of I/O 3 prior to and following each subsequent sector erase command. If I/O 3 is high on the second status check, the last command might not have been accepted. Table 13 shows the status of I/O 3 relative to the other status bits.

PRELIMINARY (August, 2005, Version 0.0) 33 AMIC Technology, Corp. Table 13. Write Operation Status

1 No toggle 0 N/A Toggle 1

  1. I/O5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

Refer to the section on I/O5 for more information.

  1. I/O7 and I/O2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
  2. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm

is in progress. The device outputs array data if the system addresses a non-busy bank.

A82DL32x4T(U) Series PRELIMINARY (August, 2005, Version 0.0) 35 AMIC Technology, Corp. DC CHARACTERISTICS CMOS Compatible Parameter Symbol Parameter Description Test Description Min. Typ. Max. Unit ILI Input Load Current VIN = VSS to VCC_F. VCC_F= VCC_F Max ±1.0 µA ILIT A9 Input Load Current VCC = VCC Max, A9 =12.5V 35 µA ILO Output Leakage Current VOUT = VSS to VCC_F. VCC = VCC_F Max ±1.0 µA

5 MHz 10 16 CE_F = VIL, OE = VIH

5 MHz 10 16

ICC1_F VCC_F Active Read Current (Notes 1, 2) CE_F = VIL, OE = VIH Word Mode 1 MHz 2 4 mA ICC2_F VCC_F Active Write Current (Notes 2, 3) CE_F = VIL, OE =VIH 20 30 mA ICC3_F VCC_F Standby Current (Note 2) CE_F = VIH, RESET= VCC_F ± 0.3V 0.2 5 µA ICC4_F VCC_F Reset Current (Note 2) RESET= VSS ± 0.3V 0.2 5 µA ICC5_F Automatic Sleep Mode (Note 2, 4) VIH = VCC_F ± 0.3V; VIL = VSS ± 0.3V 0.2 5 µA Byte 21 45 ICC6_F VCC_F Active Read-While-Program Current (Notes 1, 2) CE_F = VIL, OE = VIH Word 21 45 mA Byte 21 45 ICC7_F VCC_F Active Read-While-Erase Current (Notes 1, 2) CE_F = VIL, OE = VIH Word 21 45 mA ICC8_F VCC_F Active Program-While-Erase-Suspended Current (Notes 2, 5) CE_F = VIL, OE = VIH 17 35 mA ACC pin 5 10 IACC ACC Accelerated Program Current, Word or Byte CE_F = VIL, OE = VIH VCC_F pin 15 30 mA VIL Input Low Level -0.5 0.8 V VIH Input High Level 0.7 x VCC_F VCC_F + 0.3 V VHH Voltage for WP /ACC Sector Protect/Unprotect and Program Acceleration VCC_F = 3.0 V ± 10% 8.5 9.5 V VID Voltage for Autoselect and Temporary Unprotect Sector VCC_F = 3.0 V ± 10% 8.5 12.5 V VOL Output Low Voltage IOL = 4.0mA, VCC_F = VCC_F Min 0.45 V VOH1 IOH = -2.0 mA, VCC_F = VCC_F Min 0.85x VCC_F V VOH2 Output High Voltage IOH = -100 µA, VCC_F = VCC Min VCC_F - 0.4 V VLKO Low VCC_F Lock-Out Voltage (Note 5) 2.3 2.5 V Notes: 1. The ICC current listed is typically less than 2 mA/MHz, withOE at VIH. 2. Maximum ICC specifications are tested with VCC_F = VCC_F max. 3. ICC active while Embedded Algorithm (program or erase) is in progress. 4. Automatic sleep mode enables the low power mode when addresses remain stable for t ACC_F + 30ns. Typical sleep mode current is 200nA. 5. Not 100% tested.

PRELIMINARY (August, 2005, Version 0.0) 37 AMIC Technology, Corp.

  1. See Figure 9 and Table 14 for test specifications.
  2. Measurements performed by placing a 50-ohm termination on the data pin with a bias of (VCC_F)/2. The time from OE high

to the data bus driven to (VCC_F)/2 is taken as tDF. Figure 11. Read Operation Timings

PRELIMINARY (August, 2005, Version 0.0) 38 AMIC Technology, Corp. Figure 12. RESET Timings

A82DL32x4T(U) Series PRELIMINARY (August, 2005, Version 0.0) 40 AMIC Technology, Corp. AC CHARACTERISTICS Erase and Program Operations Parameter Description Speed Unit JEDEC Std -70 tAVAV tWC Write Cycle Time (Note 1) Min. 70 ns tAVWL tAS Address Setup Time Min. 0 ns tASO Address Setup Time to OE low during toggle bit polling 15 ns tWLAX tAH Address Hold Time Min. 45 ns tAHT Address Hold Time From CE_F or OE high during toggle bit polling 0 ns tDVWH tDS Data Setup Time Min. 35 ns tWHDX tDH Data Hold Time Min. 0 ns tOEPH Output Enable High during toggle bit polling Min. 20 ns tGHWL tGHWL Read Recover Time Before Write (OE high to WE low) Min. 0 ns tELWL t CS CE_F Setup Time Min. 0 ns tWHEH tCH CE_F Hold Time Min. 0 ns tWLWH tWP Write Pulse Width Min. 30 ns tWHDL tWPH Write Pulse Width High Min. 30 ns tSR/W Latency Between Read and Write Operations Min. 0 Byte Typ. 5 tWHWH1 t WHWH1 Byte Programming Operation (Note 2) Word Typ. 7 µs tWHWH1 t WHWH1 Accelerated Programming Operation, Word or Byte (Note 2) Typ. 4 sec tWHWH2 t WHWH2 Sector Erase Operation (Note 2) Typ. 0.7 sec tvcs VCC_F Set Up Time (Note 1) Min. 50 µs tRB Recovery Time from RY/BY Min 0 ns tBUSY Program/Erase Valid to RY/BY Delay Min 90 ns Notes: 1. Not 100% tested. 2. See the "Erase and Programming Performance" section for more information.

PRELIMINARY (August, 2005, Version 0.0) 42 AMIC Technology, Corp.

  1. SA = Sector Address (for Sector Erase), VA = Valid Address for reading status data (see "Write Operaion Ststus").
  2. Illustration shows device in word mode.

Figure 17. Chip/Sector Erase Operation Timings

PRELIMINARY (August, 2005, Version 0.0) 45 AMIC Technology, Corp. Figure 22. Temporary Sector/Sector Block Unprotect Timing Diagram

PRELIMINARY (August, 2005, Version 0.0) 46 AMIC Technology, Corp. Figure 23. Sector/Sector Block Protect and Unprotect Timing Diagram

A82DL32x4T(U) Series PRELIMINARY (August, 2005, Version 0.0) 47 AMIC Technology, Corp. AC CHARACTERISTICS Alternate CE_F Controlled Erase and Program Operations Parameter Speed JEDEC Std

Description

-70 Unit tAVAV t WC Write Cycle Time (Note 1) Min. 70 ns tAVEL t AS Address Setup Time Min. 0 ns tELAX t AH Address Hold Time Min. 45 ns tDVEH t DS Data Setup Time Min. 35 ns tEHDX t DH Data Hold Time Min. 0 ns tGHEL t GHEL Read Recover Time Before Write (OE High to WE Low) Min. 0 ns tWLEL t WS WE Setup Time Min. 0 ns tEHWH t WH WE Hold Time Min. 0 ns tELEH t CP CE_F Pulse Width Min. 30 ns tEHEL t CPH CE_F Pulse Width High Min. 30 ns Byte Typ. 5 tWHWH1 t WHWH1 Programming Operation (Note 2) Word Typ. 7 µs tWHWH1 t WHWH1 Accelerated Programming Operation, Word or Byte (Note 2) Typ. 4 µs tWHWH2 t WHWH2 Sector Erase Operation (Note 2) Typ. 0.7 sec Notes: 1. Not 100% tested. 2. See the "Erase and Programming Perfo rmance" section for more information.

PRELIMINARY (August, 2005, Version 0.0) 48 AMIC Technology, Corp. Figure 24. Alternate CE_F Controlled Write (Erase/Program) Operation Timings

  1. Figure indicates last two bus cycl es of a program or erase operation.
  2. PA = program address, SA = sect or address, PD = program data.
  3. 7I/O is the complement of the data written to the device. DOUT is the data written to the device.
  4. Waveforms are for the word mode.

A82DL32x4T(U) Series PRELIMINARY (August, 2005, Version 0.0) 49 AMIC Technology, Corp. SRAM Symbol Parameter - 70 ns Unit Conditions Min. Max. ⎜ILI⎥ Input Leakage Current - 1 µA VIN = GND to VCC_S ⎜ILO⎥ Output Leakage Current - 1 µA CE1_S = VIH or CE2_S = VIL or OE = VIH or WE = VIL VI/O = GND to VCC ICC_S Active Power Supply Current - 3 mA CE1_S = VIL, CE2_S = VIH II/O = 0mA ICC1_S Dynamic Operating - 30 mA Min. Cycle, Duty = 100% CE1_S = VIL, CE2_S = VIH II/O = 0mA ICC2_S Current - 3 mA CE1_S = VIL, CE2_S = VIH VIH = VCC_S, VIL = 0V f = 1 MHZ, II/O = 0mA ISB_S - 0.5 mA VCC_S ≤ 3.3V, CE1_S = VIH or CE2_S =VIL ISB1_S Standby Power Supply Current - 5 µA VCC ≤ 3.3V, CE1_S ≥ VCC - 0.2V or CE2_S ≤ 0.2V, VIN ≥ 0V VOL Output Low Voltage - 0.4 V I OL = 2.1mA VOH Output High Voltage 2.2 - V I OH = -1.0mA Truth Table Mode CE1_S CE2_S OE WE I/O Operation Supply Current Standby H X X X High Z I SB, ISB1 X L X X High Z I SB, ISB1 Output Disable L H H H High Z I CC, ICC1, ICC2 Read L H L H D OUT I CC, ICC1, ICC2 Write L H X L D IN I CC, ICC1, ICC2 Note: X = H or L

A82DL32x4T(U) Series PRELIMINARY (August, 2005, Version 0.0) 50 AMIC Technology, Corp. Capacitance (TA = 25°C, f = 1.0MHz) Symbol Parameter Min. Max. Unit Conditions CIN* Input Capacitance 6 pF V IN = 0V CI/O* Input/Output Capacitance 8 pF V I/O = 0V * These parameters are sampled and not 100% tested.

A82DL32x4T(U) Series PRELIMINARY (August, 2005, Version 0.0) 51 AMIC Technology, Corp. AC Characteristics (TA = -40°C to +85°C, VCC_S = 2.7V to 3.6V) Symbol Parameter -70 ns Unit Min. Max. Read Cycle tRC Read Cycle Time 70 - ns tAA Address Access Time - 70 ns tACE1 Chip Enable Access Time CE1_S - 70 ns tACE2 CE2_S - 70 ns tOE Output Enable to Output Valid - 35 ns tCLZ1 Chip Enable to Output in Low Z CE1_S 10 - ns tCLZ2 CE2_S 10 - ns tOLZ Output Enable to Output in Low Z 5 - ns tCHZ1 Chip Disable to Output in High Z CE1_S 0 25 ns tCHZ2 CE2_S 0 25 ns tOHZ Output Disable to Output in High Z 0 25 ns tOH Output Hold from Address Change 10 - ns Write Cycle tWC Write Cycle Time 70 - ns tCW Chip Enable to End of Write 60 - ns tAS Address Setup Time 0 - ns tAW Address Valid to End of Write 60 - ns tWP Write Pulse Width 50 - ns tWR Write Recovery Time 0 - ns tWHZ Write to Output in High Z 0 25 ns tDW Data to Write Time Overlap 30 - ns tDH Data Hold from Write Time 0 - ns tOW Output Active from End of Write 5 - ns Notes: tCHZ1, t CHZ2, t OHZ, and t WHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels.

A82DL32x4T(U) Series PRELIMINARY (August, 2005, Version 0.0) 52 AMIC Technology, Corp. Timing Waveforms Read Cycle 1 (1, 2, 4) tRC tOH tAA tOH Address DOUT Read Cycle 2 (1, 3, 4, 6) tCLZ15 tACE1 tCHZ15 CE1_S DOUT Read Cycle 3 (1, 4, 7, 8) tCLZ25 tACE2 tCHZ25 CE2_S DOUT

A82DL32x4T(U) Series PRELIMINARY (August, 2005, Version 0.0) 53 AMIC Technology, Corp. Timing Waveforms (continued) Read Cycle 4 (1) tRC Address CE2_S DOUT tAA tOE tOLZ5 tACE1 tCLZ15 tACE2 tCLZ25 tCHZ25 tOHZ5 tCHZ15 tOH CE1_S OE Notes: 1. WE is high for Read Cycle. 2. Device is continuously enabled CE1_S = VIL and CE2_S = VIH. 3. Address valid prior to or coincident with CE1_S transition low. 4. OE = VIL. 5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested. 6. CE2_S is high. 7. CE1_S is low. 8. Address valid prior to or coincident with CE2_S transition high. Write Cycle 1 (6) (Write Enable Controlled) tWC Addres s CE1_S CE2_S DIN tOW tDHtDW tWHZ tWP2tAS1 (4) tCW5 tAW tWR3 WE DOUT (4)

A82DL32x4T(U) Series PRELIMINARY (August, 2005, Version 0.0) 54 AMIC Technology, Corp. Timing Waveforms (continued) Write Cycle 2 (Chip Enable Controlled) tWC Address CE1_S CE2_S DIN tDHtDW (4) (4) tCW5 tAW tWR3 WE DOUT tWHZ 7 tWP2 tCW5 tAS1 Notes: 1. tAS is measured from the address valid to the beginning of Write. 2. A Write occurs during the overlap (t WP) of a low CE1_S, a high CE2_S and a low WE . 3. t WR is measured from the earliest of CE1_S or WE going high or CE2_S going low to the end of the Write cycle. 4. If the CE1_S low transition or the CE2_S high transition occurs simultaneously with the WE low transition or after the WE transition, outputs remain in a high impedance state. 5. t CW is measured from the later of CE1_S going low or CE2_S going high to the end of Write. 6. OE is continuously low. ( OE = VIL) 7. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.

A82DL32x4T(U) Series PRELIMINARY (August, 2005, Version 0.0) 55 AMIC Technology, Corp. SRAM Data Retention Characteristics (TA = -40°C to 85°C) Symbol Parameter Min. Max. Unit Conditions VDR1 2.0 3.6 V CE1_S ≥ VCC - 0.2V VDR2 VCC for Data Retention ICCDR1_S Data Retention Current µA VCC_S = 2V, CE1_S ≥ VCC_S - 0.2V, VIN ≥ 0V ICCDR2_S µA VCC_S = 2V, CE2_S ≤ 0.2V, VIN ≥ 0V tCDR Chip Disable to Data Retention Time 0 - ns See Retention Waveform tR Operation Recovery Time 5 - ms * I CCDR_S: max. 1µA at TA = 0°C to + 40°C Low VCC_S Data Retention Waveform (1) (CE1_S Controlled) VCC_S CE1_S tCDR VIH 3.0V tR VIH 3.0V DATA RETENTION MODE VDR _Σ ≥ 2V CE1_S ≥ VDR - 0.2V Low VCC Data Retention Waveform (2) (CE2_S Controlled) VCC_S CE2_S tCDR VIL 3.0V tR VIL 3.0V DATA RETENTION MODE VDR_S ≥ 2.0V CE2_S ≤ 0.2V

A82DL32x4T(U) Series PRELIMINARY (August, 2005, Version 0.0) 56 AMIC Technology, Corp. ERASE AND PROGRAMMING PERFORMANCE Parameter Typ. (Note 1) Max. (Note 2) Unit Comments Sector Erase Time 0.7 15 sec Chip Erase Time 27 sec Excludes 00h programming prior to erasure (Note 4) Byte Programming Time 5 150 µs Word Programming Time 7 210 µs Accelerated Word/Byte Programming Time 4 120 µs Byte Mode 9 27 sec Chip Programming Time (Note 3) Word Mode 6 18 sec Excludes system-level overhead (Note 5) Notes: 1. Typical program and erase times assume the following conditions: 25 °C, 3.0V VCC_F, 10,000 cycles. Additionally, programming typically assumes checkerboard pattern. 2. Under worst case conditions of 90°C, VCC_F = 2.7V, 100,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum byte program time listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 12 for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 10,000 cycles. FLASH LATCH-UP CHARACTERISTICS Description Min. Max. Input Voltage with respect to VSS on all I/O pins -1.0V VCC_F+1.0V VCC_F Current -100 mA +100 mA Input voltage with respect to VSS on all pins except I/O pins (including A9, OE and RESET) -1.0V 12.5V Includes all pins except VCC_F. Test conditions: VCC_F = 3.0V, one pin at time. DATA RETENTION Parameter Test Conditions Min Unit 150°C 10 Years Minimum Pattern Data Retention Time 125°C 20 Years

A82DL32x4T(U) Series PRELIMINARY (August, 2005, Version 0.0) 57 AMIC Technology, Corp.

Ordering Information

Top Boot Sector Flash & SRAM Part No. Access Time (ns) Bank 1 Bank 2 Package A82DL3224TG-70 69-ball TFBGA A82DL3224TG-70F 69-ball Pb-Free TFBGA A82DL3224TG-70I 69-ball TFBGA A82DL3224TG-70IF 69-ball Pb-Free TFBGA A82DL3224TG-70U 69-ball TFBGA A82DL3224TG-70UF 70 4M 28M 69-ball Pb-Free TFBGA A82DL3234TG-70 69-ball TFBGA A82DL3234TG-70F 69-ball Pb-Free TFBGA A82DL3234TG-70I 69-ball TFBGA A82DL3234TG-70IF 69-ball Pb-Free TFBGA A82DL3234TG-70U 69-ball TFBGA A82DL3234TG-70UF 70 8M 24M 69-ball Pb-Free TFBGA A82DL3244TG-70 69-ball TFBGA A82DL3244TG-70F 69-ball Pb-Free TFBGA A82DL3244TG-70I 69-ball TFBGA A82DL3244TG-70IF 69-ball Pb-Free TFBGA A82DL3244TG-70U 69-ball TFBGA A82DL3244TG-70UF 70 16M 16M 69-ball Pb-Free TFBGA Note: Industrial operating temperature range: -40°C to 85°C for –U; -25°C to 85°C for –I

A82DL32x4T(U) Series PRELIMINARY (August, 2005, Version 0.0) 58 AMIC Technology, Corp. Bottom Boot Sector Flash & SRAM Part No. Access Time (ns) Bank 1 Bank 2 Package A82DL3224UG-70 69-ball TFBGA A82DL3224UG-70F 69-ball Pb-Free TFBGA A82DL3224UG-70I 69-ball TFBGA A82DL3224UG-70IF 69-ball Pb-Free TFBGA A82DL3224UG-70U 69-ball TFBGA A82DL3224UG-70UF 70 4M 28M 69-ball Pb-Free TFBGA A82DL3234UG-70 69-ball TFBGA A82DL3234UG-70F 69-ball Pb-Free TFBGA A82DL3234UG-70I 69-ball TFBGA A82DL3234UG-70IF 69-ball Pb-Free TFBGA A82DL3234UG-70U 69-ball TFBGA A82DL3234UG-70UF 70 8M 24M 69-ball Pb-Free TFBGA A82DL3244UG-70 69-ball TFBGA A82DL3244UG-70F 69-ball Pb-Free TFBGA A82DL3244UG-70I 69-ball TFBGA A82DL3244UG-70IF 69-ball Pb-Free TFBGA A82DL3244UG-70U 69-ball TFBGA A82DL3244UG-70UF 70 16M 16M 69-ball Pb-Free TFBGA Note: Industrial operating temperature range: -40°C to 85°C for –U; -25°C to 85°C for –I

A82DL32x4T(U) Series PRELIMINARY (August, 2005, Version 0.0) 59 AMIC Technology, Corp.

Package Information

69LD STF BGA (8 x 11mm) Outline Dimensions unit: mm 87654321 A B C D E F G H J K -A- -B- Pin #1 D E aaa aaa See Detail A 91 0 e -C- ccc C CAVITY SEATING PLANE SOLDER BALL c A1 A2 A 123 A B C See Detail B b Detail A Detail B C ddd CM eee M A B // bbb C Dimensions in mm Dimensions in inches Symbol Min Nom Max Min Nom Max aaa 0.15 0.006 bbb 0.20 0.008 ccc 0.12 0.005 ddd 0.15 0.006 eee 0.08 0.003 MD/ME 10/10 10/10 Notes: 1. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 2. DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO PRIMARY DATUM C. 3. THERE SHALL BE A MINIMUM CLEARANCE OF 0.25mm BETWEEN THE EDGE OF THE SOLDER BALL AND THE BODY EDGE. 4. REFERENCE DOCUMENT: JEDEC MO-219 5. THE PATTERN OF PIN 1 FIDUCIAL IS FOR REFERENCE ONLY.