A81L801 AMICC | Alldatasheet

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Stacked Multi-chip Package (MCP) 1 M X 8 Bit / 512K X 16 Bit Boot Sector Flash Memory and 128K x 8 Low Voltage CMOS SRAM Preliminary PRELIMINARY (March, 2005, Version 0.0) AMIC Technology, Corp. Document Title Stacked Multi-chip Package (MCP) 1M X 8 Bit / 512K X 16 Bit Boot Sector Flash Memory and 128K x 8 Low Voltage CMOS SRAM

Revision History

Rev. History Issue Date Remark

0.0 Initial issue March 25, 2005 Preliminary

Stacked Multi-chip Package (MCP) 1 M X 8 Bit / 512K X 16 Bit Boot Sector Flash Memory and 128K x 8 Bit Low Voltage CMOS SRAM Preliminary PRELIMINARY (March, 2005, Version 0.0) 1 AMIC Technology, Corp. MCP Features „ Single power supply operation 2.7 to 3.6 volt „ High Performance - Access time as fast as 70ns „ Package - 69-Ball FBGA (8x11x1.4 mm) „ Industrial operating temperature range: -25°C to 85°C for –I Flash Features „ Single power supply operation - Full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications „ Access times: - 70 (max.) „ Current: - 9 mA typical active read current - 20 mA typical program/erase current - 200 nA typical CMOS standby - 200 nA Automatic Sleep Mode current „ Flexible sector architecture - 16 Kbyte/ 8 KbyteX2/ 32 Kbyte/ 64 KbyteX15 sectors - 8 Kword/ 4 KwordX2/ 16 Kword/ 32 KwordX15 sectors - Any combination of sectors can be erased - Supports full chip erase - Sector protection: A hardware method of protecti ng sectors to prevent any inadvertent program or erase operations within that sector. Temporary Sector Unprotect feature allows code changes in previously locked sectors „ Extended operating temperature range: -25°C ~ +85°C for – I series „ Unlock Bypass Program Command - Reduces overall programming time when issuing multiple program command sequence „ Top or bottom boot block configurations available „ Embedded Algorithms - Embedded Erase algorithm wi ll automatically erase the entire chip or any combinati on of designated sectors and verify the erased sectors - Embedded Program algorithm automatically writes and verifies data at specified addresses „ Typical 100,000 program/erase cycles per sector „ 20-year data retention at 125°C - Reliable operation for the life of the system „ Data Polling and toggle bits - Provides a software method of detecting completion of program or erase operations „ Ready / BUSY pin (RY / BY) - Provides a hardware method of detecting completion of program or erase operations „ Erase Suspend/Erase Resume - Suspends a sector erase oper ation to read data from, or program data to, a non-erasing sector, then resumes the erase operation „ Hardware reset pin (RESET ) - Hardware method to reset the device to reading array data LP SRAM Features „ Power supply range: 2.7V to 3.6V „ Access times: 70 ns (max.) „ Current: Very low power version: Operating: 30mA(max.) Standby: 5uA (max.) „ Full static operation, no clock or refreshing required „ All inputs and outputs are directly TTL-compatible „ Common I/O using three-state output „ Output enable and two chips enable inputs for easy application „ Data retention voltage: 2.0V (min.)

PRELIMINARY (March, 2005, Version 0.0) 2 AMIC Technology, Corp. General Description The Flash memory of A81L801 is an 8Mbit, 3.0 volt-only memory organized as 1,048,576 bytes of 8 bits or 524,288 words of 16 bits each. The 8 bits of data appear on I/O 0 - I/O7; the 16 bits of data appear on I/O 0~I/O15. The A81L801 is offered in 69-ball TFBGA package. This device is designed to be programmed in-system with the standard system 3.0 volt VCC supply. Additional 12.0 volt VPP is not required for in- system write or erase operat ions. However, the A81L801 can also be programmed in standard EPROM programmers. The Flash memory of A81L801 has the first toggle bit, I/O 6, which indicates whether an Embedded Program or Erase is in progress, or it is in the Erase Suspend. Besides the I/O 6 toggle bit, the Flash memory of A81L801 also has a second toggle bit, I/O 2, to indicate whether the addressed sector is being selected for erase. The A81L801 also offers the ability to program in the Erase Suspend mode. The standard A81L801 offers access times of 70 and 90ns, allowing high-speed microprocessors to operate without wait states. To eliminate bus contention the device ha s separate chip enables ( CE_F , and CE_S ), write enable ( WE ) and output enable ( OE ) controls. The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provi ded for the program and erase operations. The Flash memory of A81L801 is entirely software command set compatible with the JEDEC single-power-supply Flash standard. Commands are writte n to the command register using standard microprocessor write timings. Register contents serve as input to an internal st ate-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by writing the proper program command sequence. This initiates the Embedded Program algorithm - an internal algorith m that automatically times the program pulse widths and verifies proper program margin. Device erasure occurs by executing the proper erase command sequence. This initiates the Embedded Erase algorithm - an internal algo rithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper erase margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. The host system can detect whether a program or erase operation is complete by observing the RY / BY pin, or by reading the I/O 7 ( Data Polling) and I/O 6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The Flash memo ry of A81L801 is fully erased when shipped from the factory. The hardware sector protection feature disables operations for both program and erase in any combination of the sectors of memory. This can be achieved via programming equipment. The Erase Suspend/Erase Resu me feature enables the user to put erase on hold for any period of time to read data from, or program data to, any other se ctor that is not selected for erasure. True background erase can thus be achieved. The hardware RESET pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system micropro cessor to read the boot-up firmware from the Flash memory. The A81L801 device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes.

PRELIMINARY (March, 2005, Version 0.0) 3 AMIC Technology, Corp. Pin Configurations „ 69-Ball FBGA Top View A5 A6 A10 B3 B4 B5 B6 B7 B8 C3 C4 C5 C6 C7 C8 C9 D4 D4 D5 D6 D7 D8 D9 E3 E4 E7 E8 E9 E10 F3 F4 F7 F8 F9 F10 NC NC NC A7 NC NC WE A8 A11 A6 NC RESET NC NC A12 A15 A5 A18 RY/BY NC A9 A13 NC A4 A17 A10 A14 NC NC VSS I/O 1 I/O6 NC A16 NC Flash only SRAM only Shared E1 E2 F1 F2 NC NC NC A1 NC A0 G3 G4 G5 G6 G7 G8 G9 H3 H4 H5 H6 H7 H8 H9 I/O9 I/O3 I/O4 I/O13 I/O15(A-1) BYTE_ F I/O0 I/O10 VCC_F VCC_S I/O 12 I/O7 VSS CE_F OE CE_S J3 J4 J5 J6 J7 J8 K5 K6 K10 I/O8 I/O2 I/O11 NC I/O 5 I/O14 NC NC NC NC Special Handling Instructions for FBGA Package Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if expo sed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time

PRELIMINARY (March, 2005, Version 0.0) 4 AMIC Technology, Corp. Product Information Guide Part Number A81L801 Speed Options Standard Voltage Range: VCC_F/VCC_S=2.7-3.6V 70 Max Access Time (ns) 70 CE_F / CE_S Access (ns) 70 OE Access (ns) 40 MCP Block Diagram 8M Bit Flash Memory 1M Bit Static RAM VCC_S VSS VCC_F VSS A18 to A0 RY/BY I/O15 (A-1) to I/O0 I/O15 (A-1) to I/O0 I/O15 (A-1) to I/O0 A16 to A0 A18 to A0 BYTE_F RESET CE_F WE OE CE_S

PRELIMINARY (March, 2005, Version 0.0) 5 AMIC Technology, Corp. Flash Memory Block Diagram State Control Command Register Address Latch X-decoder Y-Decoder Chip Enable Output Enable Logic Cell Matrix Y-Gating VCC Detector PGM Voltage Generator Data Latch Input/Output BuffersErase Voltage Generator VCC_F VSS WE OE A0-A18 I/O0 - I/O15 (A-1) Timer STB STB RESET Sector Switches BYTE_F RY/BY CE_F

PRELIMINARY (March, 2005, Version 0.0) 6 AMIC Technology, Corp. SRAM Block Diagram ROW DECODER

512 X 2048

A0 VCC_S VSS OE CE_S

PRELIMINARY (March, 2005, Version 0.0) 7 AMIC Technology, Corp. A17-A0 A-1 CE_F CE_S OE WE RESET BYTE_F RY/BY I/O15-I/O0 16 or 8 Pin Description Logic Symbol Pin No. Description A18-A0 18 Address Inputs (Common) I/O14 - I/O0 15 Data Inputs/Outputs (Common) I/O15 (A-1) I/O15 Data Input/Output, Word Mode A-1 LSB Address Input, Byte Mode CE_F Chip Enable (Flash) CE_S Chip Enable (SRAM) OE Output Enable (Common) WE Write Enable (Common) RY/BY Ready/BUSY - Output RESET Hardware Reset Pin, Active Low BYTE_F Select Byte Mode or Word Mode VCC_F Power Supply (Flash) VCC_S Power Supply (SRAM) VSS Device Ground (Common) NC Pin Not Connected Internally

PRELIMINARY (March, 2005, Version 0.0) 8 AMIC Technology, Corp. Absolute Maximum Ratings* Ambient Temperature with Power Applied . . . -55°C to + 125°C Voltage with Respect to Ground VCC_F/VCC_S . . . . (Note 1) A9, Notes: 1. Minimum DC voltage on input or I/O pins is -0.5V. During voltage transitions, input or I/O pins may undershoot VSS to -2.0V for periods of up to 20ns. Maximum DC voltage on input and I/O pins is VCC_F/V CC_S +0.5V. During voltage transitions, input or I/O pins may overshoot to VCC_F/VCC_S +2.0V for periods up to 20ns. 2. Minimum DC input voltage on A9, OE and RESET is - 0.5V. During voltage transitions, A9, OE and RESET may overshoot VSS to -2.0V for periods of up to 20ns. Maximum DC input voltage on A9 is +12.5V which may overshoot to 14.0V for periods up to 20ns. 3. No more than one output is s horted at a time. Duration of the short circuit should not be greater than one second. *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. Operating Ranges Commercial (C) Devices Extended Range Devices Ambient Temperature (T VCC Supply Voltages Operating ranges define thos e limits between which the functionally of the device is guaranteed. Device Bus Operations This section describes the requi rements and use of the device bus operations, which are init iated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the regi ster serve as inputs to the internal state machine. The st ate machine outputs dictate the function of the device. The appr opriate device bus operations table lists the inputs and cont rol levels required, and the resulting output. The following subsections describe each of these operations in further detail.

PRELIMINARY (March, 2005, Version 0.0) 9 AMIC Technology, Corp. Table 1.1 Device Bus Operations—Flash Word Mode BYTE_F = VIH Operation (Notes 1,2) CE_F CE_S OE WE A0-A18 RESET I/O7-I/O0 I/O 15-I/O8 Read from Flash L H L H A IN H D OUT D OUT Standby H H X X X H High-Z High-Z Output Disable L H H H X H High-Z High-Z Write to Flash (Program/Erase) L H H L A IN H D IN D IN Sector Protect L H H Sector Address, A6=L, A1=H, A0=L H D IN X Sector Unprotect L H L L Sector Address, A6=L, A1=H, A0=L H D IN X Temporary Sector Unprotection X H X X A IN V ID D IN X Flash Reset (Hardware) / Standby X H X X X L High-Z High-Z Boot Block Sector Write Protect X H X X X X X X DOUT D OUT High-Z D OUT Read from SRAM H L L H A IN H DOUT High-Z DIN D IN High-Z D IN Write to SRAM H L H L A IN H DIN High-Z Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5-12.5V, = Pulse input, X = Don’t Care, DIN = Data In, DOUT = Data Out Notes: 1. Other operations except for those indicated in this column are inhibited. 2. Do not apply CE_F = VIL, CE_S = VIL at the same time.

PRELIMINARY (March, 2005, Version 0.0) 10 AMIC Technology, Corp. Table 1.2 Device Bus Operations—Flash Word Mode BYTE_F = VIL Flash Operation (Notes 1,2) CE_F CE_S OE WE I/O15 (A-1) A0-A18 RESET I/O7-I/O0 I/O14-I/O8 Read from Flash L H L H A-1 A IN H D OUT High-Z Standby H H X X X X H High-Z High-Z Output Disable L H H H X X H High-Z High-Z Write to Flash (Program/Erase) L H H L A-1 A IN H D IN High-Z Sector Protect L H V ID L Sector Address, A6=L, A1=H, A0=L VID X High-Z Sector Unprotect L H L H L Sector Address, A6=L, A1=H, A0=L VID Code High-Z Temporary Sector Unprotection X H X X X A IN V ID X High-Z Flash Reset (Hardware)/ Standby X H X X X X L High-Z High-Z Boot Block Sector Write Protect X H X X X X X X High-Z DOUT DOUT D OUT DOUT High-Z High-Z Read from SRAM H L L H High-z A0 H DOUT D OUT DIN DIN D IN DIN High-Z High-Z Write to SRAM H L H L High-z A0 H DIN D IN Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5-12.5V, = Pulse input, X = Don’t Care, DIN = Data In, DOUT = Data Out Notes: 1. Other operations except for those indicated in this column are inhibited. 2. Do not apply CE_F = VIL, CE_S = VIL at the same time.

PRELIMINARY (March, 2005, Version 0.0) 11 AMIC Technology, Corp. Word/Byte Configuration The BYTE_F pin determines whether the I/O pins I/O 15-I/O0 operate in the byte or word configuration. If the BYTE_F pin is set at logic ”1”, the device is in word configuration, I/O 15-I/O0 are active and controlled by CE_F and OE . If the BYTE_F pin is set at logic “0”, the device is in byte configuration, and only I/O 0-I/O7 are active and controlled by CE_F and OE . I/O8-I/O14 are tri-stated, and I/O 15 pin is used as an input for the LSB (A-1) address function. Requirements for Reading Array Data To read array data from the output s, the system must drive the CE_F and OE pins to V IL. CE_F is the power control and selects the device. OE is the output cont rol and gates array data to the output pins. WE should remain at V IH all the time during read operation. The BYTE_F pin determines whether the device outputs array data in words and bytes. The internal state machine is set for reading array data upon device power- up, or after a hardware reset. This ensures that no spurious alteration of the memory cont ent occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs . The device remains enabled for read access until the comm and register contents are altered. See "Reading Array Data" for more information. Refer to the AC Read Operations table for ti ming specifications and to the Read Operations Timings diagram for the timing waveforms, lCC1 in the DC Characteristics table represents the active current specification for reading array data. Writing Commands/Command Sequences To write a command or command sequence (which includes programming data to the devic e and erasing sectors of memory), the system must drive WE and CE_F to V IL, and OE to V IH. For program operations, the BYTE_F pin determines whether the device a ccepts program data in bytes or words, Refer to “Word/Byte Configuration” for more information. The device features an Unlock Bypass mode to facilitate faster programming . Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The “ Word / Byte Program Command Sequence” section has details on programming data to the dev ice using both standard and Unlock Bypass command sequence. An erase operation can erase one sector, multiple sect ors, or the ent ire device. The Sector Address Tables indicate the address range that each sector occupies. A "sector address" consists of the address inputs required to uniquely sele ct a sector. See the "Command Definitions" section for details on erasing a sector or the entire chip, or suspending/resuming the erase operation. After the system writes the auto-select command sequence, the device enters the auto-select mode. The system can then read auto-select codes from the internal register (which is separate from the memory array) on I/O 7 - I/O0. Standard read cycle timings apply in this mode. Refer to the "Auto-select Mode" and "Auto-select Comm and Sequence" sections for more information. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The "AC Characteristics" section contains timing specification tables and timing diagrams for write operations. Program and Erase Operation Status During an erase or program oper ation, the system may check the status of the oper ation by reading the status bits on I/O 7 - I/O0. Standard read cycle timings and I CC read specifications apply. Refer to "Write Operation Status" for more information, and to each AC Characteristics section for timing diagrams. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced , and the outputs are placed in the high impedance state, independent of the OE input. The device enters the CMOS standby mode when the CE_F & RESET pins are both held at VCC_F ± 0.3V. (Note that this is a more restricted voltage range than VIH.) If CE_F and RESET are held at VIH, but not within VCC_F ± 0.3V, the device will be in the standby mode, but the st andby current will be greater. The device requires the standard access time (t CE) before it is ready to read data. If the device is deselected duri ng erasure or programming, the device draws active current until the operation is completed. ICC3 and ICC4 in the DC Characteristics tables represent the standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for t ACC +30ns. The automatic sleep mode is independent of the CE_F , WE and OE control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. I CC4 in the DC Characteristics table repres ents the automatic sleep mode current specification. Output Disable Mode When the OE input is at V IH, output from the device is disabled. The output pins are placed in the high impedance state. RESET : Hardware Reset Pin The RESET pin provides a hardware method of resetting the device to reading array data. When the system drives the RESET pin low for at least a period of t RP, the device immediately terminates any operati on in progress, tri-states all data output pins, and ignores all read/write attempts for the duration of the RESET pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinit iated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET pulse. When RESET is held at VSS ± 0.3V, the device draws CMOS standby current (I CC4). If RESET is held at V IL but not within VSS ± 0.3V, the standby current will be greater.

PRELIMINARY (March, 2005, Version 0.0) 12 AMIC Technology, Corp. system can read data tRH after the RESET pin return to VIH. Table 2. A81L801 Top Boot Block Sector Address Table Address range is A18: A-1 in byte mode and A18: A0 in word mode. See “Word/Byte Configuration” section.

PRELIMINARY (March, 2005, Version 0.0) 13 AMIC Technology, Corp. Table 3. A81L801 Bottom Boot Block Sector Address Table Address range is A18: A-1 in byte mode and A18: A0 in word mode. See “Word/Byte Configuration” section.

PRELIMINARY (March, 2005, Version 0.0) 14 AMIC Technology, Corp. accessed in-system through the command register. details on using the autoselect mode. Table 4. A81L801 Autoselect Codes (High Voltage Method) Note: The autoselect codes may also be accessed in-system via command sequences.

PRELIMINARY (March, 2005, Version 0.0) 15 AMIC Technology, Corp. operations in previously protected sectors. unprotected. See “Autoselect Mode” for details. The device is shipped with all sectors unprotected. unprotected. See "Autoselect Mode" for details. do not initiate a write cycle. and WE must be a logical zero while OE is a logical one. device does not accept commands on the rising edge of WE . array data on the initial power-up. Unprotect mode is activated by setting the RESET pin to V ID. programmed or erased by sele cting the sector addresses. the timing waveforms, for this feature.

  1. All protected sectors unprotected.
  2. All previously protected sectors are protected once again.

Figure 1. Temporary Sector Unprotect Operation

PRELIMINARY (March, 2005, Version 0.0) 16 AMIC Technology, Corp. Figure 2. In-System Sector Protect/Unprotect Algorithms

PRELIMINARY (March, 2005, Version 0.0) 17 AMIC Technology, Corp. Command Definitions Writing specific address and data commands or sequences into the command register init iates device operations. The Command Definitions table defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. All addresses are latched on the falling edge of WE or CE_F , whichever happens later. All data is latched on the rising edge of WE or CE_F , whichever happens first. Refer to the appropriate timing diagrams in the "AC Characteristics" section. Reading Array Data The device is automatically set to reading array data after device power-up. No commands ar e required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, ex cept that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the syst em may once again read array data with the same exception. See "Erase Suspend/Erase Resume Commands" for more information on this mode. The system must issue the reset command to re-enable the device for reading array data if I/O 5 goes high, or while in the autoselect mode. See the "Reset Command" section, next. See also "Requirements for Reading Array Data" in the "Device Bus Operations" section for mo re information. The Read Operations table provides the read parameters, and Read Operation Timings diagram shows the timing diagram. Reset Command Writing the reset command to the device resets the device to reading array data. Addresses bits are don't care for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend). If I/O 5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and dev ices codes, and determine whether or not a sector is pr otected. The Command Definitions table shows the address and data requirements. This method is an alternative to that shown in the Autoselect Codes (High Voltage Method) table, wh ich is intended for PROM programmers and requires VID on address bit A9. The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. The device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. A read cycle at address XX00h retrieves the manufacturer code and another read cycle at XX0 3h retrieves the continuation code. A read cycle at address XX01h returns the device code. A read cycle containing a sector address (SA) and the address 02h in returns 01h if that sector is protected, or 00h if it is unprotected. Refer to the Sector Address tables for valid sector addresses. The system must write the reset command to exit the autoselect mode and return to reading array data. Word/Byte Program Command Sequence The system may program the device by word or byte, depending on the state of the BYTE_F pin. Programming is a four-bus-cycle operation. T he program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not requi red to provide further controls or timings. The device automatic ally provides internally generated program pulses and verify the programmed cell margin. Table 5 shows the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are longer latched. The system can determi ne the status of the program operation by using I/O 7, I/O6, or RY/ BY . See “White Operation Status” for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the progr amming operation. The Byte Program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a “0” back to a “1”. Attempting to do so may halt the operation and set I/O5 to “1”, or cause the Data Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still “0”. Only erase operations can convert a “0” to a “1”.

PRELIMINARY (March, 2005, Version 0.0) 19 AMIC Technology, Corp.

  1. See the appropriate Command Definitions table for erase

3 : Sector Erase Timer" for more information. Figure 4. Erase Operation WE pulse in the command sequence. Suspend command is valid. All other commands are ignored. Status" for information on these status bits. Timing diagram for timing waveforms. time-out period during the se ctor erase command sequence. suspends the erase operation. erase-suspended sectors produces status data on I/O 7 - I/O 0. determine if a sector is actively erasing or is erase-suspended. command can be written after the device has resumed erasing.

PRELIMINARY (March, 2005, Version 0.0) 20 AMIC Technology, Corp. Table 5. A81L801 Command Definitions RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data latches on the rising edge of WE or CE_F pulse, whichever happens first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A18 - A12 select a unique sector.

  1. See Table 1 for description of bus operations.
  2. All values are in hexadecimal.
  3. Except when reading array or autoselect data, all bus cycles are write operation.
  4. Data bits I/O 15~I/O8 are don’t care for unlock and command cycles.
  5. Address bits A18 - A11 are don't cares for unlock and command cycles, unless SA or PA required.
  6. No unlock or command cycles required when reading array data.
  7. The Reset command is required to return to reading array data when device is in the autoselect mode, or if I/O5 goes high (while

the device is providing status data).

  1. The fourth cycle of the autoselec t command sequence is a read cycle.
  2. The data is 00h for an unprotected sector and 01h for a protected sector. See “Autoselect Command Sequence” for more information.
  3. The Unlock Bypass command is required prior to the Unlock Bypass Program command.
  4. The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass mode.
  5. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode.
  6. The Erase Resume command is valid only during the Erase Suspend mode.

PRELIMINARY (March, 2005, Version 0.0) 21 AMIC Technology, Corp. complete, the device outputs the datum programmed to I/O 7. and ignores the selected sectors that are protected. Algorithms) in the "AC Characteri stics" section illustrates this. shows the Data Polling algorithm.

  1. VA = Valid address for programming. During a sector

address is any non-protected sector address. I/O7 may change simultaneously with I/O5. Figure 5. Data Polling Algorithm

PRELIMINARY (March, 2005, Version 0.0) 22 AMIC Technology, Corp. RY/BY : Read/Busy The RY/BY is a dedicated, open-drain output pin that indicates whether an Embedded algorithm is in progress or complete. The RY/BY status is valid after the rising edge of the final WE pulse in the command sequence. Since RY/ BY is an open- drain output, several RY/ BY pins can be tied together in parallel with a pull-up resistor to VCC. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is ready to read array data (including during the Erase Suspend mode), or is in the standby mode. Table 6 shows the outputs for RY/ BY . Refer to “ RESET Timings”, “Timing Waveforms for Program Operation” and “Timing Waveforms for Chip/Sector Erase Operation” for more information. I/O6: Toggle Bit I Toggle Bit I on I/O 6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE pulse in the command sequence (prior to the program or erase operation), and during the sector erase time- out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause I/O 6 to toggle. (The system may use either OE or CE_F to control the read cycles.) When the operation is complete, I/O6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, I/O 6 toggles for approximately 100µs, then returns to reading array data. If not all selected sectors are pr otected, the Embedded Erase algorithm erases the unprotec ted sectors, and ignores the selected sectors that are protected. The system can use I/O 6 and I/O 2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), I/O 6 toggles. When the device enters the Erase Suspend mode, I/O 6 stops toggling. However, the system must also use I/O 2 to determine which sectors are erasing or erase-suspended. Alte rnatively, the system can use I/O7 (see the subsection on " I/O7: Data Polling"). If a program address falls within a protected sector, I/O6 toggles for approximately 2µs after the program command sequence is written, then returns to reading array data. I/O 6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. The Write Operation Status table shows the outputs for Toggle Bit I on I/O 6. Refer to Figure 6 for the toggle bit algorithm, and to the Toggle Bit Timings figure in the "AC Characteristics" section for the timing diagram. The I/O 2 vs. I/O 6 figure shows the differences between I/O 2 and I/O 6 in graphical form. See also the subsection on " I/O2: Toggle Bit II". I/O2: Toggle Bit II The "Toggle Bit II" on I/O 2, when used with I/O 6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE pulse in the command sequence. I/O2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE or CE_F to control the read cycles.) But I/O 2 cannot distinguish whether the sect or is actively erasing or is erase-suspended. I/O6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are se lected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 6 to compare outputs for I/O2 and I/O6. Figure 6 shows the toggle bit algorithm in flowchart form, and the section " I/O 2: Toggle Bit II" explains the algorithm. See also the " I/O 6: Toggle Bit I" subsection. Refer to the Toggle Bit Timings figure for the togg le bit timing diagram. The I/O 2 vs. I/O6 figure shows the differences between I/O 2 and I/O6 in graphical form. Reading Toggle Bits I/O6, I/O2 Refer to Figure 6 for the following discussion. Whenever the system initially begins reading t oggle bit status, it must read I/O7 - I/O 0 at least twice in a row to determine whether a toggle bit is toggling. Typically, a system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bi t is not toggling, the device has completed the program or eras e operation. The system can read array data on I/O7 - I/O0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of I/O 5 is high (see the section on I/O 5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as I/O5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and I/O 5 has not gone high. The system may continue to monitor the toggle bit and I/O 5 through successive read cycles, determining the status as described in the previous paragr aph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginni ng of the algorithm when it returns to determine the status of the operation (top of Figure 6). I/O5: Exceeded Timing Limits I/O5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions I/O5 produces a "1." This is a failure condition that indicates the program or erase cycle was not successfully completed. The I/O 5 failure condition may appear if the system tries to program a "1 "to a location that is previously programmed to "0." Only an erase operation can change a "0" back to a "1." Under this condition, the device halts the operation, and when the operation has exceeded the timing limits, I/O 5 produces a "1." Under both these conditions, the system must issue the reset command to return the device to reading array data.

PRELIMINARY (March, 2005, Version 0.0) 23 AMIC Technology, Corp. Erase Command Sequence" section.

  1. Read toggle bit twice to determine whether or not it is
  2. Recheck toggle bit because it may stop toggling as I/O

Figure 6. Toggle Bit Algorithm

PRELIMINARY (March, 2005, Version 0.0) 24 AMIC Technology, Corp. Table 6. Write Operation Status

  1. I/O 7 and I/O2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
  2. I/O5 switches to “1” when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See

“I/O5: Exceeded Timing Limits” for more information.

PRELIMINARY (March, 2005, Version 0.0) 25 AMIC Technology, Corp. DC Characteristics CMOS Compatible (TA=0°C to 70°C or -25°C to + 85°C for –I) Parameter Symbol Parameter Description Test Description Min. Typ. Max. Unit ILI Input Load Current VIN = VSS to VCC_F. VCC_F = VCC_F Max ±1.0 µA ILIT A9 Input Load Current VCC_F = V CC_F Max, A9 =12.5V 35 µA ILO Output Leakage Current VOUT = VSS to VCC_F. VCC_F = VCC_F Max ±1.0 µA

5 MHz 9 16 CE_F = VIL, OE = VIH

5 MHz 9 16

ICC1 VCC_F Active Read Current (Notes 1, 2) CE_F = VIL, OE = VIH Word Mode 1 MHz 2 4 mA ICC2 VCC_F Active Write (Program/Erase) Current (Notes 2, 3, 4) CE_F = VIL, OE =VIH 20 30 mA ICC3 VCC_F Standby Current (Note 2) CE_F = VIH, RESET= VCC_F ± 0.3V 0.2 5 µA ICC4 VCC_F Standby Current During Reset (Note 2) RESET= VSS ± 0.3V 0.2 5 µA ICC5 Automatic Sleep Mode (Note 2, 4, 5) VIH = VCC_F ± 0.3V; VIL = VSS ± 0.3V 0.2 5 µA VIL Input Low Level -0.5 0.8 V VIH Input High Level 0.7 x VCC_F VCC_F + 0.3 V VID Voltage for Autoselect and Temporary Unprotect Sector VCC_F = 3.3 V 11.5 12.5 V VOL Output Low Voltage IOL = 4.0mA, VCC_F = VCC_F Min 0.45 V VOH1 IOH = -2.0 mA, VCC_F = VCC_F Min 0.85 x VCC_F V VOH2 Output High Voltage IOH = -100 µA, VCC_F = VCC_F Min VCC_F - 0.4 V Notes: 1. The ICC current listed is typically less than 2 mA/MHz, withOE at VIH. Typical VCC_F is 3.0V. 2. Maximum ICC specifications are tested with VCC_F = VCC_F max. 3. ICC active while Embedded Algorithm (program or erase) is in progress. 4. Automatic sleep mode enables the low power mode when addresses remain stable for t ACC + 30ns. Typical sleep mode current is 200nA. 5. Not 100% tested.

PRELIMINARY (March, 2005, Version 0.0) 26 AMIC Technology, Corp. DC Characteristics (continued) Zero Power Flash 0 500 1000 1500 2000 2500 3000 3500 4000 Time in ns Supply Current in mA Note: Addresses are switching at 1MHz ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) 12 3 4 5 Frequency in MHz Supply Current in mA C25T :Note °= Typical ICC1 vs. Frequency 3.6V 2.7V

PRELIMINARY (March, 2005, Version 0.0) 27 AMIC Technology, Corp. AC Characteristics Read Only Operations (TA=0°C to 70°C or -25°C to + 85°C for –I) Parameter Symbols Speed JEDEC Std Description Test Setup -70 Unit tAVAV t RC Read Cycle Time (Note 1) Min. 70 ns tAVQV tACC Address to Output Delay CE_F = VIL OE = VIL Max. 70 ns tELQV TCE_F Chip Enable to Output Delay OE = VIL Max. 70 ns tGLQV t OE Output Enable to Output Delay Max. 30 ns Read Min. 0 ns tOEH Output Enable Hold Time (Note 1) Toggle and Data Polling Min. 10 ns tEHQZ tDF Chip Enable to Output High Z (Notes 1) Max. 25 ns tGHQZ tDF Output Enable to Output High Z (Notes 1) 25 ns tAXQX t OH Output Hold Time from Addresses, CE or OE , Whichever Occurs First (Note 1) Min. 0 ns Notes: 1. Not 100% tested. 2. See Test Conditions and Test Setup for test specifications. Timing Waveforms for Read Only Operation Addresses Addresses Stable CE_F OE WE Output Valid High-ZOutput tRC tOEH tOE tCE High-Z tOH tDF tACC RESET RY/BY

PRELIMINARY (March, 2005, Version 0.0) 28 AMIC Technology, Corp. AC Characteristics Hardware Reset (RESET ) (TA=0°C to 70°C or -25°C to + 85°C for –I) Parameter JEDEC Std Description Test Setup All Speed Options Unit tREADY RESET Pin Low (During Embedded Algorithms) to Read or Write (See Note) Max 20 µs tREADY RESET Pin Low (Not During Embedded Algorithms) to Read or Write (See Note) Max 500 ns tRP RESET Pulse Width Min 500 ns tRH RESET High Time Before Read (See Note) Min 50 ns tRB RY/BY Recovery Time Min 0 ns tRPD RESET Low to Standby Mode Min 20 µs Note: Not 100% tested. RESET Timings CE_F, OE RESET tRH tRP tReady Reset Timings NOT during Embedded Algorithms RESET tRP Reset Timings during Embedded Algorithms RY/BY tRB tReady CE_F, OE RY/BY

PRELIMINARY (March, 2005, Version 0.0) 29 AMIC Technology, Corp. Temporary Sector Unprotect (TA=0°C to 70°C or -25°C to + 85°C for –I) Parameter JEDEC Std Description All Speed Options Unit tVIDR V ID Rise and Fall Time (See Note) Min 500 ns tRSP RESET Setup Time for Temporary Sector Unprotect Min 4 µs Note: Not 100% tested. Temporary Sector Unprotect Timing Diagram Program or Erase Command Sequence RESET 12V 0 or 3V tVIDR tVIDR 0 or 3V tRSP CE_F WE RY/BY

PRELIMINARY (March, 2005, Version 0.0) 30 AMIC Technology, Corp. AC Characteristics Word/Byte Configuration (BYTE_F) (TA=0°C to 70°C or -25°C to + 85°C for – I) Parameter Speed Option JEDEC Std

Description

-70 Unit tELFL/tELFH CE_F to BYTE_F Switching Low or High Max 5 ns tFLQZ BYTE_F Switching Low to Output High-Z Max 25 ns tHQV BYTE_F Switching High to Output Active Min 70 ns BYTE_F Timings for Read Operations BYTE_F Timings for Write Operations Note: Refer to the Erase/Program Operations table for tAS and tAH specifications. The falling edge of the last WE signal tHOLD(tAH) tSET (tAS) CE_F BYTE_F WE Data Output (I/O0-I/O14) Data Output (I/O0-I/O7) I/O15 Output Address Input Data Output (I/O0-I/O14) Data Output (I/O0-I/O7) I/O15 OutputAddress Input tFHQV tFLQZ tELFH tELFL CE_F OE BYTE_F I/O0-I/O14 I/O15 (A-1) BYTE_F I/O0-I/O14 I/O15 (A-1) BYTE_F Switching from word to byte mode BYTE_F Switching from byte to word mode

PRELIMINARY (March, 2005, Version 0.0) 31 AMIC Technology, Corp. AC Characteristics Erase and Program Operations (TA=0°C to 70°C or -25°C to + 85°C for –I) Parameter Speed JEDEC Std -70 Unit tAVAV tWC Write Cycle Time (Note 1) Min. 70 ns tAVWL tAS Address Setup Time Min. 0 ns tWLAX tAH Address Hold Time Min. 45 ns tDVWH tDS Data Setup Time Min. 35 ns tWHDX tDH Data Hold Time Min. 0 ns tOES Output Enable Setup Time Min. 0 ns tGHWL tGHWL Read Recover Time Before Write (OE high to WE low) Min. 0 ns tELWL t CS CE_F Setup Time Min. 0 ns tWHEH tCH CE_F Hold Time Min. 0 ns tWLWH tWP Write Pulse Width Min. 35 ns tWHWL tWPH Write Pulse Width High Min. 30 ns Byte Typ. 5 tWHWH1 t WHWH1 Byte Programming Operation (Note 2) Word Typ. 7 µs tWHWH2 t WHWH2 Sector Erase Operation (Note 2) Typ. 0.7 sec tvcs VCC_F Set Up Time (Note 1) Min. 50 µs tRB Recovery Time from RY/BY Min 0 ns tBUSY Program/Erase Valid to RY/BY Delay Min 90 ns Notes: 1. Not 100% tested. 2. See the "Erase and Programming Performance" section for more information.

PRELIMINARY (March, 2005, Version 0.0) 32 AMIC Technology, Corp. Timing Waveforms for Program Operation Addresses CE_F OE WE DATA VCC_F A0h PD tWC PA Program Command Sequence (last two cycles) PA DOUT ~~~~ PA Status tAS tVCS Read Status Data (last two cycles) 555h tAH tWHWH1 tCH tWP tWPHtCS tDS tDH Note : 1. PA = program addrss, PD = program data, Dout is the true data at the program address. 2. Illustration shows device in word mode. tRB tBUSY RY/BY

PRELIMINARY (March, 2005, Version 0.0) 33 AMIC Technology, Corp. Addresses CE_F OE WE Data VCC_F 55h 30h tWC SA Erase Command Sequence (last two cycles) VA Complete ~~~~ VA In Progress tAS tVCS Read Status Data 2AAh tAH tWHWH2 tCH tWP tWPH tCS tDS tDH Note : 1. SA = Sector Address (for Sector Erase), VA = Valid Address for reading status data (see "Write Operaion Ststus"). 2. Illustratin shows device in word mode. 555h for chip erase 10h for chip erase tRBtBUSY RY/BY Timing Waveforms for Chip/Sector Erase Operation

PRELIMINARY (March, 2005, Version 0.0) 34 AMIC Technology, Corp. Timing Waveforms for Data Polling (During Embedded Algorithms) Addresses CE_F OE WE I/O7 tRC VAVA VA Complement ~~ Complement True Valid Data High-Z Status Data ~~ Status Data True Valid Data High-Z I/O0 - I/O6 tACC tCE_F tCH tOE tOEH tDF tOH Note : VA = Valid Address. Illustation shows first status cycle after command sequence, last status read cycle, and array data read cycle. tBUSY RY/BY High-Z

PRELIMINARY (March, 2005, Version 0.0) 35 AMIC Technology, Corp. Timing Waveforms for Toggle Bit (During Embedded Algorithms) Addresses CE_F OE WE I/O6 , I/O2 tRC VAVA VA Valid Status tACC tCE_F tCH tOE tOEH tDF tOH VA Valid Status Valid Status Valid Data (first read) (second read) (stop togging) RY/BY tBUSY High-Z Note: VA = Valid Address; not required for I/O 6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle. Timing Waveforms for Sector Protect/Unprotect VID Note : For sector protect, A6=0, A1=1, A0=0. For sector unprotect, A6=1, A1=1, A0=0 VIHRESET SA, A6, A1, A0 Data CE_F WE OE Valid* Valid* Valid* 60h 60h 40h Status Sector Protect/Unprotect Verify 1us Sector Protect:150us Sector Unprotect:15ms

PRELIMINARY (March, 2005, Version 0.0) 36 AMIC Technology, Corp. Timing Waveforms for I/O2 vs. I/O6 AC Characteristics Erase and Program Operations Alternate CE_F Controlled Writes (TA=0°C to 70°C or -25°C to + 85°C for –I) Parameter Speed JEDEC Std -70 Unit tAVAV t WC Write Cycle Time (Note 1) Min. 70 ns tAVEL t AS Address Setup Time Min. 0 ns tELAX t AH Address Hold Time Min. 45 ns tDVEH t DS Data Setup Time Min. 35 ns tEHDX t DH Data Hold Time Min. 0 ns t OES Output Enable Setup Time Min. 0 ns tGHEL t GHEL Read Recover Time Before Write (OE High to WE Low) Min. 0 ns tWLEL t WS WE Setup Time Min. 0 ns tEHWH t WH WE Hold Time Min. 0 ns tELEH t CP CE Pulse Width Min. 35 ns tEHEL t CPH CE Pulse Width High Min. 30 ns Byte Typ. 5 tWHWH1 t WHWH1 Programming Operation (Note 2) Word Typ. 7 µs tWHWH2 t WHWH2 Sector Erase Operation (Note 2) Typ. 0.7 sec Notes: 1. Not 100% tested. 2. See the "Erase and Programming Perfo rmance" section for more information. Enter Embedded Erasing Erase Suspend Enter Erase Suspend Program Erase Resume WE I/O6 I/O2 Erase Erase Suspend Read Erase Suspend Read Erase Erase Complete I/O2 and I/O6 toggle with OE and CE_F Note : Both I/O6 and I/O2 toggle with OE or CE_F. See the text on I/O6 and I/O2 in the section "Write Operation Status" for more information. Erase Suspend Program ~~~~

PRELIMINARY (March, 2005, Version 0.0) 37 AMIC Technology, Corp. Timing Waveforms for Alternate CE_F Controlled Write Operation Addresses WE OE CE_F Data 555 for program 2AA for erase PA DOUT ~~~~ I/O7 Data Polling Note : 1. PA = Program Address, PD = Program Data, SA = Sector Address, I/O7 = Complement of Data Input, DOUT = Array Data. 2. Figure indicates the last two bus cycles of the command sequence. PD for program 30 for sector erase 10 for chip erase tBUSY tWHWH1 or 2 tAH tAStWC tWH tCP tWS tCPH PA for program SA for sector erase 555 for chip erase A0 for program 55 for erase tRH tDS tDH ~~~~ RESET RY/BY Erase and Programming Performance Parameter Typ. (Note 1) Max. (Note 2) Unit Comments Sector Erase Time 1.0 8 sec Chip Erase Time 35 sec Excludes 00h programming prior to erasure Byte Programming Time 35 300 µs Word Programming Time 12 500 µs Byte Mode 11 33 sec Chip Programming Time (Note 3) Word Mode 7.2 21.6 sec Excludes system-level overhead (Note 5) Notes: 1. Typical program and erase times assume the following conditions: 25 °C, 3.0V VCC_F, 10,000 cycles. Additionally, programming typically assumes checkerboard pattern. 2. Under worst case conditions of 90°C, VCC_F = 2.7V, 100,000 cycles. 3. The typical chip programming time is considerably less t han the maximum chip programming time listed, since most bytes program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then does the device set I/O5 = 1. See the section on I/O5 for further information. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time r equired to execute the four-bus-cycle comm and sequence for programming. See Table 5 for further information on command definitions. 6. The device has a guaranteed minimum erase and program cycle endurance of 10,000 cycles.

PRELIMINARY (March, 2005, Version 0.0) 38 AMIC Technology, Corp. SRAM Symbol Parameter 70ns Unit Conditions Min. Max. ⎜ILI⎥ Input Leakage Current - 1 µA VIN = GND to VCC_S ⎜ILO⎥ Output Leakage Current - 1 µA CE_S = VIH or OE = VIH or WE = VIL VI/O = GND to VCC_S ICC Active Power Supply Current - 3 mA CE_S = VIL II/O = 0mA ICC1 Dynamic Operating - 30 mA Min. Cycle, Duty = 100% CE_S = VIL, CE2 = VIH II/O = 0mA ICC2 Current - 3 mA CE_S = VIL VIH = VCC_S, VIL = 0V f = 1 MHZ, II/O = 0mA ISB - 0.5 mA VCC_S ≤ 3.3V, CE_S = VIH ISB1 Standby Power Supply Current - 5 µA VCC_S ≤ 3.3V, CE_S ≥ VCC_S - 0.2V or VIN ≥ 0V VOL Output Low Voltage - 0.4 V I OL = 2.1mA VOH Output High Voltage 2.2 - V I OH = -1.0mA Truth Table Mode CE_S OE WE I/O Operation Supply Current Standby H X X High Z I SB, ISB1 X X X High Z I SB, ISB1 Output Disable L H H High Z I CC, ICC1, ICC2 Read L L H D OUT I CC, ICC1, ICC2 Write L X L D IN I CC, ICC1, ICC2 Note: X = H or L

PRELIMINARY (March, 2005, Version 0.0) 39 AMIC Technology, Corp. Capacitance (TA = 25°C, f = 1.0MHz) Symbol Parameter Min. Max. Unit Conditions CIN* Input Capacitance 6 pF V IN = 0V CI/O* Input/Output Capacitance 8 pF V I/O = 0V * These parameters are sampled and not 100% tested. AC Characteristics (TA = -25°C to +85°C, VCC_S = 2.7V to 3.6V) Symbol Parameter 70 ns Unit Min. Max. Read Cycle tRC Read Cycle Time 70 - ns tAA Address Access Time - 70 ns tACE1_S Chip Enable Access Time CE_S - 70 ns tOE Output Enable to Output Valid - 35 ns tCLZ1 Chip Enable to Output in Low Z CE_S 10 - ns tOLZ Output Enable to Output in Low Z 5 - ns tCHZ1 Chip Disable to Output in High Z CE_S 0 25 ns tOHZ Output Disable to Output in High Z 0 25 ns tOH Output Hold from Address Change 10 - ns Write Cycle tWC Write Cycle Time 70 - ns tCW Chip Enable to End of Write 60 - ns tAS Address Setup Time 0 - ns tAW Address Valid to End of Write 60 - ns tWP Write Pulse Width 50 - ns tWR Write Recovery Time 0 - ns tWHZ Write to Output in High Z 0 25 ns tDW Data to Write Time Overlap 30 - ns tDH Data Hold from Write Time 0 - ns tOW Output Active from End of Write 5 - ns Notes: tCHZ1, t OHZ, and t WHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels.

PRELIMINARY (March, 2005, Version 0.0) 40 AMIC Technology, Corp. SRAM Timing Waveforms Read Cycle 1 (1, 2, 4) tRC tOH tAA tOH Address DOUT Read Cycle 2 (1, 3, 4, 6) tCLZ15 tACE1 tCHZ15 CE_S DOUT

PRELIMINARY (March, 2005, Version 0.0) 41 AMIC Technology, Corp. Timing Waveforms (continued) Read Cycle 3 (1) tRC Address CE_S DOUT tAA tOE tOLZ tACE1 tACE2 tCLZ25 tCHZ25 tOHZ5 tOH OE Notes: 1. WE is high for Read Cycle. 2. Device is continuously enabled CE_S = VIL. 3. Address valid prior to or coincident with CE_S transition low. 4. OE = VIL. 5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested. 6. CE_S is low. Write Cycle 1 (6) (Write Enable Controlled) tWC Address CE_S DIN tOW tDHtDW tWHZ tWP2tAS1 (4) tCW5 tAW tWR3 WE DOUT

PRELIMINARY (March, 2005, Version 0.0) 42 AMIC Technology, Corp. Timing Waveforms (continued) Write Cycle 2 (Chip Enable Controlled) tWC Address CE_S DIN tDHtDW (4) tCW5 tAW tWR3 WE DOUT tWHZ7 tCW5 tAS1 Notes: 1. tAS is measured from the address valid to the beginning of Write. 2. A Write occurs during the overlap (t WP) of a low CE_S , and a low WE . 3. t WR is measured from the earliest of CE_S or WE going high going low to the end of the Write cycle. 4. If the CE_S low transition occurs simultaneously with the WE low transition or after the WE transition, outputs remain in a high impedance state. 5. t CW is measured from the later of CE_S going low going high to the end of Write. 6. OE is continuously low. ( OE = VIL) 7. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.

PRELIMINARY (March, 2005, Version 0.0) 43 AMIC Technology, Corp.

  • Including scope and jig. * Including scope and jig.

Figure 7. Output Load Figure 8. Output Load for t CLZ1,

PRELIMINARY (March, 2005, Version 0.0) 44 AMIC Technology, Corp. Low VCC Data Retention Waveform (1) (CE_S Controlled) VCC_S CE_S tCDR VIH 3.0V tR VIH 3.0V DATA RETENTION MODE VDR ≥ 1.5V CE_S ≥ VDR - 0.2V

PRELIMINARY (March, 2005, Version 0.0) 45 AMIC Technology, Corp.

Ordering Information

Top Boot Sector Flash & SRAM Part No. Access Time (ns) Active Read Current Typ. (mA) Program/Erase Current Typ. (mA) Standby Current Typ. (µA) Package A81L801TG-70 69-ball FBGA A81L801TG-70F 69-ball Pb-Free FBGA A81L801TG-70I 69-ball FBGA A81L801TG-70IF 70 9 20 0.2 69-ball Pb-Free FBGA Note: Industrial operating temperature range: -25°C to 85°C for –I Bottom Boot Sector Flash & SRAM Part No. Access Time (ns) Active Read Current Typ. (mA) Program/Erase Current Typ. (mA) Standby Current Typ. (µA) Package A81L801UG-70 69-ball FBGA A81L801UG-70F 69-ball Pb-Free FBGA A81L801UG-70I 69-ball FBGA A81L801UG-70IF 70 9 20 0.2 69-ball Pb-Free FBGA Note: Industrial operating temperature range: -25°C to 85°C for –I

PRELIMINARY (March, 2005, Version 0.0) 46 AMIC Technology, Corp.

Package Information

69LD STF BGA (8 x 11mm) Outline Dimensions unit: mm 87654321 A B C D E F G H J K -A- -B- Pin #1 D E aaa aaa See Detail A 91 0 e -C- ccc C CAVITY SEATING PLANE SOLDER BALL c A1 A2 A 123 A B C See Detail B b Detail A Detail B C ddd CM eee M A B // bbb C Dimensions in mm Dimensions in inches Symbol Min Nom Max Min Nom Max aaa 0.15 0.006 bbb 0.20 0.008 ccc 0.12 0.005 ddd 0.15 0.006 eee 0.08 0.003 MD/ME 10/10 10/10 Notes: 1. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 2. DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO PRIMARY DATUM C. 3. THERE SHALL BE A MINIMUM CL EARANCE OF 0.25mm BETWEEN THE EDGE OF THE SOLDER BALL AND THE BODY EDGE. 4. REFERENCE DOCUMENT : JEDEC MO-219 5. THE PATTERN OF PIN 1 FIDUCIAL IS FOR REFERENCE ONLY.