A8032 AMICC | Alldatasheet

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Preliminary 8 Bit Microcontroller PRELIMINARY (November, 1998, Version 0.0) AMIC Technology, Inc. Document Title

8 Bit Microcontroller

Revision History

Rev. No. History Issue Date Remark

0.0 Initial issue November 27, 1998

Preliminary 8 Bit Microcontroller PRELIMINARY (November, 1998, Version 0.0) 1 AMIC Technology, Inc.

Features

n 8-bit CMOS microcontroller nFully static design with power saving idle mode and power down mode nLow standby current at full supply voltage n Versions for 12/24/40MHZ operating frequency n On chip 256B RAM n Four 8-bit bidirectional ports nThree 16-bit Timers/Counters (Timer 2 with up/down counter feature) nOne full duplex serial port nBoolean processor n Six interrupt sources, two priority levels n Available in 40-pin P-DIP and 44-pin PLCC packages n 64K bytes external data memory space General Description The AMIC A8032 is a high-performance 8-bit microcontroller. It is compatible with the industry standard 80C52 microcontroller series. The A8032 contains a 256B RAM , four 8-bit bidirectional parallel ports, three 16-bit timer/counters, a serial port and six interrupt sources with two priority levels. The A8032 has supports 64KB external data memory. Pin Configurations n P-DIP n PLCC T2,P1.0 T2EX,P1.1 P1.2 TXD,P3.1 XTAL2 XTAL1 GND P0.2,AD2 P0.1,AD1 P0.0,AD0 VCC A8032 P0.3,AD3 P1.3 P1.4 P1.6 P1.7 RST RXD,P3.0 T1,P3.5 INT0,P3.2 P1.5 PSEN ALE EA P0.7,AD7 P0.6,AD6 P0.5,AD5 P0.4,AD4 A8032L P1.5 P1.4 INT1,P3.3 T0,P3.4 WR,P3.6 RD,P3.7 P2.7,A15 P2.6,A14 P2.5,A13 P2.4,A12 P2.3,A11 P2.2,A10 P2.1,A9 P2.0,A8 P1.3 P1.2 P1.1,T2EX P1.0,T2 GND VCC P0.0,AD0 P0.1,AD1 P0.2,AD2 P0.3,AD3 P1.6 P1.7 RST RXD,P3.0 NC TXD,P3.1 INT0, P3.2 INT1,P3.3 T0,P3.4 T1,P3.5 P0.4,AD4 EA NC ALE PSEN P2.7,A15 P2.6,A14 P2.5,A13 P0.5,AD5 P0.6,AD6 P0.7,AD7 WR,P3.6 RD,P3.7 XTAL2 XTAL1 GND NC P2.0,A8 P2.1,A9 P2.2,A10 P2.3,A11 P2.4,A12

PRELIMINARY (November, 1998, Version 0.0) 2 AMIC Technology, Inc. Block Diagram CPU CORE TIMING AND CONTROL SFR PSEN ALE EA RST OSCILLATOR XTAL1 XTAL2 PORT 0 P0.0-P0.7 ADDRESS (AD0-AD7) PORT 2 P2.0-P2.7 ADDRESS A8-A15 256B RAM PORT 1 TIMER 2 INTERRUPT SERIAL PORT TIMER 0.1 PORT 3

PRELIMINARY (November, 1998, Version 0.0) 3 AMIC Technology, Inc. Pin Description Pin No. Symbol I/O Description I/O Port1. Port1 is a bidirectional I/O port with internal pull-ups. Pin P1.0 and P1.1 also provide alternate functions as follows: I/O P1.0 T2 Timer/Counter2 external input/clock out 1 - 8 P1.0 - P1.7 I P1.1 T2EX Timer/Counter2 capture/reload input 9 RST I Reset input, active high. It must be kept high for at least two machine cycles to be recognized by the processor 10 - 17 P3.0 - P3.7 I/O Port3. Port3 is a bidirectional I/O port with internal pull-ups. Port3 pins also serve alternate functions as follows: I P3.0 RXD Serial receive port O P3.1 TXD Serial transmit port I P3.2 INT0 External interrupt 0 I P3.3 INT1 External interrupt 1 I P3.4 T0 Timer/Counter 0 input I P3.5 T1 Timer/Counter 1 input O P3.6 WR External data memory write strobe O P3.7 RD External data memory read strobe 18 XTAL2 O Crystal2. This is the output of crystal oscillator. It is the inversion of XTAL1 19 XTAL1 I Crystal1. This is the input of crystal oscillator. It can be driven by an external clock

20 GND I Ground

21 - 28 P2.0 - P2.7 I/O Port2. Port2 is a bidirectional I/O port with internal pull-ups. Port2 is also the multiplexed upper-order address bus during accesses to external data memory 29 PSEN O Program Store Enable, active low. The read strobe to external program memory. PSEN is activated in each machine cycle when fetching external program memory 30 ALE O Address latch enable, active high. ALE is used to enable the address latch that separates the data on Port 0 31 EA I External Access enable, active low. It is held low to enable the device to fetch code from external program memory 32 - 39 P0.7 - P0.0 I/O Port0. Port0 is an open drain, bidirectional I/O port. Port0 is also the multiplexed low-order address bus during accesses to external data memory

40 VCC I Power supply

PRELIMINARY (November, 1998, Version 0.0) 5 AMIC Technology, Inc. Recommended DC Operating Conditions (TA = -25°C to + 85°C) Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage 4.5 5.0 5.5 V GND Ground 0 0 0 V VIH* Input High Voltage 2.4 - VCC+0.2 V VIL Input Low Voltage 0 - 0.8 V * XTAL1 is a CMOS input. RESET is a Schmit trigger input. The min. of VIH is 3.5 Volts for these two pins. Absolute Maximum Ratings* Power Dissipation1* 1* : Operating frequency is 40MHZ *Comments Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. Symbol Parameter Min. Max. Unit Conditions ILI 1 Input Leakage Current - 10 µA VIN = GND to VCC ILO  Output Leakage Current - 10 µA VI/O = GND to VCC ICC Operating Current - 50 mA foper = 40MHZ External oscillator is on XTAL1 pin No load VOL1 Output Low Voltage (PORT1, PORT2 and PORT3) - 0.45 V IOL = 2mA VOL2 Output Low Voltage (ALE, PSEN and PORT0) - 0.45 V IOL = 4mA VOH1 Output High Voltage (PORT1, PORT2 and PORT3) 2.4 - V IOH = -100µA VOH2 Output High Voltage (ALE, PSEN and PORT0) 2.4 - V IOH = -400µA C1 Input Pin Capacitance - 10 pF 1MHZ , 25°C 1. For RESET pin, the ILI  max. is 300 µA, since it has an internal pull-low of approx. 30KΩ resistor.

PRELIMINARY (November, 1998, Version 0.0) 6 AMIC Technology, Inc. AC Characteristics (TA = -25°C to + 85°C, VCC = 5V ± 10%) Symbol Parameter Min. Max. Unit Program Memory Cycle tAP ALE Pulse Width 2tck – 20 1 - ns tALS Address Valid to ALE Low 1tck - ns tALH Address Hold from ALE Low 1tck - ns top PSEN Pulse Width 3tck - 201 - ns tAO ALE Low to PSEN Low 1tck - ns tOI2 PSEN Low to Valid Instruction in - 2tck ns tIDO Input Instruction Hold after PSEN High - 1tck ns tIFO Input Instruction Float after PSEN High - 1tck ns External Clock fOPER Clock Frequency 0 40 MHZ tCK3 Clock Period 25 - ns tCKH4 Clock High Time 10 - ns tCKL4 Clock Low Time 10 - ns Data Memory Cycle tPR RD Pulse Width 6tck - 201 - ns tPD RD Low to Valid Data in - 4tck ns tDHR Data Hold from RD High 0 2tck ns tDFR Data Float from RD High 0 2tck ns tAR ALE Low to RD Low 3tck 3tck + 201 ns tWP WR Pulse Width 6tck - 201 - ns tDS Valid Data to WR Low 1tck - ns tDHW Data Hold from WR High 1tck - ns tAW ALE Low to WR Low 3tck 3tck + 201 ns Serial Port Cycle tSCK Serial Port Clock 12tck - ns tKI Clock Rising Edge to Valid Input Data - 11tck ns tIKH Input Data to Serial Clock Rising Clock Hold Time 0 - ns tOKS Output Data to Serial Clock Rising Edge Setup Time 11tck - ns tOKH Output Data to Serial Clock Rising Edge Hold Time 1tck - ns 1. This 20 ns is due to buffer driving delay and wire loading. 2. Instruction cycle time is 12 tck. 3. tck = 1/ foper 4. There are no duty cycle requirements on the XTAL1 input.

PRELIMINARY (November, 1998, Version 0.0) 7 AMIC Technology, Inc. Timing Waveforms Program Memory Cycle Clock Input Waveform tAP S1 S2 S3 S4 S5 S6 S1 XTAL 1 ALE tAO PSEN PORT 2 A8 - A15 A8 - A15 tOP tALS A0 - A7 A0 - A7PORT 0 tALH tOI tIHO tIFO INSTRUCTION IN INSTRUCTION IN XTAL 1 tCKH tCKL tCK

PRELIMINARY (November, 1998, Version 0.0) 8 AMIC Technology, Inc. Timing Waveforms (continued) Data Memory Read Cycle Data Memory Write Cycle Serial Port Timing – Shift Register Mode tDHR A0-A7 S4 S5 S6 S1 S2 S3 S4 XTAL 1 S5 S6 ALE PSEN PORT 2 A8-A15 DATA IN A0-A7PORT 0 RD tAR tRD tDFRtRP tDS tDHW A0-A7 S4 S5 S6 S1 S2 S3 S4 XTAL 1 S5 S6 ALE PSEN PORT 2 A8-A15 PORT 0 tWP DATA OUT tAW WR 0 1 2 3 4 5 6 7 8INSTRUCTION tSCK tOKS tOKH tKI tIKH VALID VALID VALID VALID VALID VALID VALID VALID 0 1 2 3 4 5 6 7 SET TI SET RI ALE CLOCK OUTPUT DATA INPUT DATA

PRELIMINARY (November, 1998, Version 0.0) 9 AMIC Technology, Inc.

Ordering Information

Part No. RAM FREQ (MHZ) Package A8032-12 256 Byte 12 40L P-DIP A8032L-12 256 Byte 12 44L PLCC A8032-24 256 Byte 24 40L P-DIP A8032L-24 256 Byte 24 44L PLCC A8032-40 256 Byte 40 40L P-DIP A8032L-40 256 Byte 40 44L PLCC

PRELIMINARY (November, 1998, Version 0.0) 10 AMIC Technology, Inc.

Package Information

P-DIP 40L Outline Dimensions unit: inches/mm Dimensions in inches Dimensions in mm Symbol Min Nom Max Min Nom Max B 0.018 TYP 0.457 TYP B1 0.050 TYP 1.270 TYP e1 0.100 TYP 2.540 TYP Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E1 does not include resin fins. AL E eA D C θ 0º/15º B Base Plane Seating Plane

PRELIMINARY (November, 1998, Version 0.0) 11 AMIC Technology, Inc. PLCC 44L Outline Dimension unit: inches/mm Dimensions in inches Dimensions in mm Symbol Min Nom Max Min Nom Max Notes: 1. Dimensions D and E do not include resin fins. 2. Dimensions GD & GE are for PC Board surface mount pad pitch design reference only. HD D 18 28 E HE 44 40 A1 A2 A e GD Seating Plane b1 b 0.150 REF0.020 MIN L 0.630/0.590 0.050 REF 0.022/0.016 0.032/0.026 GE C 0.630/0.590 0.014/0.0008 D 0.004 y