AM29SL800D_07 AMD | Alldatasheet

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Publication Number 27546 Revision A Amendment 6 Issue Date January 23, 2007 The following document contains information on Spansion memory products. Although the document is marked with the name of the company that orig inally developed the specification, Spansion will continue to offer these products to existing customers. Continuity of Specifications There is no change to this data sheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal data sheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary. Continuity of Ordering Part Numbers Spansion continues to support existing part numbers beginning with “Am” and “MBM”. To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local sales office for additional information about Spansion memory solutions. Am29SL800D Data Sheet

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This Data Sheet states AMD’s current specifications regarding the Products described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Publication# 27546 Rev: A Amendment/6 Issue Date: January 23, 2007 Am29SL800D

8 Megabit (1 M x 8-Bit/512 K x 16-Bit)

CMOS 1.8 Volt-only Super Low Voltage Flash Memory DISTINCTIVE CHARACTERISTICS „ Single Power Supply Operation — 1.65 to 2.2 V for read, program, and erase operations — Ideal for battery-powered applications „ Manufactured on 0.23 µm Process Technology — Compatible with 0.32 µm Am29SL800C device „ High Performance — Access times as fast as 90 ns „ Ultra Low Power Consumption (Typical Values at

5 MHz)

— 0.2 µA Automatic Sleep Mode current — 0.2 µA standby mode current — 5 mA read current — 15 mA program/erase current „ Flexible Sector Architecture — One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and fifteen 64 Kbyte sectors (byte mode) — One 8 Kword, two 4 Kword, one 16 Kword, and fifteen 32 Kword sectors (word mode) — Supports full chip erase — Sector Protection Features: A hardware method of locking a sector to prevent any program or erase operations within that sector Sectors can be locked in-system or via programming equipment Temporary Sector Unprotect feature allows code changes in previously locked sectors „ Unlock Bypass Program Command — Reduces overall programming time when issuing multiple program command sequences „ Top or Bottom Boot Block Configurations Available „ Embedded Algorithms — Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors — Embedded Program algorithm automatically writes and verifies data at specified addresses „ Minimum 1,000,000 Erase Cycle Guarantee Per Sector „ 20-Year Data Retention at 125°C „ Package Option — 48-pin TSOP — 48-ball FBGA „ Compatibility with JEDEC Standards — Pinout and software compatible with single- power supply Flash — Superior inadvertent write protection „ Data# Polling and Toggle Bits — Provides a software method of detecting program or erase operation completion „ Ready/Busy# Pin (RY/BY#) — Provides a hardware method of detecting program or erase cycle completion „ Erase Suspend/Erase Resume — Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation „ Hardware Reset Pin (RESET#) — Hardware method to reset the device to reading array data

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The Am29SL800D is an 8 Mbit, 1.8 V volt-only Flash- memory organized as 1,048,576 bytes or 524,288 words. The device is offered in 48-pin TSOP and 48- ball FBGA packages. The word-wide data (x16) appears on DQ15–DQ0; the byte-wide (x8) data appears on DQ7–DQ0. This device is designed to be programmed and erased in-system with a single 1.8 volt V CC supply. No VPP is for write or erase operations. The device can also be programmed in standard EPROM programmers. The standard device offers access times of 90, 100, 120, and 150 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus conten- tion, the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. The device requires only a single 1.8 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard . Com- mands are written to the command register using standard microprocessor write timings. Register con- tents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that auto- matically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facili- tates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm—an internal algorithm that automati- cally preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low V CC detector that automatically inhibits write opera- tions during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achi eved in-system or via pro- gramming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode . The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes. AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effective- ness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection.

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Notes: 1. See “AC Characteristics” for full specifications. 2. V CC min. = 1.7 V BLOCK DIAGRAM Family Part Number Am29SL800D Speed Options 90 (Note 2) 100 120 150 Max access time, ns (tACC)9 0 ( Note 2) 100 120 150 Max CE# access time, ns (tCE)9 0 ( Note 2) 100 120 150 Max OE# access time, ns (tOE) 3 03 55 06 5 Input/Output Buffers X-Decoder Y-Decoder Chip Enable Output Enable Logic Erase Voltage Generator PGM Voltage Generator TimerVCC Detector State Control Command Register VCC VSS WE# BYTE# CE# OE# STB STB DQ0–DQ15 (A-1) Sector Switches RY/BY# RESET# Data Latch Y-Gating Cell Matrix Address LatchA0–A18

January 23, 2007 27546A6 Am29SL800D 5 CONNECTION DIAGRAMS Special Handling Instructions for FBGA Packages Special handling is required for Flash Memory products in molded packages (TSOP and BGA). The package and/or data integrity may be compromised if the package body is exposed to temperatures about 150°C for prolonged periods of time. A15 A18 A14 A13 A12 A11 A10 NC NC WE# RESET# NC NC RY/BY# A17 A16 DQ2 BYTE# V SS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 Standard TSOP A1 B1 C1 D1 E1 F1 G1 H1 A2 B2 C2 D2 E2 F2 G2 H2 A3 B3 C3 D3 E3 F3 G3 H3 A4 B4 C4 D4 E4 F4 G4 H4 A5 B5 C5 D5 E5 F5 G5 H5 A6 B6 C6 D6 E6 F6 G6 H6 DQ15/A-1 V SSBYTE#A16A15A14A12A13 DQ13 DQ6DQ14DQ7A11A10A8A9 VCC DQ4DQ12DQ5NCNCRESET#WE# DQ11 DQ3DQ10DQ2NCA18NCRY/BY# DQ9 DQ1DQ8DQ0A5A6A17A7 OE# V SSCE#A0A1A2A4A3 48-Ball FBGA (Top View, Balls Facing Down)

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A0–A18 = 19 addresses DQ0–DQ14 = 15 data inputs/outputs DQ15/A-1 = DQ15 (data input/output, word mode), A-1 (LSB address input, byte mode) BYTE# = Selects 8-bit or 16-bit mode CE# = Chip enable OE# = Output enable WE# = Write enable RESET# = Hardware reset pin, active low RY/BY# = Ready/Busy# output V CC = 1.65–2.2 V single power supply VSS = Device ground NC = Pin not connected internally LOGIC SYMBOL 16 or 8 DQ0–DQ15 (A-1) A0–A18 CE# OE# WE# RESET# BYTE# RY/BY#

January 23, 2007 27546A6 Am29SL800D 7

ORDERING INFORMATION

AMD standard products are available in several packages and operating ranges. The order number (Valid Combi- nation) is formed by a combination of the elements below. Valid Combinations Valid Combinations list configurations planned to be supported in vol- ume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly re- leased combinations. Am29SL800D T -100 E C TEMPERATURE RANGE C = Commercial (0°C to +70°C) D = Commercial (0°C to +70°C) with Pb-free package I = Industrial (–40 °C to +85°C) F = Industrial (–40 °C to +85°C) with Pb-free package PACKAGE TYPE E = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048) VU = 48-ball Fine-Pitch Ball Grid Array (FBGA) 0.80mm pitch, 8.15 x 6.15 mm package (VBK048) WA = 48-Ball Fine-Pitch Ball Grid Array (FBGA) 0.80 mm pitch, 8.15 x 6.15 mm package (FBA048) WC = 48-Ball Fine-Pitch Ball Grid Array (FBGA) 0.80 mm pitch, 9 x 8 mm package (FBC048) SPEED OPTION See Product Selector Guide and Valid Combinations BOOT CODE SECTOR ARCHITECTURE T = Top Sector B = Bottom Sector DEVICE NUMBER/DESCRIPTION Am29SL800D

8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS Flash Memory

1.8 Volt-only Read, Program, and Erase

Valid Combinations for TSOP Packages AM29SL800DT90, AM29SL800DB90 EC, EI, ED, EF AM29SL800DT100, AM29SL800DB100 AM29SL800DT120, AM29SL800DB120 AM29SL800DT150, AM29SL800DB150 Valid Combinations for FBGA Packages Order Number Package Marking AM29SL800DT90, AM29SL800DB90 WAC, WAD WAI, WAF A800DT90U, A800DB90U C, I, D, F WCC, WCD, WCI, WCF A800DT90P , A800DB90P AM29SL800DT100, AM29SL800DB100 WAC, WAD WAI, WAF A800DT10U, A800DB10U WCC, WCD, WCI, WCF A800DT10P , A800DB10P AM29SL800DT120, AM29SL800DB120 WAC, WAD WAI, WAF A800DT12U, A800DB12U WCC, WCD, WCI, WCF A800DT12P , A800DB12P AM29SL800DT150, AM29SL800DB150 WAC, WAD WAI, WAF A800DT15U, A800DB15U WCC, WCD, WCI, WCF A800DT15P , A800DB15P Am29SL800DT120 VUF A800DT12V A800DB12V

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describe each of these operations in further detail.

  1. Addresses are A18:A0 in word mode (BYTE# = V IH), A18:A-1 in byte mode (BYTE# = VIL).
  2. The sector protect and sector unprotect functions may also be implemented via programming equipment.

used as an input for the LSB (A-1) address function. register contents are altered. Table 1. Am29SL800D Device Bus Operations

0.2 V XX VCC ±

0.2 V X High-Z High-Z High-Z

January 23, 2007 27546A6 Am29SL800D 9 words. Refer to Word/Byte Configuration‚ on page 8 for more information. The device features an Unlock Bypass mode to facili- tate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The Word/Byte Program Command Sequence‚ on page 15 has details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sec- tors, or the entire device. Tables 2 and 3 indicate the address space that each sector occupies. A “sector address” consists of the address bits required to uniquely select a sector. The Command Definitions‚ on page 14 has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode‚ on page 12 and Autoselect Command Sequence‚ on page 15 sec- tions for more information. I CC2 in the DC Characteristics table represents the active current specification for the write mode. AC Characteristics‚ on page 28 contains timing specifica- tion tables and timing diagrams for write operations. Program and Erase Operation Status During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7–DQ0. Standard read cycle timings and I CC read specifications apply. Refer to Write Operation Status‚ on page 20 for more information, and to “AC Characteristics” for timing diagrams. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, inde- pendent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V CC ± 0.2 V. (Note that this is a more restricted voltage range than V IH.) If CE# and RESET# are held at VIH, but not within VCC ± 0.2 V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (t CE) for read access when the device is in either of these standby modes, before it is ready to read data. The device also enters the standby mode when the RESET# pin is driven low. Refer to the next section, RESET#: Hardware Reset Pin. If the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. I CC3 in Table 7 on page 25 represents the standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for t ACC + 50 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. I CC4 in Table 7 on page 25 represents the automatic sleep mode current specification. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of reset- ting the device to reading array data. When the RESET# pin is driven low for at least a period of t RP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be rein itiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at V SS±0.2 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within V SS±0.2 V, the standby current is greater. The RESET# pin may be tied to the system reset cir- cuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firm- ware from the Flash memory. If RESET# is asserted during a program or erase oper- ation, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of t READY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed within a time of t READY (not during Embedded Algo- rithms). The system can read data t RH after the RESET# pin returns to VIH.

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Table 2. Am29SL800DT Top Boot Block Sector Address Table

Table 3. Am29SL800DB Bottom Boot Block Sector Address Table

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through the command register. read the corresponding identifier code on DQ7–DQ0. command register, as shown in Table 5 on page 19 . L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care. first sector unprotect write cycle. The device is shipped with all sectors unprotected. AMD representative for details. the timing diagrams, for this feature. Table 4. Am29SL800D Autoselect Code (High Voltage Method)

Figure 1. In-System Sector Protect/Unprotect Algorithms

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Figure 2. Temporary Sector Unprotect Operation WE# do not initiate a write cycle. reset to reading array data on power-up. AC Characteristics‚ on page 28 section. more information on this mode.

  1. All protected sectors unprotected.
  2. All previously pr otected sectors are protected once again.

January 23, 2007 27546A6 Am29SL800D 15 The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to read ing array data (also applies to autoselect during Erase Suspend). If DQ5 goes high during a program or erase operation, writing the reset comman d returns the device to reading array data (also applies during Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. Table 5 on page 19 shows the address and data requirements. This method is an alternative to that shown in Table 4 on page 12 , which is intended for PROM programmers and requires V ID on address bit A9. The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. The device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. A read cycle at address XX00h retrieves the manufacturer code. A read cycle at address 01h in word mode (or 02h in byte mode) returns the device code. A read cycle containing a sector address (SA) and the address 02h in word mode (or 04h in byte mode) returns 01h if that sector is protected, or 00h if it is unprotected. Refer to Table 2 on page 10 and Table 3 on page 11 for valid sector addresses. The system must write the reset command to exit the autoselect mode and return to reading array data. Word/Byte Program Command Sequence The system may program the device by word or byte, depending on the state of the BYTE# pin. Program- ming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or tim- ings. The device automatically generates the program pulses and verifies the programmed cell margin. Table 5 on page 19 shows the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. See Table on page 20 for infor- mation on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program- ming operation. The Byte Program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a “0” back to a “1”. Attempting to do so may halt the operation and set DQ5 to “1”, or cause the Data# Polling algorithm to indicate the operation was suc- cessful. However, a succeeding read will show that the data is still “0”. Only erase operations can convert a “0” to a “1”. Unlock Bypass Command Sequence The unlock bypass feature allows the system to program bytes or words to the device faster than using the standard program command sequence. The unlock bypass command sequence is in itiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two- cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total program- ming time. Table 5 on page 19 shows the requirements for the command sequence. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the data 90h; the second cycle the data 00h. Addresses are don’t cares. The device then returns to reading array data.

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Figure 17, on page 32 for timing diagrams.

  1. See Table 5 for program command sequence.

Figure 3. Program Operation the chip erase command sequence. Operation Status” for information on these status bits. ters, and to Figure 10, on page 26 for timing diagrams. requirements for the sector erase command sequence. timings during these operations.

January 23, 2007 27546A6 Am29SL800D 17 this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. If the time between additional sector erase commands can be assumed to be less than 50 µs, the system need not monitor DQ3. Any command other than Sector Erase or Erase Suspend during the time-out period resets the device to reading array data. The system must rewrite the command sequence and any additional sector addresses and commands. The system can monitor DQ3 to determine if the sector erase timer has timed out. (See DQ3: Sector Erase Timer‚ on page 22.) The time-out begins from the rising edge of the final WE# pulse in the command sequence. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. Note that a hardware reset during the sector erase operation immediately terminates the operation. The Sector Erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. (Refer to Write Operation Status‚ on page 20 for information on these status bits.) Figure 4, on page 18 illustrates the algorithm for the erase operation. Refer to the Table 16 on page 39 for parameters, and to Figure 18, on page 33 for timing diagrams. Erase Suspend/Erase Resume Commands The Erase Suspend comma nd allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation, including the 50 µs time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algo- rithm. Writing the Erase Suspend command during the Sector Erase time-out immediately terminates the time-out period and suspends the erase operation. Addresses are “don’t-cares” when writing the Erase Suspend command. When the Erase Suspend command is written during a sector erase operation, the device requires a maximum of 20 µs to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately ter- minates the time-out period and suspends the erase operation. After the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.) Normal read and write timings and command definitions apply. Reading at any address within erase-suspended sectors produces status data on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-sus- pended. See Write Operation Status‚ on page 20 for information on these status bits. After an erase-suspended program operation is com- plete, the system can once again read array data within non-suspended sectors. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program oper- ation. See Write Operation Status‚ on page 20 for more information. The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. See Autoselect Command Sequence‚ on page 15 for more information. The system must write the Erase Resume command (address bits are don’t care) to exit the erase suspend mode and continue the sector erase operation. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the device has resumed erasing.

18 Am29SL800D 27546A6 January 23, 2007

  1. See Table 5 for erase command sequence.
  2. See “DQ3: Sector Erase Timer” for more information.

Figure 4. Erase Operation

RA = Address of the memory location to be read. RD = Data read from location RA during read operation. rising edge of WE# or CE# pulse, whichever happens first. erased. Address bits A18–A12 uniquely select any sector.

  1. See Table 1 for description of bus operations.
  2. All values are in hexadecimal.
  3. Except when reading array or aut oselect data, all bus cycles are
  4. Data bits DQ15–DQ8 are don’t cares for unlock and command
  5. Address bits A18–A11 are don’t cares for unlock and command

cycles, unless SA or PA required.

  1. No unlock or command cycles required when reading array data,
  2. The Reset command is required to return to reading array data

the device is providing status data).

  1. The fourth cycle of the autoselect command sequence is a read
  2. The data is 00h for an unprotected sector and 01h for a protected
  3. The Unlock Bypass command is required prior to the Unlock
  4. The Unlock Bypass Reset command is required to return to

reading array data when the device is in the unlock bypass mode.

  1. The system may read and program in non-erasing sectors, or enter the

command is valid only during a sector erase operation.

  1. The Erase Resume command is valid only during the Erase Suspend

Table 5. Am29SL800D Command Definitions

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progress. These three bits are discussed first. Suspend mode, Data# Polling produces a 1 on DQ7. the selected sectors that are protected. Algorithms), illustrates this. on DQ7. Figure 5 shows the Data# Polling algorithm.

  1. VA = Valid address for progra mming. During a sector erase

non-protected sector address.

  1. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may

change simultaneously with DQ5. Figure 5. Data# Polling Algorithm

22 Am29SL800D 27546A6 January 23, 2007

determine the status of the operation (top of Figure 6).

  1. Read toggle bit twice to determine whether or not it is toggling.
  2. Recheck toggle bit because it ma y stop toggling as DQ5 changes

Figure 6. Toggle Bit Algorithm the timing limits, DQ5 produces a 1. Sector Erase Command Sequence‚ on page 16. accepted the command sequence, and then read DQ3. pend) are ignored until the erase operation is complete. accepted. Figure 6 shows the outputs for DQ3.

  1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See “DQ5:

Exceeded Timing Limits for more information.

  1. DQ7 and DQ2 require a valid addres s when reading status information. Refer to the appropriate subsection for further details.

Table 6. Write Operation Status

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  1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage

or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns.

  1. Minimum DC input voltage on pins A9, OE#, and RESET# is –0.5

12.5 V for periods up to 20 ns.

  1. No more than one output may be shorted to ground at a time.

conditions for extended periods may affect device reliability. of the device is guaranteed. Figure 7. Maximum Negative Overshoot Waveform Figure 8. Maximum Positive Overshoot Waveform

  1. The I CC current listed is typically less than 1 mA/MHz, with OE# at VIH. Typical VCC is 2.0 V.
  2. The maximum I CC specifications are tested with VCC = VCCmax.
  3. I CC active while Embedded Erase or Embedded Program is in progress.
  4. Automatic sleep mode enables the low power mode when addresses remain stable for t ACC + 50 ns.

Table 7. CMOS Compatible

5 MHz 5 10

1 MHz 1 3

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Figure 9. I CC1 Current vs. Time (Showing Active and Automatic Sleep Currents) Figure 10. Typical I CC1 vs. Frequency

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Notes: 1. Not 100% tested. 2. See Figure 11, on page 27 and Table 8 on page 27 for test specifications 3. V CC min. = 1.7V Table 10. Read Operations

Description

JEDEC Std Test Setup -90 -100 -120 -150 Unit tAVAV tRC Read Cycle Time (Note 1) Min 90 (Note 3) 100 120 150 ns tAVQV tACC Address to Output Delay CE# = VIL OE# = VIL Max 90 (Note 3) 100 120 150 ns tELQV tCE Chip Enable to Output Delay OE# = V IL Max 90 (Note 3) 100 120 150 ns tGLQV tOE Output Enable to Output Delay Max 30 35 50 65 ns tEHQZ tDF Chip Enable to Output High Z (Note 1) Max 16 ns tGHQZ tDF Output Enable to Output High Z (Note 1) Max 16 ns tOEH Output Enable Hold Time (Note 1) Read Min 0 ns Toggle and Data# Polling Min 30 ns tAXQX tOH Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First (Note 1) Min 0 ns tCE Outputs WE# Addresses CE# OE# HIGH Z Output Valid HIGH Z Addresses Stable tRC tACC tOEH tOE

0 VRY/BY#

RESET# tD tO Figure 13. Read Operations Timings

Table 11. Hardware Reset (RESET#) Figure 14. RESET# Timings

30 Am29SL800D 27546A6 January 23, 2007

Table 12. Word/Byte Configuration (BYTE#) JEDEC Std -90 -100 -120 -150 Unit tELFL/tELFH CE# to BYTE# Switching Low or High Max 10 ns tFLQZ BYTE# Switching Low to Output HIGH Z Max 50 50 60 60 ns tFHQV BYTE# Switching High to Output Active Min 90 100 120 150 ns DQ15 Output Data Output CE# OE# BYTE# tELFL DQ0–DQ14 Data Output (DQ0–DQ14) DQ15/A-1 Address Input tFLQZ BYTE# Switching from word to byte mode DQ15 Output Data Output BYTE# tELFH DQ0–DQ14 Data Output (DQ0–DQ14) DQ15/A-1 Address Input tFHQV BYTE# Switching from byte to word mode Figure 15. BYTE# Timing s for Read Operations Note: Refer to the Erase/Program Operations table for tAS and tAH specifications. Figure 16. BYTE# Timings for Write Operations

  1. See the Table 16 on page 39 for more information.

Table 13. Erase/Program Operations

32 Am29SL800D 27546A6 January 23, 2007

  1. PA = program address, PD = program data, D OUT is the true data at the program address.
  2. Illustration shows device in word mode.

Figure 17. Program Operation Timings

  1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).
  2. Illustration shows device in word mode.

Figure 18. Chip/Sector Er ase Operation Timings

34 Am29SL800D 27546A6 January 23, 2007

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. Figure 19. Data# Polling Timings (During Embedded Algorithms) Figure 20. Toggle Bit Timings (During Embedded Algorithms)

36 Am29SL800D 27546A6 January 23, 2007

Figure 23. Sector Protect/U nprotect Timing Diagram

January 23, 2007 27546A6 Am29SL800D 37 AC CHARACTERISTICS Notes: 1. Not 100% tested. 2. See the “Erase and Programming Performance” section for more information. Table 15. Alternate CE# Controlled Erase/Program Operations JEDEC Std -90 -100 -120 -150 Unit tAVAV tWC Write Cycle Time (Note 1) Min 90 100 120 150 ns tAVEL tAS Address Setup Time Min 0 ns tELAX tAH Address Hold Time Min 45 50 60 70 ns tDVEH tDS Data Setup Time Min 45 50 60 70 ns tEHDX tDH Data Hold Time Min 0 ns tOES Output Enable Setup Time Min 0 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE# Pulse Width Min 45 50 60 70 ns tEHEL tCPH CE# Pulse Width High Min 30 ns tWHWH1 tWHWH1 Programming Operation (Notes 1, 2) Byte Typ 5 µs Word Typ 7 tWHWH2 tWHWH2 Sector Erase Operation (Notes 1, 2) Typ 0.7 sec

38 Am29SL800D 27546A6 January 23, 2007

  1. PA = program address, PD = program data, DQ7# = complement of the data written, D OUT = data written
  2. Figure indicates the last two bus cycles of command sequence.
  3. Word mode address used as an example.

Figure 24. Alternate CE# Controlled Write Operation Timings

  1. Typical program and erase times assume the following conditions: 25 °C, 2.0 V VCC, 1,000,000 cycles. Additionally, programming typicals

assume checkerboard pattern.

  1. Under worst case conditions of 90°C, V CC = 1.8 V, 1,000,000 cycles.
  2. The typical chip programming time is cons iderably less than the maximum chip programming time listed, since most bytes program faster

than the maximum program times listed.

  1. In the pre-programming step of the Embedded Erase algorit hm, all bytes are programmed to 00h before erasure.
  2. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 5 for further

information on command definitions.

  1. The device has a minimum guaranteed erase and program cycle endurance of 1,000,000 cycles.

Includes all pins except VCC. Test conditions: VCC = 1.8 V, one pin at a time.

  1. Sampled, not 100% tested.
  2. Test conditions T A = 25°C, f = 1.0 MHz.

Table 16. Erase and Programming Performance Table 17. Latchup Characteristics Table 18. TSOP Pin Capacitance Table 19. Data Retention

40 Am29SL800D 27546A6 January 23, 2007

TS 048—48-Pin Standard TSOP Dwg rev AA; 10/99

January 23, 2007 27546A6 Am29SL800D 41 PHYSICAL DIMENSIONS FBA048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 8.15 X 6.15 mm Package Dwg rev AF; 10/99

42 Am29SL800D 27546A6 January 23, 2007

FBC048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 9 x 8 mm Package Dwg rev AF; 10/99

January 23, 2007 27546A6 Am29SL800D 43 PHYSICAL DIMENSIONS VBK048—48 Ball Fine-Pitch Ball Grid Array (FBGA) 8.15 x 6.15 mm 3338 \\ 16-038.25b NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT AS NOTED). 4. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE "E" DIRECTION. N IS THE TOTAL NUMBER OF SOLDER BALLS.

6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C.

7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS

A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW PARALLEL TO THE D OR E DIMENSION, RESPECTIVELY, SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. NOT USED. 9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED B ALLS.

10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK

MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. PACKAGE VBK 048 JEDEC N/A 8.15 mm x 6.15 mm NOM PACKAG E SYMBOL MIN NOM MAX NOT E A --- --- 1.00 OVERALL THICKNESS A1 0.18 --- --- BALL HEIGHT A2 0.62 --- 0.76 BODY THICKNESS D 8.15 BSC. BODY SIZE E 6.15 BSC. BODY SIZE D1 5.60 BSC. BALL FOOTPRINT E1 4.00 BSC. BALL FOOTPRINT MD 8 ROW MATRIX SIZE D DIRECTION ME 6 ROW MATRIX SIZE E DIRECTION N 48 TOTAL BALL COUNT fb 0.35 --- 0.43 BALL DIAMETER e 0.80 BSC. BALL PITCH SD / SE 0.40 BSC. SOLDER BALL PLACEMEN T --- DEPOPULATED SOLDER BALLS SIDE VIEW TOP VIEW SEATING PLAN E A2A (4X)0.10 D E C0.10 A1 C B A C0.08 BOTTOM VIEW A1 CORNER BAMf 0.15 C M e SE SD ABCDEFG H fb Cf 0.08 PIN A1 CORNER INDEX MARK

44 Am29SL800D 27546A6 January 23, 2007

Revision A (February 4, 2003) Initial release. Revision A+1 (March 17, 2003) Corrected typo in table. Corrected typo to OPNs. Revision A+2 (June 10, 2004) Added Pb-free package OPNs. Revision A+3 (October 27, 2004) Updated VCC values Revision A+4 (April 27, 2005) Added VBK048 package. Added Colophon. Updated Trademark. Revision A+5 (February 17, 2006) Global Removed Reverse TSOP throughout. Revision A6 (January 23, 2007) Erase and Program Operations table Changed tBUSY to a maximum specification. Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limita- tion, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as con- templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion Inc. will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. Y ou must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au- thorization by the respective government entity will be required for export of those products. Trademarks Copyright © 2003–2005 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trade- marks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. Copyright © 2006–2007 Spansion Inc. All Rights Reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, HD-SIM, and combinations thereof are trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners.