A67P8318

A67P8318 AMICC | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 18

Technical content

Preliminary 256K X 18, 128K X 36 LVTTL, Pipelined ZeBLTM SRAM PRELIMINARY (July, 2005, Version 0.0) AMIC Technology, Corp. Document Title 256K X 18, 128K X 36 LVTTL, Pipelined ZeBL TM SRAM

Revision History

Rev. No. History Issue Date Remark

0.0 Initial issue July 13, 2005 Preliminary

Preliminary 256K X 18, 128K X 36 LVTTL, Pipelined ZeBLTM SRAM PRELIMINARY (July, 2005, Version 0.0) 2 AMIC Technology, Corp.

Features

„ Fast access time: „ Zero Bus Latency between READ and WRITE cycles allows 100% bus utilization „ Signal +2.5V ± 5% power supply „ Individual Byte Write control capability „ Clock enable ( CEN) pin to enable clock and suspend operations „ Clock-controlled and regi stered address, data and control signals „ Registered output for pipelined applications „ Three separate chip enables allow wide range of options for CE control, address pipelining „ Internally self-timed write cycle „ Selectable BURST mode (Linear or Interleaved) „ SLEEP mode (ZZ pin) provided „ Available in 100 pin LQFP package General Description The AMIC Zero Bus Latency (ZeBL TM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. The A67P8318, A67P7336 SRAMs integrate a 256K X 18, 128K X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bi t burst counter. These SRAMs are optimized for 100 percent bus utilization without the insertion of any wait cycles during Write-Read alternation. The positive edge triggered single clock input (CLK) controls all synchronous inputs passing through the registers. The synchronous inputs include all address, all data inputs, active low chip enable ( CE), two additional chip enables for easy depth expansion (CE2, CE2 ), cycle start input (ADV/ LD ), synchronous clock enable ( CEN ), byte write enables (BW1,BW2 ,BW3 ,BW4 ) and read/write (R/ W ). Asynchronous inputs include the output enable ( OE), clock (CLK), SLEEP mode (ZZ, ti ed LOW if unused) and burst mode (MODE). Burst Mode can provide either interleaved or linear operation, burst operat ion can be initiated by synchronous address Advance/Load (ADV/ LD) pin in Low state. Subsequent burst address can be internally generated by the chip and contro lled by the same input pin ADV/LD in High state. Write cycles are internally self-time and synchronous with the rising edge of the clock input and when R/ W is Low. The feature simplified the writ e interface. Individual Byte enables allow individual bytes to be written. BW1 controls I/Oa pins; BW2 controls I/Ob pins; BW3 controls I/Oc pins; and BW4 controls I/Od pins. Cycle types can only be defined when an address is loaded. The SRAM operates from a +2.5V power supply, and all inputs and outputs are LVTTL-c ompatible. The device is ideally suited for high bandwidth utilization systems.

PRELIMINARY (July, 2005, Version 0.0) 3 AMIC Technology, Corp. Pin Configuration A17 A16 A15 A14 A13 A12 A11 NC VCC VSS NC NC MODE 100 256Kx18 A16 A15 A14 A13 A12 A11 A10 VCC VSS NC MODE 128Kx36 I/Ob8 I/Oa8 NC NC CE2 NC NC VCC VSS CLK NC NC A10 NC NC VCCQ VSSQ NC VSSQ VCCQ VSS VCC VCC ZZ VCCQ VSSQ NC NC VSSQ VCCQ NC NC NC I/Oa0 I/Oa1 NC NC NC VCCQ VSSQ NC NC VSSQ VCCQ VCC VCC VSS VCCQ VSSQ NC VSSQ VCCQ NC NC NC I/Ob8 I/Ob7 I/Ob6 VCC I/Ob4 CE2 CLK VSS VCC NC NC VCCQ VSSQ VSSQ VCCQ VSS VCC VCC ZZ VCCQ VSSQ VSSQ VCCQ I/Ob7 CECE BW4 BW3 BW2BW2 BW1BW1 CE2 CE2 CENCEN OEOE ADV/ LD ADV/ LD A67P8318E A67P7336E R/W R/W I/Ob5 I/Ob3 I/Ob2 I/Ob1 I/Ob0 VCCQ VSSQ VSSQ VCCQ VCC VCC VSS VCCQ VSSQ VSSQ VCCQ VCC I/Oc8 I/Oc0 I/Oc1 I/Oc2 I/Oc3 I/Oc4 I/Oc5 I/Oc6 I/Oc7 I/Od0 I/Od1 I/Od2 I/Od3 I/Od4 I/Od5 I/Od6 I/Od7 I/Od8 I/Oa2 I/Oa3 I/Oa4 I/Oa5 I/Oa6 I/Oa7 I/Oa8 I/Ob6 I/Ob5 I/Ob4 I/Ob3 I/Ob2 I/Ob1 I/Ob0 I/Oa7 I/Oa6 I/Oa5 I/Oa4 I/Oa3 I/Oa2 I/Oa1 I/Oa0 NCNC

PRELIMINARY (July, 2005, Version 0.0) 4 AMIC Technology, Corp. Block Diagram (128K X 36) 128Kx9x4 MEMORY ARRAY MODE LOGIC CLK LOGIC ADDRESS REGISTERS BURST LOGIC ADDRESS COUNTER CLR WRITE REGISTRY CONTROL LOGIC BYTEa WRITE DRIVER BYTEb WRITE DRIVER BYTEc WRITE DRIVER BYTEd WRITE DRIVER OUTPUT REGISTERS OUTPUT BUFFERS DATA-IN REGISTERS CHIP ENABLE LOGIC PIPELINED ENABLE LOGIC OUTPUT ENABLE LOGIC ZZ MODE ADV/LD CLK A0-A16 R/W BW1 BW2 BW3 BW4 CE CE2 CE2 OE CEN WRITE ADDRESS REGISTER WRITE ADDRESS REGISTER ADV/LD DATA-IN REGISTERS I/OsSENSE AMPS

PRELIMINARY (July, 2005, Version 0.0) 5 AMIC Technology, Corp. Block Diagram (256K X 18) DATA-IN REGISTERS MODE LOGIC CLK LOGIC ADDRESS REGISTERS BURST LOGIC ADDRESS COUNTER CLR WRITE REGISTRY CONTROL LOGIC BYTEa WRITE DRIVER BYTEb WRITE DRIVER 256KX9X2 MEMORY ARRAY9 OUTPUT REGISTERS OUTPUT BUFFERS CHIP ENABLE LOGIC PIPELINED ENABLE LOGIC OUTPUT ENABLE LOGIC ZZ MODE ADV/LD CLK A0-A17 R/W BW1 BW2 CE CE2 CE2 OE CEN WRITE ADDRESS REGISTER WRITE ADDRESS REGISTER ADV/LD I/OSSENSE AMPS DATA-IN REGISTERS

PRELIMINARY (July, 2005, Version 0.0) 6 AMIC Technology, Corp. Pin Description Pin No. Symbol Description LQFP (X18) LQFP (X36) 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48, 49, 50 35, 34, 33, 32, 100, 99, 82, 81, 45, 46, 47, 48, 49, 50 A2 - A9 A11 - A17 A10 Synchronous Address Inputs : These inputs are registered and must meet the setup and hold times around the rising edge of CLK. A0 and A1 are the two lest significant bits (LSB) of the address field and set the internal burst counter if burst is desired. 93 (BW1) 94 (BW2 ) 93 (BW1) 94 (BW2 ) 95 (BW3 ) 96 (BW4 ) BW1 BW2 BW3 BW4 Synchronous Byte Write Enables : These active low inputs allow individual bytes to be written when a WRITE cycle is active and must meet the setup and hold times around the rising edge of CLK. BYTE WRITEs need to be asserted on the same cycle as the address, BWs are associated with addresses and apply to subsequent data. BW1 controls I/Oa pins; BW2 controls I/Ob pins; BW3 controls I/Oc pins; BW4 controls I/Od pins. 89 89 CLK Clock: This signal registers the address, data, chip enables, byte write enables and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock are rising edge. 98 98 CE Synchronous Chip Enable : This active low input is used to enable the device. This input is sampled only when a new external address is loaded (ADV/ LD LOW). 92 92 CE2 Synchronous Chip Enable : This active low input is used to enable the device and is sampled only when a new external address is loaded (ADV/ LD LOW). This input can be used for memory depth expansion. 97 97 CE2 Synchronous Chip Enable : This active high input is used to enable the device and is sampled only when a new external address is loaded (ADV/ LD LOW). This input can be used for memory depth expansion. 86 86 OE Output Enable : This active low asynchronous input enables the data I/O output drivers. 85 85 ADV/ LD Synchronous Address Advance/Load : When HIGH, this input is used to advance the internal burst counter, controlling burst access after the external address is loaded. When HIGH, R/ W is ignored. A LOW on this pin permits a new address to be loaded at CLK rising edge. 87 87 CEN Synchronous Clock Enable : This active low input permits CLK to propagate throughout the device. When HIGH, the device ignores the CLK input and effectively internally extends the previous CLK cycle. This input must meet setup and hold times around the rising edge of CLK.

PRELIMINARY (July, 2005, Version 0.0) 7 AMIC Technology, Corp. Pin Description (continued) Pin No. Symbol Description LQFP (X18) LQFP (X36) 64 64 ZZ Snooze Enable : This active high asynchronous input causes the device to enter a low-power standby mode in which all data in the memory array is retained. When active, all other inputs are ignored. 88 88 R/ W Read/Write : This active input determines the cycle type when ADV/LD is LOW. This is the only means for determining READs and WRITEs. READ cycles may not be converted into WRITEs (and vice versa) other than by loading a new address. A LOW on this pin permits BYTE WRITE operations and must meet the setup and hold times around the rising edge of CLK. Full bus width WRITEs occur if all byte write enables are LOW. 63, 62, 59, 58, 24, 23, 22, 19, 18 13, 12, 9, 8 58, 59, 62, 63 75, 78, 79, 80 12, 13, 25, 28, 29, 30 I/Oa I/Ob I/Oc I/Od SRAM Data I/O : Byte “a” is I/Oa pins; Byte “b” is I/Ob pins; Byte “c” is I/Oc pins; Byte “d” is I/Od pins. Input data must meet setup and hold times around CLK rising edge. 31 31 MODE Mode : This input selects the burst sequence. A LOW on this pin selects linear burst. NC or HIGH on this pin selects interleaved burst. Do not alter input state while device is operating. 29, 30, 38, 39, 42,43 51, 52, 53, 95, 96 38,39,42,43 NC No Connect : These pins can be left floating or connected to GND to minimize thermal impedance. 15, 41, 65, 91 15, 41, 65, 91 VCC Power Supply : See DC Electrical Characteristics and Operating Conditions for range. 14, 16, 66 14, 16, 66 VCC These pins do not have to be connected directly to VCC as long as the input voltage is ≥ VIH. This input is not connected to VCC bus internally. 4, 11, 20, 27, 54, 61, 70, 77 4, 11, 20, 27, 54, 61, 70, 77 VCCQ Isolated Output Buffer Supply : See DC Electrical Characteristics and Operating Conditions for range. 17, 40, 90 17, 40, 90 VSS Ground : GND. 5,10,21,26, 55,60,71,76 5,10,21,26, 55,60,71,76 VSSQ Isolated Output Buffer Ground

PRELIMINARY (July, 2005, Version 0.0) 8 AMIC Technology, Corp. Truth Table (Notes 5 - 7) Operation Address Used CE CE2 CE2 ZZ ADV/ LD R/ W BWx OE CEN CLK I/O Notes Deselected Cycle, Power-down None H X X L L X X X L L →H High-Z Deselected Cycle, Power-down None X H X L L X X X L L →H High-Z Deselected Cycle, Power-down None X X L L L X X X L L →H High-Z Continue Deselect Cycle None X X X L H X X X L L →H High-Z 1 READ Cycle (Begin Burst) External L L H L L H X L L L →H Q READ Cycle (Continue Burst) Next X X X L H X X L L L →H Q 1,7 NOP/Dummy READ (Begin Burst) External L L H L L H X H L L →H High-Z 2 Dummy READ (Continue Burst) Next X X X L H X X H L L →H High-Z 1,2,7 WRITE Cycle (Begin Burst) External L L H L L L L X L L →H D 3 WRITE Cycle (Continue Burst) Next X X X L H X L X L L →H D 1,3,7 NOP/WRITE Abort (Begin Burst) None L L H L L L H X L L →H High-Z 2,3 WRITE Abort (Continue Burst) Next X X X L H X H X L L →H High-Z 1,2,3,7 IGNORE Clock Edge (Stall) Current X X X L X X X X H L →H - 4 SLEEP Mode None X X X H X X X X X X High-Z Notes: 1. Continue Burst cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ or WRITE) is chosen in the initial Begin Burst cycle. A Continue Deselect cycle can only be entered if a Deselect cycle is executed first. 2. Dummy READ and WRITE Abort cycles can be consider ed NOPs because the device performs no operation. A WRITE Abort means a WRITE command is given, but no operation is performed. OE may be wired LOW to minimize the number of control signals to the SRAM. The device will automatically turn off the output drivers during a WRITE cycle. Some users may use OE when the bus turn-on and turn-off times do not meet their requirements. 4. If an Ignore Clock Edge command occurs dur ing a READ operation, the I/O bus will re main active (Low-Z). If it occurs during a WRITE cycle, the bus will remain in High-Z. No WRITE operations will be perfo rmed during the Ignored Clock Edge cycle. 5. X means “Don’t Care.” H means logic HIGH. L means logic LOW. BWx = H means all byte write signals (BW1,BW2 ,BW3 and BW4 ) are HIGH. BWx = L means one or more byte write signals are LOW. 6. BW1enables WRITEs to Byte “a” (I/Oa pins); BW2 enables WRITEs to Byte “b” (I/Ob pins); BW3 enables WRITEs to Byte “c” (I/Oc pins); BW4 enables WRITEs to Byte “d” (I/Od pins). 7. The address counter is incremented for all Continue Burst cycles.

PRELIMINARY (July, 2005, Version 0.0) 9 AMIC Technology, Corp. Partial Truth Table for READ/WRITE Commands (X18) Operation R/ W BW1 BW2 READ H X X WRITE Byte “a” L L H WRITE Byte “b” L H L WRITE all bytes L L L WRITE Abort/NOP L H H Note : Using and BYTE WRITE(s), any one or more bytes may be written. Partial Truth Table for READ/WRITE Commands (X36) Operation R/ W BW1 BW2 BW3 BW4 READ H X X X X WRITE Byte “a” L L H H H WRITE Byte “b” L H L H H WRITE Byte “c” L H H L H WRITE Byte “d” L H H H L WRITE all bytes L L L L L WRITE Abort/NOP L H H H H Note : Using R/W and BYTE WRITE(s), any one or more bytes may be written. Linear Burst Address Table (MODE = LOW) First Address (External) Second Address (Internal) Third Address (Internal) Fourth Address (Internal) Interleaved Burst Address Table (MODE = HIGH or NC) First Address (External) Second Address (Internal) Third Address (Internal) Fourth Address (Internal)

PRELIMINARY (July, 2005, Version 0.0) 10 AMIC Technology, Corp. Absolute Maximum Ratings* Voltage Relative to GND for any Pin Except VCC (Vin, °C to 70°C *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. (0°C ≤ TA ≤ 70°C, VCC, VCCQ = +2.5V± 5% unless otherwise noted) Symbol Parameter Conditions Min. Max. Unit Note VIH Input High Voltage 1.7 VCC+0.3 V 1,2 VIL Input Low Voltage -0.3 0.8 V 1,2 ILI Input Leakage Current 0V ≤ VIH ≤ VCC -2.0 TBD µA ILO Output Leakage Current Output(s) disabled, 0V ≤ VIN≤ VCC -2.0 TBD µA VOH Output High Voltage I OH = -1.0mA 2.0 V 1,3 VOL Output Low Voltage I OL = 1.0mA 0.4 V 1,3 VCC Supply Voltage 2.375 2.625 V 1 VCCQ Isolated Output Buffer Supply 2.375 VCC V 1,4 Capacitance Symbol Parameter Conditions Typ. Max. Unit Note CI Control Input Capacitance 3 4 pF 6 CO Input/Output Capacitance (I/O) 4 5 pF 6 CA Address Capacitance TA = 25°C; f = 1MHz VCC = 2.5V 3 3.5 pF 6 Note : 1. All voltages referenced to VSS (GND). 2. Overshoot : V IH ≤ +4.6V for t ≤ tKHKH/2 for I ≤ 20mA Undershoot : V IL ≥ -0.7V for t ≤ tKHKH/2 for I ≤ 20mA Power-up : V IH ≤ +2.625V and VCC ≤ 2.625V for t ≤ 200ms 3. The load used for VOH, VOL testing is shown in Figure 2. AC load current is higher than the shown DC values. AC I/O curves are available upon request. 4. VCC and VCCQ can be externally wired together to the same power supply. 5. This parameter is sampled.

PRELIMINARY (July, 2005, Version 0.0) 11 AMIC Technology, Corp. ICC Operating Condition and Maximum Limits Max. Symbol Parameter Unit Conditions ICC Power Supply Current : Operating TBD TBD TBD TBD TBD TBD mA Device selected; All inputs ≤ V IL or ≥ VIH; Cycle time ≥ t KC (MIN); VCC = MAX; Outputs open ISB Standby TBD TBD TBD TBD TBD TBD mA Device deselected; VCC = MAX; All inputs ≤ VSS+0.2 or ≥ VCC- 0.2; Cycle time ≥ tKC (MIN) ISB1 Standby TBD TBD TBD TBD TBD TBD mA Device deselected; VCC = MAX; All inputs ≤VSS+0.2 or ≥ VCC- 0.2; All inputs static; CLK frequency=0 ZZ ≤ 0.2V ISB2 Standby TBD TBD TBD TBD TBD TBD mA Device deselected; VCC = MAX; All inputs ≤ VIL; or ≥ VIH; All inputs static; CLK frequency=MAX ZZ ≥ VCC-0.2V ISB2Z SLEEP Mode TBD TBD TBD TBD TBD TBD mA ZZ ≥ VIH

PRELIMINARY (July, 2005, Version 0.0) 12 AMIC Technology, Corp. AC Characteristics (Note 4) Unit NoteSymbol Parameter Min Max Min Max Min Max Min Max Min Max Min Max Clock tKF Clock frequency - 250 - 227 - 200 - 166 - 150 - 133 MH Output Times tGLQX OE to output in Low-Z 0 - 0 - 0 - 0 - 0 - 0 - ns 1,2,3 Setup Times Hold Times Notes: 1. This parameter is sampled. 2. Output loading is specified with C1=5pF as in Figure 2. 3. Transition is measured ±200mV from steady state voltage. 4. OE can be considered a “Don’t Care” during WRITE; however, controlling OE can help fine-tune a system for turnaround timing. 5. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK when ADV/ LD is LOW and chip enabled. All other synchronous inputs meet the setup and hold times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each rising edge of CLK (when ADV/ LD is LOW) to remain enabled.

PRELIMINARY (July, 2005, Version 0.0) 14 AMIC Technology, Corp. SLEEP Mode SLEEP Mode is a low current “Power-down” mode in which the device is deselected and current is reduced to I SB2Z. This duration of SLEEP Mode is dictat ed by the length of time the ZZ is in a HIGH state. Afte r entering SLEEP Mode, all inputs except ZZ become disabled and all outputs go to High-Z. The ZZ pin is asynchronous, active high input that causes the device to enter SLEEP Mode. When the ZZ pin becomes logic HIGH, ISB2Z is guaranteed after the time t ZZI is met. Any operation pending when ent ering SLEEP Mode is not guaranteed to successfully complete. Therefore, SLEEP Mode (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting SLEEP Mode during t RZZ, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SLEEP Mode. SLEEP Mode Electrical Characteristics (VCC, VCCQ = +2.5V±5%) Symbol Parameter Conditions Min. Max. Unit Note ISB2Z Current during SLEEP Mode ZZ ≥ VIH - 60 mA tZZ ZZ active to input ignored 0 2(t KHKH) ns 1 tRZZ ZZ inactive to input sampled 0 2(t KHKH) ns 1 tZZI ZZ active to snooze current - 2(t KHKH) ns 1 tRZZI ZZ inactive to exit snooze current 0 ns 1 Note : 1. This parameter is sampled. SLEEP Mode Waveform tRZZtZZ tZZI IISB2Z High-Z DESELECT or READ Only Output (Q) ALL INPUTS (except ZZ) ISUPPLY ZZ CLK : Don't Care tRZZI

PRELIMINARY (July, 2005, Version 0.0) 15 AMIC Technology, Corp. READ/WRITE Timing Note : 1. For this waveform, ZZ is tied LOW. 2. Burst sequence order is determined by MODE (0 = linear, 1 = interleaved). BRST operations are optional. 3. CE represents three signals. When CE = 0, it represents CE = 0, CE2 = 0, CE2 = 1. 4. Data coherency is provided for all possible operations. If a READ is initiated the most current data is used. The most recent data may be from the input data register. A3A2A1 A4 A5 D(A1) WRITE D(A1) WRITE D(A2) BURST WRITE D(A2+1) READ Q(A3) READ Q(A4) BURST READ Q(A4+1) WRITE D(A5) READ Q(A6) WRITE D(A7) DESELECT : Don't Care : Undefined 12345 tGLQX tKHKH 6789 1 0 CLK CEN CE ADV/ LD R/W BWx ADDRESS I/O COMMAND A6 A7 D(A2) D(A2+1) Q(A6)D(A5)Q(A4+1)Q(A4)Q(A3) OE tKLKHtEVKH tKHEX tKHKL tKHCXtCVKH tKHAXtAVKH tKHDXtDVKH tKHQZtGLQV tKHQXtGHQZ tKHQX tKHQV tKHQX1

PRELIMINARY (July, 2005, Version 0.0) 16 AMIC Technology, Corp. NOP, STALL and Deselect Cycles Note : 1. The IGNORE CLOCK EDGE or STALL cycle (clock 3) illustrates CEN being used to create a “pause.” A WRITE is not performed during this cycle. 2. For this waveform, ZZ and OE are tied LOW. 3. CE represents three signals. When CE = 0, it represents CE = 0, 2CE = 0, CE2 = 1. 4. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most recent data may be from the input data register. A3A2A1 A4 A5 Q(A5)D(A4)Q(A3)Q(A2)D(A1) WRITE D(A1) READ Q(A2) STALL READ Q(A3) WRITE D(A4) STALL NOP READ Q(A5) DESELECT CONTINUE DESELECT : Don't Care : Undefined 12345 tKHQX tKHQZ 6789 1 0 CLK CEN CE ADV/ LD R/W BWx ADDRESS I/O COMMAND

PRELIMINARY (July, 2005, Version 0.0) 17 AMIC Technology, Corp.

Ordering Information

Part No. Configure Cycle Time / Access Time Package A67P8318E-4.2 7.5ns / 4.2ns 100L LQFP A67P8318E-4.2F 7.5ns / 4.2ns 100L Pb-Free LQFP A67P8318E-3.8 6.7ns / 3.8ns 100L LQFP A67P8318E-3.8F 6.7ns / 3.8ns 100L Pb-Free LQFP A67P8318E-3.5 6.0ns / 3.5ns 100L LQFP A67P8318E-3.5F 6.0ns / 3.5ns 100L Pb-Free LQFP A67P8318E-3.2 5.0ns / 3.2ns 100L LQFP A67P8318E-3.2F 5.0ns / 3.2ns 100L Pb-Free LQFP A67P8318E-2.8 4.4ns / 2.8ns 100L LQFP A67P8318E-2.8F 4.4ns / 2.8ns 100L Pb-Free LQFP A67P8318E-2.6 4.0ns / 2.6ns 100L LQFP A67P8318E-2.6F 256K X 18 4.0ns / 2.6ns 100L Pb-Free LQFP A67P7336E-4.2 7.5ns / 4.2ns 100L LQFP A67P7336E-4.2F 7.5ns / 4.2ns 100L Pb-Free LQFP A67P7336E-3.8 6.7ns / 3.8ns 100L LQFP A67P7336E-3.8F 6.7ns / 3.8ns 100L Pb-Free LQFP A67P7336E-3.5 6.0ns / 3.5ns 100L LQFP A67P7336E-3.5F 6.0ns / 3.5ns 100L Pb-Free LQFP A67P7336E-3.2 5.0ns / 3.2ns 100L LQFP A67P7336E-3.2F 5.0ns / 3.2ns 100L Pb-Free LQFP A67P7336E-2.8 4.4ns / 2.8ns 100L LQFP A67P7336E-2.8F 4.4ns / 2.8ns 100L Pb-Free LQFP A67P7336E-2.6 4.0ns / 2.6ns 100L LQFP A67P7336E-2.6F 128K X 36 4.0ns / 2.6ns 100L Pb-Free LQFP

PRELIMINARY (July, 2005, Version 0.0) 18 AMIC Technology, Corp.

Package Information

LQFP 100L Outline Dimensions unit: inches/mm Symbol Dimensions in inches Dimensions in mm A1 0.002 - 0.006 0.05 - 0.15 c 0.004 - 0.008 0.09 - 0.20 HE 0.866 BSC 22.00 BSC E 0.787 BSC 20.00 BSC HD 0.630 BSC 16.00 BSC D 0.551 BSC 14.00 BSC e 0.026 BSC 0.65 BSC L1 0.039 REF 1.00 REF Notes: 1. Dimensions D and E do not include mold protrusion. 2. Dimensions b does not include dambar protrusion. Total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. 5180 100 HD D E HE 13 0 b D y A1A2 ce θ L