A64S9316G-85

A64S9316 AMICC | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 15

Technical content

Preliminary 512K X 16 Bit Low Voltage Super RAMTM PRELIMINARY (July, 2002, Version 0.1) AMIC Technology, Inc. Document Title 512K X 16 Bit Low Voltage Super RAMTM

Revision History

Rev. No. History Issue Date Remark

0.0 Initial issue May 16, 2002 Preliminary

0.1 Add tASC, tAHC, tCEH, tWEH July 31, 2002

Preliminary 512K X 16 Bit Low Voltage Super RAMTM PRELIMINARY (July, 2002, Version 0.1) 1 AMIC Technology, Inc.

Features

n Operating voltage: 2.7V to 3.1V n Access times: 70 ns (max.) n Current: A64S9316 series: Operating: 35mA (max.) Power Down Standby: 10µA (max.) n Fully SRAM compatible operation n Full static operation, no clock or refreshing required n All inputs and outputs are directly TTL-compatible n Common I/O using three-state output n Industrial operating temperature range: -25°C to +85°C for -I n Available in 48-ball Mini BGA (6X8) package. General Description The A64S9316 is a low operating current 8,388,608 -bit Super RAM organized as 524,288 words by 16 bits and operates on low power supply voltage from 2.7V to 3.1V. It is built using AMIC’s high performance CMOS DRAM process. Using hidden refresh technique, the A64S9316 provides a 100% compatible asynchronous interface. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. The chip enable input is provided for POWER -DOWN, device enable. Two byte enable inputs and an output enable input are included for easy interfacing. This A64S9316 is suited for low power application such as mobile phone and PDA or other battery -operated handh eld device. Pin Configuration n Mini BGA (6X8) Top View 1 2 3 4 5 6 A LB OE A0 A1 A2 CE2 B I/O8 HB A3 A4 CE1 I/O0 C I/O9 I/O10 A5 A6 I/O1 I/O2 D VSS I/O11 A17 A7 I/O3 VCC E VCC I/O12 GND A16 I/O4 VSS F I/O14 I/O13 A14 A15 I/O5 I/O6 G I/O15 NC A12 A13 WE I/O7 H A18 A8 A9 A10 A11 NC A64S9316G

PRELIMINARY (July, 2002, Version 0.1) 2 AMIC Technology, Inc. Block Diagram DECODER 8,388,608 MEMORY ARRAY COLUMN I/OINPUT DATA CIRCUIT CONTROL CIRCUIT VCC GND I/O7 I/O0 A18 A17 WE HB INPUT DATA CIRCUIT I/O8 I/O15 CE2 LB OE CE1 VSS Pin Description Symbol Description A0 - A18 Address Inputs CE1 Chip Enable 1 Input CE2 Chip Enable 2 Input I/O0 - I/O15 Data Input/Outputs WE Write Enable Input LB Byte Enable Input (I/O0 to I/O7) HB Byte Enable Input (I/O8 to I/O15) OE Output Enable Input VCC Power VSS Ground GND Ground NC No Connection

PRELIMINARY (July, 2002, Version 0.1) 3 AMIC Technology, Inc. Recommended DC Operating Conditions (TA = 0°C to + 70°C or -25°C to 85°C) Symbol Parameter Min. Max. Unit VCC Supply Voltage 2.7 3.1 V VSS Ground 0 0 V GND Ground 0 0 V VIH Input High Voltage 2.4 VCC + 0.3 V VIL Input Low Voltage -0.3 +0.6 V CL Output Load - 30 pF TTL Output Load - 1 - Absolute Maximum Ratings* *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. Symbol Parameter -70 -85 Unit Conditions Min. Max. Min. Max. ILI Input Leakage Current - 1 - 1 µA VIN = GND to VCC ILO Output Leakage Current - 1 - 1 µA CE1 = VIH or CE2 = VIL or OE = VIH or WE = VIL VI/O = GND to VCC ICC1 - 35 - 30 mA Min. Cycle, Duty = 100% CE1 = VIL, CE2 = VIH II/O = 0mA ICC2 Dynamic Operating Current - 5 - 5 mA CE1 = VIL, CE2 = VIH VIH = VCC, VIL = 0V, f = 1MHz, II/O = 0mA

PRELIMINARY (July, 2002, Version 0.1) 4 AMIC Technology, Inc. Symbol Parameter -70 -85 Unit Conditions Min. Max. Min. Max. ISB1 Standby Power Supply Current - 80 - 80 µA CE1 ≥ VCC - 0.2V CE2 ≥ VCC - 0.2V VIN ≥ 0V ISB2 Power Down Mode Standby Current - 10 - 10 µA CE2 ≤ 0.2V VOL Output Low Voltage - 0.4 - 0.4 V IOL = 2.1mA VOH Output High Voltage 2.4 - 2.4 - V IOH = -1.0mA Truth Table CE1 CE2 OE WE LB HB I/O0 to I/O7 Mode I/O8 to I/O15 Mode VCC Current H H X X X X Not selected Not selected ISB1, ISB X H X X H H Not selected Not selected ISB1, ISB X L X X X X Not selected Not selected ISB2 L L Read Read ICC1, ICC2 L H L H L H Read High - Z ICC1, ICC2 H L High - Z Read ICC1, ICC2 L L Write Write ICC1, ICC2 L H X L L H Write Not Write/Hi - Z ICC1, ICC2 H L Not Write/Hi - Z Write ICC1, ICC2 High - Z High - Z ICC1, ICC2 L H H H X X High - Z High - Z ICC1, ICC2 Note: X = H or L Capacitance (TA = 25°C, f = 1.0MHz) Symbol Parameter Min. Max. Unit Conditions CIN* Input Capacitance - 10 pF VIN = 0V CI/O* Input/Output Capacitance - 10 pF VI/O = 0V * These parameters are sampled and not 100% tested.

PRELIMINARY (July, 2002, Version 0.1) 5 AMIC Technology, Inc. Initialization The A64S9316 is initialized in the power-on sequence according to the following. 1. To stabilize internal circuits, after turning on the power, a 350 µs or longer wait time must precede any signal toggling. 2. After the wait time, it can be normal operation. Power on Chart VCC VCC(min) CE1 CE2 50ns (min) 350us Wait Time Normal Operation Notes: 1. Following power application, make CE2 and CE1 high level during the wait time interval. 2. After power on sequence, the normal operating CE2 must keep at high. Power on / Depower down State Machine Standby Mode Characteristics Standby Mode Memory Cell Data Hold Standby Supply Current (µA) Standby Valid 100 (ISB1) Power down Invalid 10 (ISB2) Initial State Active Standby Mode Power Down Mode Power on Wait 350us CE1=VIH, CE2=VIH CE1=VIH CE2=VIH, CE1=VIL, CE2=VIH CE1=VIH CE2=VIL, CE1=VIH, CE2=VIH CE1=VIL, CE2=VIH CE1=VIH, CE2=VIH CE1=VIH CE2=VIL,

PRELIMINARY (July, 2002, Version 0.1) 7 AMIC Technology, Inc. AC Characteristics (TA = 0°C to +70°C or -25°C to 85°C, VCC = 2.7V to 3.1V) Symbol Parameter -70 -85 Unit Min. Max. Min. Max. Read Cycle tRC Read Cycle Time 70 - 85 - ns tSKEW Address Skew - 10 - 10 ns tAA Address Access Time - 70 - 85 ns tACE Chip Enable Access Time - 70 - 85 ns tBE Byte Enable Access Time - 70 - 85 ns tOE Output Enable to Output Valid - 35 - 45 ns tCLZ Chip Enable to Output in Low Z 10 - 10 - ns tBLZ Byte Enable to Output in Low Z 5 - 5 - ns tOLZ Output Enable to Output in Low Z 5 - 5 - ns tCHZ Chip Disable to Output in High Z 0 25 0 35 ns tBHZ Byte Disable to Output in High Z 0 25 0 35 ns tOHZ Output Disable to Output in High Z 0 25 0 35 ns tOH Output Hold from Address Change 10 - 10 - ns tASC Address Setup to CE1 Low 0 - 0 - ns tAHC Address Hold Time from CE1 High 0 - 0 - ns tCEH CE1 High Pulse With 10 - 10 - ns Write Cycle tWC Write Cycle Time 70 - 85 - ns tSKEW Address Skew - 10 - 10 ns tCW Chip Enable to End of Write 60 - 70 - ns tBW Byte Enable to End of Write 60 - 70 - ns tAS Address Setup Time 0 - 0 - ns tAW Address Valid to End of Write 60 - 70 - ns tWP Write Pulse Width 50 - 55 - ns tWR Write Recovery Time 0 - 0 - ns tWHZ Write to Output in High Z - 20 - 20 ns tDW Data to Write Time Overlap 30 - 35 - ns tDH Data Hold from Write Time 0 - 0 - ns tOW Output Active from End of Write 5 - 5 - ns tASC Address Setup to CE1 Low 0 - 0 - ns tAHC Address Hold Time from CE1 High 0 - 0 - ns tCEH CE1 High Pulse With 10 - 10 - ns tWEH WE High Pulse With 10 - 10 - ns Note: tCHZ, tBHZ and t OHZ and t WHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels.

PRELIMINARY (July, 2002, Version 0.1) 8 AMIC Technology, Inc. Timing Waveforms Read Cycle 1(1, 2, 4, 6) Address DOUT CE1 tSKEW tRC tSKEW tRC tAA tOH tAA tOH tASC

PRELIMINARY (July, 2002, Version 0.1) 9 AMIC Technology, Inc. Read Cycle 2-1(1, 3, 6) tRC tRC tSKEWtSKEW tASC tAA tAHC tCEH tASC tAHC tAA tACE tCLZ5 tBE tBLZ5 tOE tOLZ5 tCHZ5 tBHZ5 tOHZ5 tACE tCLZ5 tBE tBLZ5 tOE tOLZ5 tOHZ5 tBHZ5 tCHZ5 Address CE1 HB LB, OE DOUT tBE Read Cycle 2-2(1, 3, 6) tRC tRC tSKEWtSKEW tASC tAHC tACE tCLZ5 tBE tBLZ5 tOE tOLZ5 tBHZ5 tOHZ5 tBLZ5 tOE tOLZ5 tOHZ5 tBHZ5 tCHZ5 Address CE1 HB LB, OE DOUT tBE tSKEW tAA tAA Notes: 1. WE is high for Read Cycle. 2. Device is continuously enabled 1CE = VIL, HB = VIL and, or LB = VIL. 3. Address valid prior to or coincident with CE1 and ( HB and, or LB ) transition low. 4. OE = VIL. 5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested. 6. CE2 is high for Read Cycle.

PRELIMINARY (July, 2002, Version 0.1) 10 AMIC Technology, Inc. Timing Waveforms (continued) Write Cycle 1-1(6) (Write Enable Controlled) tWC tWC tSKEWtSKEW tASC tAHC tCEH tASC tAHC Address CE1 HB LB, tAW tCW tAW tCW tBW tBW tWR3 tWR3tAS1 tWP2 tDW tDH tWHZ4 tOW tWP2 tAS1 tWHZ4 tDHtDW tOW WE Data In Data Out Write Cycle 1-2(6) (Write Enable Controlled) tWC tWC tSKEWtSKEW tASC tAHC Address CE1 HB LB, tBW tBW tWR3 tWR3tAS1 tWP2 tDW tDH tWHZ4 tOW tWP2 tAS1 tWHZ4 tDHtDW tOW WE Data In Data Out tWEH tSKEW

PRELIMINARY (July, 2002, Version 0.1) 11 AMIC Technology, Inc. Timing Waveforms (continued) Write Cycle 2-1(6) (Chip Enable Controlled) tWC tWC tSKEWtSKEW tASC tCEH tASC Address CE1 HB LB, tAW tCW2 tAW tCW2 tBW tWP tDW tDH tWHZ4 tOW tWP tWHZ4 tDHtDW tOW WE Data In Data Out tAHC tAHC tBW tWR3 tWR3 Write Cycle 2-2(6) (Chip Enable Controlled) tWC tWC tSKEWtSKEW tASC Address CE1 HB LB, tAW tBW tWP tDW tDH tWHZ4 tOW tWP tWHZ4 tDHtDW tOW WE Data In Data Out tAHC tBW tWR3 tWR3 tSKEW

PRELIMINARY (July, 2002, Version 0.1) 12 AMIC Technology, Inc. Timing Waveforms (continued) Write Cycle 3-1(6) (Byte Enable Controlled) tWC tWC tSKEWtSKEW tASC tCEH tASC Address CE1 HB LB, tAW tCW tAW tCW tBW2 tWP tDW tDH tWHZ4 tOW tWP tWHZ4 tDHtDW tOW WE Data In Data Out tAHC tAHC tBW2 tWR3 tWR3 tAS1 tAS1 Write Cycle 3-2(6) (Byte Enable Controlled) tWC tWC tSKEWtSKEW tASC Address CE1 HB LB, tAW tBW2 tWP tDW tDH tWHZ4 tOW tWP tWHZ4 tDHtDW tOW WE Data In Data Out tAHC tBW2 tWR3 tWR3 tAS1 tAS1 tSKEW Notes: 1. tAS is measured from the address valid to the beginning of Write. 2. A Write occurs during the overlap (t WP, tBW) of a low 1CE , WE and ( HB and, or LB ). 3. tWR is measured from the earliest of 1CE or WE or ( HB and, or LB ) going high to the end of the Write cycle. 4. OE level is high or low. 5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested. 6. CE2 is high for Write Cycle.

PRELIMINARY (July, 2002, Version 0.1) 13 AMIC Technology, Inc. AC Test Conditions Input Pulse Levels 0.4V to 2.4V Input Rise And Fall Time 5 ns Input and Output Timing Reference Levels 1.5V Output Load See Figures 3 and 4 30pF * Including scope and jig. * Including scope and jig. CL TTL 5pF CL TTL Figure 3. Output Load Figure 4. Output Load for tCLZ, tOLZ,

Ordering Information

Part No. Access Time (ns) Operating Current Max. (mA) Power Down Mode Standby Current Max. (mmA) Package A64S9316G-70 70 35 10 48B Mini BGA A64S9316G-85 85 30 10 48B Mini BGA A64S9316G-70I 70 35 10 48B Mini BGA A64S9316G-85I 85 30 10 48B Mini BGA Note: -I is for industrial operating temperature range

PRELIMINARY (July, 2002, Version 0.1) 14 AMIC Technology, Inc.

Package Information

Mini BGA 6X8 (48 BALLS) Outline Dimensions unit : millimeter(mm) Symbol Min Typ Max A - 0.75 - B 5.90 6.00 6.10 B1 - 3.75 - C 7.90 8.00 8.10 C1 - 5.25 - D 0.30 0.35 0.40 E 1.00 1.10 1.20 E1 - 0.36 - E2 0.2 0.25 0.3 123456 A B C D E F G H Bottom View Pin A1 Index Diameter D Solder Ball A A Top View Pin A1 Index B C 0.10 E D