A64S06161A AMICC | Alldatasheet

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(March, 2005, Version 0.0) AMIC Technology, Corp. Preliminary

Revision history

Rev. No. History Issue Date

0.0 Initial issue March 28, 2005

16M(1M x 16bit) Normal mode & Page mode Static Random Access Memory Remark Preliminary

(March, 2005, Version 0.0) AMIC Technology, Corp. Preliminary MEMORY 16M(1M x 16bit) Normal mode & Page mode Static Random Access Memory

DESCRIPTION

FEATURES

  • Standard Asynchronous SRAM Interface and Page Mode
  • Organization : 1M x 16Bit
  • Power Supply Voltage : 2.7 ~ 3.3 V
  • Page Size : 4 words
  • Page Mode Access (tPAA) : 35ns
  • Data Retention Voltage : 2.4V
  • Tri-state Output and TTL Compatible FUNCTIONAL BLOCK DIAGRAM PRODUCT FAMILY The A64S06161A is a 16Mb high speed, low power Static Random Access Memory(SRAM) organized as 1,048,576 words by 16 bits and supports Page Mode. The A64S06161A is a Pseudo SRAM based on successfully proven DRAM CELL SRAM which was specifically developed for cost sensitive, low power computing and communication applications such as mobile cellular phone handsets, personal digital assistants and other battery-operated consumer products. Memory Array 8192 rows 128 x 16 columns Row Decoder Add. Input Buffer Column Decoder Add. Input Buffer Row Address Column Address Ref. Cont. DC Generator Circuit Control Logic /CS /OE /WE Sense Amp.Write Driver Data I/O Buffer IO0 IO7 IO8 IO15 /UB /LB Data Input / OutputIO0∼IO15 Lower Byte (IO0∼7)/LBAddress InputA0∼A19 Upper Byte (IO8∼15)/UBWrite Enable Input/WE GroundVSSOutput Enable Input/OE PowerVCCChip Select Input/CS NameFunction FunctionName /PD IO0 IO2 VCC VSS IO6 IO7 NC /CS IO1 IO3 IO4 IO5 /WE A11 A16 A15 A13 A10 A17 VSS A14 A12 /OE /UB IO10 IO11 IO12 IO13 A19 /LB IO8 IO9 VSS VCC IO14 IO15 A18 654321 A B C D E F G H PIN DESCRIPTION 100uA IccDR (Max) 100uA ISB1 (Max) 2.0mA ICC1 (Max) -40 ~ 85 ℃ Operating Temperature Speed 2.7 ~ 3.3 V Voltage ModeProduct Family A64S06161A Page Note : E3 pin ( VSS) can be remain as a NC

(March, 2005, Version 0.0) AMIC Technology, Corp. Preliminary ABSOLUTE MAXIMUM RATING Note : Stresses greater than those listed under “ABSOLUTE MAXIMUM RATINGS” may cause permanent damage to the device. This is stress rating only and the functional operation of the device under these or any other conditions above those indicated in the operation of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect reliability. PRODUCT LIST ℃-40 ~ 85TAOperating Temperature (Extended) ℃-55 to 150TSTGStorage temperature W1.0PDPower Dissipation V-0.2 to 3.6VCCVoltage on Vcc supply relative to Vss V-0.2 to VCC+0.3 VVIN, VOUTVoltage on any pin relative to Vss UnitRatingsSymbolItem StandbyDeselectedHigh-ZHigh-ZXXXXHH StandbyDeselectedHigh-ZHigh-ZHHXXHX ActiveOutput DisabledHigh-ZHigh-ZXLHHHL ActiveOutput DisabledHigh-ZHigh-ZLXHHHL ActiveLower Byte ReadHigh-ZData OutHLHLHL ActiveUpper Byte ReadData OutHigh-ZLHHLHL ActiveWord ReadData OutData OutLLHLHL ActiveLower Byte WriteHigh-ZData InHLLXHL ActiveUpper Byte WriteData InHigh-ZLHLXHL ActiveWord WriteData InData InLLLXHL I/O 0~7/PD /WE/OE /UB/LB I/O 8~15 PowerMODE/CS TRUTH TABLE 16M, 48-FBGA , 70 ns, 3.0V, -40℃∼85℃A64S06161A-70U FunctionPart Name

(March, 2005, Version 0.0) AMIC Technology, Corp. Preliminary DC AND OPERATING CHARACTERISTICS RECOMMENDED DC OPERATING CONDITIONS Note : 1.TA = -40℃ to 85℃, otherwise specified. 2. Overshoot : Vcc + 1.0V in case of pulse width ≤ 20 ns. 3. Undershoot : -1.0V in case of pulse width ≤ 20 ns. 4. Overshoot and undershoot are sampled, not 100% tested. 5. Stable power supply required 100 us before device operation. CAPACITANCE (TA = 25 ℃, f = 1.0MHz) Note : This parameter is sampled and not 100% tested pF10VIO =0VOutput CapacitanceCOUT pF8VIN =0VInput CapacitanceCIN UnitMax.ConditionParameterSymbol mA20Cycle time=Min, IIO=0mA, 100% duty /CS = VIL,VIN=VIL or VIH Icc2 uA100/CS ≥ Vcc-0.2V, /UB=/LB ≥ Vcc-0.2V (/UB,/LB Controlled) Other inputs = 0 or Vcc ISB1Standby Current(CMOS) mA10/CS1 = VIL, CS2=VIH,Tpwc = min Page address cycling Iccp mA2.0 Cycle Time = 1 us, 100%duty, IIO=0mA, /CS ≤ 0.2V, VIN ≤ 0.2V or VIN ≥ Vcc-0.2V Icc1 V2.2IOH = -1 mAVOHOutput High Voltage V0.4IOL = 2 mAVOLOutput Low Voltage mA0.3/CS=VIH, /UB=/LB= VIH, Other inputs = VIH or VIL ISBStandby Current(TTL) uA1-1/CS = VIH, /UB=/LB= VIH or /OE=VIH or /WE=VIL, VIO=Vss to Vcc ILOOutput Leakage Current uA1-1VIN = Vss to VccILIInput Leakage Current UnitMaxTypMinTest ConditionSymbolParameter 0.4 Vcc+0.2 3.3 Max V--0.2 VILInput Low Voltage V-0.8*VccVIHInput High Voltage V00VssGround V3.02.7VccSupply Voltage (5) UnitTypMinSymbolParameter

(March, 2005, Version 0.0) AMIC Technology, Corp. Preliminary Data Retention Electric Characteristic TA = -40℃ to 85℃ (Normal), unless otherwise specified Typ. (1) tRC 2.4 Min Refer to data retention wave form Vcc=2.4V, /CS=/PD=VIH＞Vcc-0.2V or /UB,/LB≥Vcc-0.2V, V IN≥VCC-0.2V or VIN≤VSS + 0.2V /CS=/PD=VIH＞Vcc-0.2V or /UB,/LB≥Vcc-0.2V, VI N≥VCC-0.2V or VIN≤VSS + 0.2V Test Condition 100 3.3 Max tR tCDR IccDR VDR Symbol nsOperating Recovery Time nsChip Deselect to Data Retention Time uAData Retention Current VVoltage for Data Retention UnitItem (1) Vcc = 2.4V, TA = 25℃ Data Retention Wave Form VCC 2.7V VIH VDR VSS Data Retention Mode /CS ≥ Vcc-0.2V tCDR tR /CS

(March, 2005, Version 0.0) AMIC Technology, Corp. Preliminary AC TEST CONDITIONS TA = -40℃ to 85℃ (Normal), unless otherwise specified AC TEST LOADS Note : (1) Including jig and scope capacitance TTL CL(1) CL = 30pF + 1TTL LoadOutput Load 1.5VInput and Output Timing Reference Level 5nsInput Rise and Fall Time 0.4V to 2.2VInput Pulse Level ValuePARAMETER POWER UP TIME At starting, maintain stable power for a minimum 100us with /CS = /PD = high.

(March, 2005, Version 0.0) AMIC Technology, Corp. Preliminary Unit 70ns SymbolParameter List ns0tASAddress Set-up Time ns10tPPage Write Precharge Time ns35tPWCPage Write Cycle Time ns5tOWEnd of Write to Output Low-Z ns20tPDWPage Write Data to Write Time overlap ns10tPPage Read Precharge Time ns10tOHOutput Hold from Address Change ns35tPRCPage Read Cycle Time ns35tPAAPage Read Address Access Time ns250tOHZOutput Disable to High-Z Output ns250tBHZ/UB, /LB Disable to High-Z Output ns250tHZChip Disable to High-Z Output ns5tOLZOutput Enable to Low-Z Output ns10tBLZ/UB, /LB Enable to Low-Z Output ns10tLZChip select to Low-Z Output ns70tBA/UB,/LB Access Time ns35tOEOutput Enable to Valid Output ns70tCOChip Select to Output ns70tAAAddress Access Time ns70tRCRead Cycle Time R E A D ns60tAWAddress Valid to End of Write ns0tWRWrite Recovery Time ns50tWPWrite Pulse Width ns60 tBW/UB, /LB Valid to End of Write ns60tCWChip Select to End of Write ns70tWCWrite Cycle Time W R I T E ns0tPDHPage Write Data Hold from Write Time ns0tDHData Hold from Write Time ns40tDWData to Write Time Overlap ns200tWHZWrite to Output High-Z MaxMin AC CHARACTERISTICS (Vcc = 2.7 ~ 3.3V, TA = -40 to 85℃)

(March, 2005, Version 0.0) AMIC Technology, Corp. Preliminary READ CYCLE (/PD = /WE = VIH) Note (READ CYCLE) : 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels 2. At any given temperature and voltage condition, tHZ(max.) is less than tLZ(min.) both for a given device and from device to device. 3. /WE is high for the read cycle. 4. Do not access device with cycle timing shorter than tRC for continuous periods > 16us. TIMING DIAGRAMS tRC tAA tCO tBA tOE tHZ(1,2) tOHZ(1) Address(A2 – A19) Page Address(A0 – A1) /CS /UB,/LB /OE DATA OUT tP tLZ(2)tAS

(March, 2005, Version 0.0) AMIC Technology, Corp. Preliminary PAGE READ CYCLE (/PD = /WE = VIH) Note (PAGE MODE READ CYCLE) : 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels 2. At any given temperature and voltage condition, tHZ(max.) is less than tLZ(min.) both for a given device and from device to device. 3. /WE is high for the read cycle. 4. Do not access device with cycle timing shorter than tRC for continuous periods > 16us. 5. tP (precharge time) should be guaranteed for new Address. 6. After initial page access is accomplished, the page mode operation provides fast read access speed of random locations within that page tRC tAA tCO tBA tOE tHZ(1,2) tOHZ(1) Address (A2-A19) Page Corresponding (A0-A1) Addresses /CS /UB,/LB /OE DATA OUT tPRC tPAA tP(5) tLZ(2)tAS

(March, 2005, Version 0.0) AMIC Technology, Corp. Preliminary WRITE CYCLE 1 (/CS Controlled, /PD = VIH) ADDR Data Valid tWRtAS tDW tDH tAW tCW /CS Data In Data Out tBW tWC High-Z High-Z High-Z tWP /WE /UB,/LB Notes (WRITE CYCLE) : 1. A write occurs during the overlap of a low /CS and low /WE. A write begins at the latest transition among /CS going low and /WE going low: A write end at the earliest transition among /CS going high and /WE going high. tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the later of /CS going low to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends as /CS. 5. Do not access device with cycle timing shorter than tRC for continuous periods > 16us. WRITE CYCLE 2 (/UB /LB Controlled, /PD = VIH) tP ADDR Data Valid tWR(4) tAS(3) tWP tDW tDH tWC tAW tCW(2) /CS /WE Data In Data Out /UB,/LB tBW High-Z tP

(March, 2005, Version 0.0) AMIC Technology, Corp. Preliminary PAGE MODE WRITE CYCLE (/PD = VIH) Notes (PAGE MODE WRITE CYCLE) : 1. A write occurs during the overlap of a low /CS and low /WE. A write begins at the latest transition among /CS going low in initial page mode . A write end at the earliest transition among /CS going high and Page Address transition. tWP is measured from the beginning of write to the end of write in initial page access. 2. tPWC is measured from Page Address trasition (After initial page access) to Page Address transition or /CS going high. 2. tCW is measured from the later of /CS going low to the end of write in initial page access. 3. tAS is measured from the address valid to the beginning of write. 4. Do not access device with cycle timing shorter than tRC for continuous periods > 16us. 5. tP (precharge time) should be guaranteed for new Page Address. 6. After initial page access is accomplished, the page mode operation provides fast read access speed of random locations within that page tWC tBW tWP(1) tPDH Address(A2 – A19) Page Address(A0 – A1) /CS /UB,/LB /WE DATA IN tPWC tP tPDW tCW(3) tDHtDW DATA OUT High-Z tAS(1) tPDHtPDW

(March, 2005, Version 0.0) AMIC Technology, Corp. Preliminary

Ordering Information

48B Pb-Free Mini BGA2070A64S06161AG-70UF 48B Mini BGA2070A64S06161AG-70U 48B Pb-Free Mini BGA2070A64S06161AG-70F 48B Mini BGA2070A64S06161AG-70 PackageOperating Current Max. (mA) Access Time (ns)Part No.

  • Note : -U is for -40c ~ 85c temperature grade

(March, 2005, Version 0.0) AMIC Technology, Corp. Preliminary PACKAGE DIMENSION FOR BGA TYPE 48 BALL FINE PITCH 6mm x 8mm BGA(0.75mm ball pitch) B E B #A1 C Unit: millimeters B/2 C A1 INDEX MARK 6 5 4 3 2 1 H G F E D C B A C1 / 2 0.10--Y 0.300.250.20E2 0.90--E1 1.20--E 0.400.350.30D -5.25-C1 8.108.007.90C -3.75-B1 6.106.005.90B -0.75-A MaxTypicalMin D C Side View Top View Bottom View A Y 0.25/Typ. 0.90/Typ.