A64E06161 AMICC | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 20

Technical content

Preliminary 1M X 16 Bit Low Voltage Super RAM Document Title 1M X 16 Bit Low Voltage Super RAM

Revision History

Rev. No. History Issue Date Remark

0.0 Initial issue October 12, 2003 Preliminary

0.1 Change VCC range and VCCQ range November 30, 2004

Change page access time from 20ns to 25ns Change operation current (ICC1) from 25mA to 15mA(-70) Change operation current (ICC1) from 20mA to 12mA(-85) Change standby current (ISB1) from 80uA to 100uA Delete reduce memory size 16M, partial array refresh 16M Change operation current (ICC2) form 5mA to 3mA(-70, -85) Change PAR current 12Mb=90uA, 8Mb=80uA, 4Mb=70uA Change TCR current +85°C=100uA +70°C=90uA Change TCR current +45°C=85uA +15°C=75uA PRELIMINARY (November, 2004, Version 0.1) AMIC Technology, Corp.

Preliminary 1M X 16 Bit Low Voltage Super RAM

Features

„ Operating voltage: VCC: 1.7V to 1.95V VCCQ: 1.7V to VCC „ Access times: tAA = 70ns (max.) „ Page Access times: tPAA = 25ns (max) „ Current: A64E06161 series: Operating Current (Icc1) : 15mA (max.) Standby Current (Isb1) : 100uA (max) Deep Power Down Standby Current (IZZ) : 10µA (max.) „ 4-word page length „ Support 4 d istinct op eration modes for r educing stand by power : Deep Power Down (DPD) mode Reduce Memory Size (RMS) mode (4M, 8M, 12M) Partial Array Refresh (PAR) mode (4M,8M,12M) Temperature Compensated Refresh (TCR) mode „ Industrial oper ating temp erature rang e: -25 °C to +85 °C for – I „ Available in 48-ball Mini BGA (6X8) package. General Description The A64E061 61 is a lo w operating current 16,777,2 16-bit super RAM or ganized as 1, 048,576 word b y 16 bit an d operated on l ow power supply voltage from 1.7V to 1.95V. It is built usin g AMIC’s high performance CMOS DRAM process. Using hidden refresh technique, the A64E06161 provides a compatible asynchronous interface and data can be read in 4-word page mode for fast access times. T he A64E06161 has an intern al register nam ed the Config uration Re gister (CR) that controls the op eration. The A64E0 6161 is designed for reduci ng c urrent consumptio n durin g hi dden self refresh and op erating th rough foll owing mod e: Dee p Power Do wn ( DPD) mode, Reduce Memo ry Size (RMS) mode, Partial Array Refresh (PAR) mode and Temperature Compensated refresh (TCR) mode. This A64E06161 is suited for low power application such as mobile phone and PDA or other battery-operated handheld device. Pin Configuration „ Mini BGA (6X8) Top View 1 2 3 4 5 6 A LB OE A0 A1 A2 ZZ B I/O8 HB A3 A4 CE I/O0 C I/O9 I/O10 A5 A6 I/O1 I/O2 D VSSQ I/O11 A17 A7 I/O3 VCC E VCCQ I/O12 NC A16 I/O4 VSS F I/O14 I/O13 A14 A15 I/O5 I/O6 G I/O15 A19 A12 A13 WE I/O7 H A18 A8 A9 A10 A11 NC A64E06161G PRELIMINARY (November, 2004, Version 0.1) 1 AMIC Technology, Corp.

16,777,216 MEMORY ARRAY COLUMN I/OINPUT DATA CIRCUIT CONTROL CIRCUIT VCC VCCQ I/O7 I/O0 A19 A18 WE HB INPUT DATA CIRCUIT I/O8 I/O15 ZZ LB OE CE VSS VSSQ Pin Description Symbol Description A0 - A19 Address Inputs CE Chip Enable Input ZZ Sleep Enable Input (When ZZ is low, the CR register can be loaded or the device can enter DPD mode or PAR mode). I/O0 - I/O15 Data Input/Outputs WE Write Enable Input LB Byte Enable Input (I/O0 to I/O7) HB Byte Enable Input (I/O8 to I/O15) OE Output Enable Input VCC Power VSS Ground VCCQ Provide isolated power to I/O for improved noise immunity VSSQ Provide isolated / Ground to I/O for improved noise immunity NC No Connection or VSSQ PRELIMINARY (November, 2004, Version 0.1) 2 AMIC Technology, Corp.

Recommended DC Operating Conditions (TA = 0°C to + 70°C or -25°C to 85°C) Symbol Parameter Min. Max. Unit VCC Supply Voltage 1.7 1.95 V VSS Ground 0 0 V VCCQ Supply Voltage I/O only 1.7 VCC V VSSQ Ground I/O only 0 0 V VIH Input High Voltage 1.4 VCCQ + 0.2 V VIL Input Low Voltage -0.2 +0.4 V CL Output Load - 30 pF Absolute Maximum Ratings* *Comments Stresses ab ove t hose list ed und er "A bsolute Ma ximum Ratings" ma y cause permanent d amage to t his dev ice. These are st ress ratings only. Functional operation of this device at t hese or an y ot her cond itions above t hose indicated in t he operational sections of this specification is not impl ied o r int ended. Exp osure t o t he abs olute maximum rating conditions for extended periods may affect device reliability. Symbol Parameter -70 -85 Unit Conditions Min. Max. Min. Max. ⎜ILI⎥ Input Leakage Current - 1 - 1 µA VIN = GND to VCCQ ⎜ILO⎥ Output Leakage Current - 1 - 1 µA CE = VIH or ZZ = VIL or OE = VIH or WE = VIL VI/O = GND to VCCQ ICC1 - 15 - 12 mA Min. Cycle, Duty = 100% CE = VIL, ZZ = VIH VIH = VCCQ, VIL = 0V, II/O = 0mA ICC2 Dynamic Operating Current - 3 - 3 mA CE = VIL, ZZ = VIH VIH = VCCQ, VIL = 0V, f = 1MHz, II/O = 0mA ISB1 Standby Power Supply Current - 100 - 100 µA CE ≥ VCCQ - 0.2V ZZ ≥ VCCQ - 0.2V VIN ≥ 0V VOL Output Low Voltage - 0.2 - 0.2 V IOL = 0.2 mA VOH Output High Voltage VCCQ-0.2 - VCCQ-0.2 - V IOH = -0.2mA PRELIMINARY (November, 2004, Version 0.1) 3 AMIC Technology, Corp.

Deep Power Down Specifications and Conditions Symbol Description Conditions Typ. Max. Units IZZ Deep Power-Down VIN = VCCQ or 0V; +25°C ZZ = LOW CR[4] = 0 10 µA Partial Array Refresh Specifications Conditions Symbol Description Conditions Density Array Partition Typ. Max. Units 12Mb 3/4 90 µA 8Mb 1/2 80 µA IPAR Partial Array Refresh Current VIN = VCCQ or 0V ZZ = LOW CR[4] = 1 4Mb 1/4 70 µA Note: IPAR (MAX) values measured with TCR set to 85°C Temperature Compensated Refresh Specifications Conditions Symbol Description Conditions Density Max Case Temperatures Typ. Max. Units +85°C 100 µA +70°C 90 µA +45°C 80 µA ITCR Temperature Compensated Refresh Standby Current VIN = VCCQ or 0V Chip Disabled 16Mb +15°C 70 µA Note: 1. ITCR (MAX) values measured with FULL ARRAY refresh. 2. This device assumes a standby mode if the chip is disabled (CE HIGH). Truth Table CE ZZ OE WE LB HB I/O0 to I/O7 Mode I/O8 to I/O15 Mode VCC Current H H X X X X Not selected Not selected ISB1 H L X X X X Not selected Not selected IZZ*2 H L X X X X Not selected Not selected IPAR*2 L L X L X X Not selected Not selected Load CR Register L L Read Read ICC1, ICC2 L H L H L H Read High - Z ICC1, ICC2 H L High - Z Read ICC1, ICC2 L L Write Write ICC1, ICC2 L H X L L H Write Not Write/Hi - Z ICC1, ICC2 H L Not Write/Hi - Z Write ICC1, ICC2 L H H H X X High - Z High - Z ICC1, ICC2 Note: 1. X = H or L 2. DPD is enable when CR register A4 is “0”; otherwise, PAR is enable PRELIMINARY (November, 2004, Version 0.1) 4 AMIC Technology, Corp.

Capacitance (TA = 25°C, f = 1.0MHz) Symbol Parameter Min. Max. Unit Conditions CIN* Input Capacitance - 6 pF VIN = 0V CI/O* Input/Output Capacitance - 6 pF VI/O = 0V * These parameters are sampled and not 100% tested. Initialization The A64E06161 is initialized in the power-on sequence according to the following. 1. To stabilize internal circuits, after turning on the power, a 200µs or longer wait time must precede any signal toggling. 2. After the wait time, it can be normal operation. Power on Chart VCC VCC(min) CE ZZ 200us Wait Time Normal Operation Notes: 1. Following power application, make CE high level during the wait time 200us interval. 2. After power on sequence, the normal operating ZZ must keep at high. Standby Mode State Machines Power On Initial State Active Mode PAR Mode (12M/8M/4M bits)Standny Mode DPD Mode (Data Invalid) Wait 200us CE = VIH CE = VIL ZZ = VIH CE = VIL ZZ = VIH CE = VIH ZZ = VIH CE = VIH ZZ = VIL CE = VIH, ZZ = VIL CE = VIH, ZZ = VIL CE = VIH, ZZ = VIL CE = VIL, ZZ = VIH HB or/and LB = VIL CE = VIH, ZZ = VIH CE = VIH, ZZ = VIH Note: DPD is enable when CR register A4 is “0”; otherwise, PAR is enable. PRELIMINARY (November, 2004, Version 0.1) 5 AMIC Technology, Corp.

The conf iguration r egister (CR) d efines ho w t he A64E06161 operat es and whether page mode read accesses ar e permit ted. T he reg ister is aut omatically loaded with d efault set ting durin g po wer on an d can be updated anytime while the device is op erating in a n ormal state. CR Register Description Reserved PAGE TCR ZZ Enable Deep Sleep Array On/Off on ZZ PAR Top/Bottom Selection PAR Memory Selection A19 - A8 A7 A6 A5 A4 A3 A2 A1 A0 Bit(s) Name Deserved A19 - A8 Reserved Reserved, All must be set to “0”

7 Page Mode on/off 0 - Page Mode Disabled (Default)

6, 5 Temperature Compensated Register Section 11 - +85°C (Default) 00 - +70°C 01 - +45°C 10 - +15°C

4 ZZ Enable Deep Sleep

1 - DPD Mode Disabled (Default)

3 Array On/Off on ZZ 0 - PAR Mode (Default)

2 PAR Top/Bottom Half Selection 0 - Bottom (Default)

1 - 0 PAR Memory Selection 01 - 3/4 Array (12M) 10 - 1/2 Array (8M) 11 - 1/4 Array (4M) PRELIMINARY (November, 2004, Version 0.1) 6 AMIC Technology, Corp.

CR Register Update – Timing Waveform tWC Eight Lower-order address bits (A7-A0) Define PAR Register tCW tWR tZZCE tAW tAS tWP tZZWE tZZMIN CE Address WE ZZ Figure 1: CR register update–Timing waveform Notes: 1. V IH(MAX) = VCCQ + 0.2V for pulse durations less than 20ns. 2. V IL(MIN) = -1V for pulse duration less than 20ns. 3. Overshoot and undershoot specifications are characterized and are not 100% tested. 4. Typical values are inclu ded for reference only and are no t guaranteed or tested. Typical values are measured at VCC = VCC(typ.) and TA = 25°C. 5. The timing values for the CR Register Update are shown in the “Partial Array Mode Timing” table and “AC Characteristics” table. PRELIMINARY (November, 2004, Version 0.1) 7 AMIC Technology, Corp.

The Page Mode op eration t akes adv antage of t he f act that adjacent address can be rea d in short er period of time than random ad dresses. W rite oper ations do n ot sup port comparable page mod e f unctionality. T he Page Mod e operation can be enabled and disabled in the CR register. If the CR register bit A7 is set to a “1”, Page Mode operation is enabled. The A64E061 61 prov ides f ollowing op eration mo de f or reducing power: 1. Deep Power Down (DPD) mode 2. Reduce Memory Size (RMS) mode 3. Partial Array Refresh (PAR) mode 4. Temperature Compensated Refresh (TCR) mode 1. Deep Power Down (DPD) mode In t his mode, the int ernal ref resh is t urned of f and all dat a integrity of the array is lost . Deep Po wer Down (DPD) mode is entered by ZZ low and keep 10us with A4 r egister bit set to a ” 0”. The device stays in the Deep Po wer Down (DPD) mode unt il ZZ is driven Hi gh. I f t he A4 register bit is set equal t o “1”, Deep P ower Down (DP D) mode will not be activated. Once the A64E06161 exits the Deep Power Down (DPD) mode, the content of the CR register is destroyed and the CR regist er would go int o the default state upon n ormal operation. 2. Reduce Memory Size (RMS) mode In this mode, the A64E06161 can be operat ed as a reduc ed size dev ice. For exampl e, one ca n o perate t he 1 6M A64E06161 as a 4M or 8M memory block. Reduce Mem ory Size (RMS) mode ca n be enabled by having the appropriate setting in t he CR regist er. T he mod e is ef fective once ZZ goes h igh and remains i n t he Red uce Me mory Siz e (R MS) mode u ntil f ull arra y rest ored b y set ting t he CR reg ister again. At po wer on, all f our sect ion o f t he devic e are activated an d t he A64E0 6161 ent er int o it s def ault st ate of full memory size and refresh space. Variable Address Space – Address Patterns Partial Array Refresh Mode (A3 =0, A4 = 1) A2 A1, A0 Refresh Section Address Size Density 0 11 One-fourth of the Die 00000h - 3FFFFh (A19 = A18 = 0) 256K × 16 4M 0 10 Half of the Die 00000h - 7FFFFh (A19 = 0) 512K × 16 8M 0 01 Three-fourths of the Die 00000h - BFFFFh (A19 : A18 ≠ 11) 768K × 16 12M 1 11 One-fourth of the Die C0000h - FFFFh (A19 = A18 = 1) 256K × 16 4M 1 10 Half of the Die 80000h - FFFFFh (A19 = 1) 512K × 16 8M 1 01 Three-fourths of the Die 40000h - FFFFFh (A19: A18 ≠ 00) 768K × 16 12M Reduced Memory Size Mode (A3 = 1, A4 = 1) 0 11 One-fourth of the Die 00000h - 3FFFFh (A19 = A18 = 0) 256K × 16 4M 0 10 Half of the Die 00000h - 7FFFFh (A19 = 0) 512K × 16 8M 0 01 Three-fourths of the Die 00000h - BFFFFh (A19 : A18 ≠ 11) 768K × 16 12M 1 11 One-fourth of the Die C0000h - FFFFh (A19 = A18 = 1) 256K × 16 4M 1 10 Half of the Die 80000h - FFFFFh (A19 = 1) 512K × 16 8M 1 01 Three-fourths of the Die 40000h - FFFFFh (A19 : A18 ≠ 00) 768K × 16 12M PRELIMINARY (November, 2004, Version 0.1) 8 AMIC Technology, Corp.

Active Address Space: A0-A17 A<18,19> = <0,0> 0 1 0 1 0 1 0 1 0 1 0 1 1/2 Address Space Refresh Active Address Space: A0-A18 A<19> = <0> Full Address Space Refresh Active Address Space: A0-A19 A<18,19> = <X, X> 3/4 Address Space Refresh Active Address Space: A0-A19 Top Address Range 1/4 Address Space Refresh Active Address Space: A0-A17 A<18,19> = <1,1> 3/4 Address Space Refresh Active Address Space: A0-A19 Full Address Space Refresh Active Address Space: A0-A19 A<18,19> = <X, X> 1/2 Address Space Refresh Active Address Space: A0-A18 A<19> = <1> PRELIMINARY (November, 2004, Version 0.1) 9 AMIC Technology, Corp.

  1. Partial Array Refresh (PAR) mode In this mode, customers can turn off section of A64E06161 in stand-by mod e t o save st andby current. The A64E06161 is divided i nto f our 4M sect ions allo wing cert ain sect ion t o be active. T he array partition t o be ref reshed i s determined by the respective bit in the CR register. When ZZ is active low, only the portion of the array that is set in the CR reg ister is refreshed an d t he dat a is keep at a c ertain sect ion of memory. T he Part ial Arra y Ref resh (PA R) mode is o nly available dur ing st andby t ime ( ZZ low). Once ZZ is turned high, t he A64 E06161 go es back t o opera ting in f ull arr ay refresh. F or Part ial Arra y Refresh (PAR ) mode t o b e activated, the register bit, A4 must be set to a “1” value. To change the address space of the Partial Array Refresh (PAR) mode, t he C R regist er mu st be updat ed usin g t he CR register description. I f t he CR regist er is not upd ated after power on, the A64E06161 will be in it s default state and t he whole memory array will be refreshed. Partial Array Refresh – Entry/Exit Partial Array Mode/ Deep Power Down Mode CE or UB / LB 1us suspend tCDR tR ZZ Figure 2: Partial Array refresh – Entry/Exit Partial Array Mode Timings Parameter Description Min. Max. Unit tZZWE ZZ LOW to WE LOW 1 µs tCDR Chip Deselect to ZZ LOW 0 µs tR Operation Recovery Time (Deep Power Down Mode only) 200 µs tZZMIN Deep Power Down Mode Time 10 µs tZZCE ZZ LOW to CE LOW 0 1 µs tZZBE ZZ LOW to LDUB / LOW 0 1 µs Notes: 1. OE and the data pins are in a “don’t care” state while the device is in Partial Array Mode. 2. All other timing parameters are as shown in the switching characteristics section. 3. tR applies only in the Deep Power Down Mode. 4. Temperature Compensated Refresh (TCR) mode In this mode, the hidden refresh rate can be optimized for the operating temperature. At higher temperature, the DRAM cell must be ref reshed more often than at lower temperature. By setting t he t emperature of oper ation i n CR regist er, t he refresh ra te ca n be o ptimized to mee t th e l ow standby current at giv en op erating temperature. T here are f our selections (+15°C, +45°C, +70°C, +85°C) in t he CR regist er description. PRELIMINARY (November, 2004, Version 0.1) 10 AMIC Technology, Corp.

AC Characteristics (TA = 0°C to + 70°C or -25°C to 85°C, VCC = 1.7V to 1.95V, VCCQ = 1.7V to VCC GND = 0V) Symbol Parameter -70 -85 Unit Min. Max. Min. Max. Read Cycle tRC Read Cycle Time 70 10000 85 10000 ns tSKEW Address Skew - 10 - 10 ns tAA Address Access Time - 70 - 85 ns tACE Chip Enable Access Time - 70 - 85 ns tBE Byte Enable Access Time - 35 - 45 ns tOE Output Enable to Output Valid - 35 - 45 ns tCLZ Chip Enable to Output in Low Z 5 - 5 - ns tBLZ Byte Enable to Output in Low Z 5 - 5 - ns tOLZ Output Enable to Output in Low Z 5 - 5 - ns tCHZ Chip Disable to Output in High Z 0 14 0 14 ns tBHZ Byte Disable to Output in High Z 0 14 0 14 ns tOHZ Output Disable to Output in High Z 0 14 0 14 ns tOH Output Hold from Address Change 10 - 10 - ns tASC Address Setup to CE Low 0 - 0 - ns tAHC Address Hold Time from CE High 0 - 0 - ns tCEH CE High Pulse With 10 - 10 - ns tPC Page Read Cycle Time 25 - 25 - ns tPAA Page access Time - 25 - 25 ns tNPPC Normal to Page Read Cycle Time - 10 - 10 µs Write Cycle tWC Write Cycle Time 70 10000 85 10000 ns tSKEW Address Skew - 10 - 10 ns tCW Chip Enable to End of Write 70 - 85 - ns tBW Byte Enable to End of Write 60 - 70 - ns tAS Address Setup Time 0 - 0 - ns tAW Address Valid to End of Write 70 - 85 - ns tWP Write Pulse Width 50 - 60 - ns tWR Write Recovery Time 0 - 0 - ns tWHZ Write to Output in High Z - 14 - 14 ns tDW Data to Write Time Overlap 30 - 35 - ns tDH Data Hold from Write Time 0 - 0 - ns tOW Output Active from End of Write 5 - 5 - ns tASC Address Setup to CE Low 0 - 0 - ns tAHC Address Hold Time from CE High 0 - 0 - ns tCEH CE High Pulse With 10 - 10 - ns tWEH WE High Pulse With 10 - 10 - ns tCEM Maximum CE Pulse width - 10 - 10 µs Note: t CHZ, t BHZ and tOHZ and t WHZ are d efined as t he t ime at which t he out puts achiev e t he ope n circu it condit ion and a re not referred to output voltage levels. PRELIMINARY (November, 2004, Version 0.1) 12 AMIC Technology, Corp.

Read Cycle 1(1, 2, 4, 6) Address DOUT CE tSKEW tRC tSKEW tRC tAA tOH tAA tOH tASC Read Cycle 2-1(1, 3, 6) tRC tRC tSKEWtSKEW tASC tAA tAHC tCEH tASC tAHC tAA tACE tCLZ5 tBE tBLZ5 tOE tOLZ5 tCHZ5 tBHZ5 tOHZ5 tACE tCLZ5 tBLZ5 tOE tOLZ5 tOHZ5 tBHZ5 tCHZ5 Address CE HB LB, OE DOUT tBE PRELIMINARY (November, 2004, Version 0.1) 13 AMIC Technology, Corp.

Read Cycle 2-2(1, 3, 6) tRC tRC tSKEWtSKEW tASC tAHC tACE tCLZ5 tBE tBLZ5 tOE tOLZ5 tBHZ5 tOHZ5 tBLZ5 tOE tOLZ5 tOHZ5 tBHZ5 tCHZ5 Address CE HB LB, OE DOUT tBE tSKEW tAA tAA Notes: 1. WE is high for Read Cycle. 2. Device is continuously enabled CE = VIL, HB = VIL and, or LB = VIL. 3. Address valid prior to or coincident with CE and (HB and, or LB ) transition low. 4. OE = VIL. 5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested. 6. ZZ is high for Read Cycle. Timing Waveforms Words Page Read Cycle Timing Chart Address A2~A19 tSKEWtPCtPC tNPPC tRC tSKEW tPC tCHZ tOH tPAAtACE tOHZ tBHZtOE tBE Page Address (A0~A1) CE I/O (Output) OE, HB, LB AN AN+1 AN+2 AN+3 QN+2QN+1QN QN+3 tOH tPAA tOH tPAA tOH tASC tAHC PRELIMINARY (November, 2004, Version 0.1) 14 AMIC Technology, Corp.

Timing Waveforms (continued) Write Cycle 1-1(6) (Write Enable Controlled) tWC tWC tSKEWtSKEW tASC tAHC tCEH tASC tAHC Address CE HB LB, tAW tCW tAW tCW tBW tBW tWR3 tWR3tAS1 tWP2 tDW tDH tWHZ4 tOW tWP2 tAS1 tWHZ4 tDHtDW tOW WE Data In Data Out Write Cycle 1-2(6) (Write Enable Controlled) tWC tWC tSKEWtSKEW tASC tAHC Address CE HB LB, tBW tBW tWR3 tWR3tAS1 tWP2 tDW tDH tWHZ4 tOW tWP2 tAS1 tWHZ4 tDHtDW tOW WE Data In Data Out tWEH tSKEW PRELIMINARY (November, 2004, Version 0.1) 15 AMIC Technology, Corp.

Timing Waveforms (continued) Write Cycle 2-1(6) (Chip Enable Controlled) tWC tWC tSKEWtSKEW tASC tCEH tASC Address CE HB LB, tAW tCW2 tAW tCW2 tBW tWP tDW tDH tWHZ4 tOW tWP tWHZ4 tDHtDW tOW WE Data In Data Out tAHC tAHC tBW tWR3 tWR3 Timing Waveforms Write Cycle 3-1(6) (Byte Enable Controlled) tWC tWC tSKEWtSKEW tASC tCEH tASC Address CE HB LB, tAW tCW tAW tCW tBW2 tWP tDW tDH tWHZ4 tOW tWP tWHZ4 tDHtDW tOW WE Data In Data Out tAHC tAHC tBW2 tWR3 tWR3 tAS1 tAS1 PRELIMINARY (November, 2004, Version 0.1) 16 AMIC Technology, Corp.

Notes: 1 . tAS is measured from the address valid to the beginning of Write.

  1. A Write occurs during the overlap (tWP, tBW) of a low CE , WE and (HB and, or LB ).
  2. tWR is measured from the earliest of CE or WE or (HB and, or LB ) going high to the end of the Write cycle.
  3. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
  4. ZZ is high for Write Cycle.

Figure 5. Output Load Circuit PRELIMINARY (November, 2004, Version 0.1) 17 AMIC Technology, Corp.

Ordering Information

Part No. Access Time (ns) Operating Current Max. (mA) Deep Power Down Mode Standby Current Max. (µA) Package A64E06161G-70 70 15 10 48B Mini BGA A64E06161G-85 85 12 10 48B Mini BGA A64E06161G-70I 70 15 10 48B Mini BGA A64E06161G-85I 85 12 10 48B Mini BGA Note: -I is for industrial operating temperature range PRELIMINARY (November, 2004, Version 0.1) 18 AMIC Technology, Corp.

Package Information

48LD CSP (6 x 8 mm) Outline Dimensions unit: mm (48TFBGA) A B C D E F G H TOP VIEW Ball#A1 CORNER SIDE VIEW C SEATING PLANE A A B C D E F G H 1 234 56 123456 C 0.10 CS

0.25 S A B

b (48X) BOTTOM VIEW Ball*A1 CORNER E e B e D A 0.20(4X) 0.10 C Dimensions in mm Symbol MIN. NOM. MAX. A --- --- 1.20 A1 0.20 0.25 0.30 D 5.90 6.00 6.10 E 7.90 8.00 8.10 D1 --- 3.75 --- E1 --- 5.25 --- e --- 0.75 --- b 0.30 0.35 0.40 Note: 1. THE BALL DIAMET ER, BALL PIT CH, S TAND-OFF & PACK AGE THICKNESS ARE DIFFERENT FROM JEDEC SPEC MO192 (LOW PROFILE BGA FAMILY). 2. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 3. DIMENSION b IS MEASURED AT THE MAXIMUM. THERE SHALL BE A MINIM UM CLEARANCE OF 0.25mm BETWEEN THE EDGE OF THE SOLDER BALL AND THE BODY EDGE. 4. BALL PAD OPENING OF SUBSTRATE IS Φ 0.3mm (SMD) SUGGEST TO DESIGN THE PCB LAND SIZE AS Φ 0.3mm (NSMD) PRELIMINARY (November, 2004, Version 0.1) 19 AMIC Technology, Corp.