A63L83361

A63L83361_15 AMICC | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 16

Technical content

256K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Flow-through Data Output (April, 2007, Version 1.0) AMIC Technology, Corp. Document Title 256K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Flow- through Data Output

Revision History

Rev. No. History Issue Date Remark

0.0 Initial issue July 14, 2005 Preliminary

1.0 Final version release April 27, 2007 Final

256K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Flow-through Data Output (April, 2007, Version 1.0) 1 AMIC Technology, Corp.

Features

„ Fast access times: 6.5/ 7.5/8.0 ns(153/133/117 MHz) „ Single 3.3V ±5% power supply „ Synchronous burst function „ Individual Byte Write control and Global Write „ Three separate chip enables allow wide range of options for CE control, address pipelining „ Selectable BURST mode „ SLEEP mode (ZZ pin) provided „ Available in 100-pin LQFP package „ Industrial operating te mperature range: -25°C to +85°C for -I series „ All Pb-free (lead-free) product are RoHS compliant General Description The A63L83361 is a high-speed SRAM containing 9M bits of bit synchronous memory, organized as 256K words by 36 bits. The A63L83361 combines advanced synchronous peripheral circuitry, 2-bit burst control, input registers, output buffer and a 256K X 36 SRAM core to provide a wide range of data RAM applications. The positive edge triggered single clock input (CLK) controls all synchronous inputs passing through the registers. Synchronous inputs include all addresses (A0 - A17), all data inputs (I/O 1 - I/O 36 ), active LOW chip enable ( CE ), two additional chip enables (CE2, CE2 ), burst control inputs ( ADSC , ADSP , ADV ), byte write enables ( BWE , BW1 , BW2 , BW3 , BW4 ) and Global Write ( GW ). Asynchronous inputs include output enable ( OE ), clock (CLK), BURST mode (MODE) and SLEEP mode (ZZ). Burst operations can be initiated with either the address status processor ( ADSP ) or address status controller ( ADSC ) input pin. Subsequent burst sequence burst addresses can be internally generated by the A63L83361 and controlled by the burst advance ( ADV ) pin. Write cycles are internally self-timed and synchronous with the rising edge of the clock (CLK). This feature simplifies the write interface. Individual Byte enables allow individual bytes to be written. BW1 controls I/O1 - I/O 9, BW2 controls I/O 10 - I/O 18, BW3 controls I/O19 - I/O 27, and BW4 controls I/O 28 - I/O 36, all on the condition that BWE is LOW. GW LOW causes all bytes to be written.

(April, 2007, Version 1.0) 2 AMIC Technology, Corp. Pin Configuration I/O20 I/O21 VCCQ GNDQ I/O22 I/O23 I/O24 I/O25 GNDQ I/O26 I/O27 VCCQ VCC NC I/O34 GND I/O28 I/O29 VCCQ GNDQ I/O30 I/O31 I/O32 I/O33 GNDQ VCCQ I/O35 I/O I/O16 VCCQ GNDQ I/O I/O14 I/O13 I/O12 GNDQ VCCQ I/O I/O10 GND NC VCC ZZ I/O I/O7 VCCQ GNDQ I/O I/O5 I/O4 I/O3 GNDQ VCCQ I/O I/O1 A16 A15 A14 A13 A12 A11 A10 VCC GND NC MODE 100 CE2 CLK GND VCC A63L83361E NC ADV ADSP ADSC OE BWE GW CE2 BW1 BW2 BW3 BW4 CE A17 I/O9 I/O18I/O19 I/O36 NC NC

(April, 2007, Version 1.0) 3 AMIC Technology, Corp. Block Diagram MODE LOGIC CLK LOGIC ADDRESS REGISTERS BURST LOGIC ADDRESS COUNTER CLR BYTE WRITE ENABLE LOGIC BYTE1 WRITE DRIVER BYTE2 WRITE DRIVER BYTE3 WRITE DRIVER BYTE4 WRITE DRIVER 256KX9X4 MEMORY ARRAY OUTPUT BUFFER DATA-IN REGISTERS CHIP ENABLE LOGIC OUTPUT ENABLE LOGIC ZZ MODE ADV CLK ADSC ADSP A0-A17 GW BWE BW1 BW2 BW3 BW4 CE CE2 CE2 OE I/O1 - I/O36

(April, 2007, Version 1.0) 4 AMIC Technology, Corp. Pin Description Pin No. Symbol Description 32 – 37 , 43 - 50, 81, 82, 99, 100 A0 - A17 Address Inputs

89 CLK Clock

87, 93 - 96 BWE , BW1 - BW4 Byte Write Enables

88 GW Global Write

86 OE Output Enable

92, 97, 98 CE2 ,CE2, CE Chip Enables

83 ADV Burst Address Advance

84 ADSP Processor Address Status

85 ADSC Controller Address Status

31 MODE Burst Mode: HIGH or NC (Interleaved burst)

LOW (Linear burst)

64 ZZ Asynchronous Power-Down (Snooze): HIGH (Sleep)

LOW or NC (Wake up) 52, 53, 56 - 59, 62, 63, 68, 69, 72 - 75, 78, 79,80 I/O1- I/O36 Data Inputs/Outputs 14, 16, 38, 39, 42, 66 NC No Connection 15, 41, 65, 91 VCC Power Supply 17, 40, 67, 90 GND Ground 4, 11, 20, 27, 54, 61, 70, 77 VCCQ Isolated Output Buffer Supply 5, 10, 21, 26, 55, 60, 71, 76 GNDQ Isolated Output Buffer Ground

(April, 2007, Version 1.0) 5 AMIC Technology, Corp. Synchronous Truth Table (See Notes 1 Through 5) Operation Address Used CE CE2 CE2 ADSP ADSC ADV WRITE OE CLK I/O Operation Deselected Cycle, Power-down NONE H X X X L X X X L-H High-Z Deselected Cycle, Power-down NONE L X L L X X X X L-H High-Z Deselected Cycle, Power-down NONE L H X L X X X X L-H High-Z Deselected Cycle, Power-down NONE L X L H L X X X L-H High-Z Deselected Cycle, Power-down NONE L H X H L X X X L-H High-Z READ Cycle, Begin Burst External L L H L X X X L L-H Dout READ Cycle, Begin Burst External L L H L X X X H L-H High-Z WRITE Cycle, Begin Burst External L L H H L X L X L-H Din READ Cycle, Begin Burst External L L H H L X H L L-H Dout READ Cycle, Begin Burst External L L H H L X H H L-H High-Z READ Cycle, Continue Burst Next X X X H H L H L L-H Dout READ Cycle, Continue Burst Next X X X H H L H H L-H High-Z READ Cycle, Continue Burst Next H X X X H L H L L-H Dout READ Cycle, Continue Burst Next H X X X H L H H L-H High-Z WRITE Cycle, Continue Burst Next X X X H H L L X L-H Din WRITE Cycle, Continue Burst Next H X X X H L L X L-H Din READ Cycle, Suspend Burst Current X X X H H H H L L-H Dout READ Cycle, Suspend Burst Current X X X H H H H H L-H High-Z READ Cycle, Suspend Burst Current H X X X H H H L L-H Dout READ Cycle, Suspend Burst Current H X X X H H H H L-H High-Z WRITE Cycle, Suspend Burst Current X X X H H H L X L-H Din WRITE Cycle, Suspend Burst Current H X X X H H L X L-H Din

(April, 2007, Version 1.0) 6 AMIC Technology, Corp. Notes: 1. X = "Disregard", H = Logic High, L = Logic Low. 2. WRITE = L means: 1) Any BWx (BW1 ,BW2 ,BW3 , or BW4 ) and BWE are low or 2) GW is low. 3. All inputs except OE must be synchronized with setup and hold times around the rising edge (L-H) of CLK. 4. For write cycles that follow read cycles, OE must be HIGH before the input data request setup time and held HIGH throughout the input data hold time. 5. ADSP LOW always initiates an internal Read at the L-H edge of CLK. A Write is performed by setting one or more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. Refer to the Write timing diagram for clarification. Write Truth Table Operation GW BWE BW1 BW2 BW3 BW4 READ H H X X X X READ H L H H H H WRITE Byte 1 H L L H H H WRITE all bytes H L L L L L WRITE all bytes L X X X X X

(April, 2007, Version 1.0) 7 AMIC Technology, Corp. Linear Burst Address Table (MODE = LOW) First Address (External) Second Address (Internal) Third Address (Internal) Fourth Address (Internal) Interleaved Burst Address Table (MODE = HIGH or NC) First Address (External) Second Address (Internal) Third Address (Internal) Fourth Address (Internal) Absolute Maximum Ratings* Voltage Relative to GND for any Pin Except VCC (Vin, Power Dissipation (P Operating Ranges Ambient Temperature VCC & VCCQ Supply Voltages Operating ranges define those limits between which the functionally of the device is guaranteed. *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sect ions of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. Recommended DC Operating Conditions (0°C ≤ TA ≤ 70°C, -25°C ≤ TA ≤ 85°C, VCC, VCCQ = 3.3V+5% or 3.3V-5%, unless otherwise noted) Symbol Parameter Min. Typ. Max. Unit Note VCC Supply Voltage (Operating Voltage Range) 3.135 3.3 3.465 V VCCQ Isolated Input Buffer Supply 3.135 3.3 3.465 V GND Supply Voltage to GND 0.0 - 0.0 V VIH Input High Voltage 2 - VCC+0.3 V 1, 2 VIHQ Input High Voltage (I/O Pins) 2 - VCC+0.3 V VIL Input Low Voltage -0.3 - 0.8 V 1, 2

(April, 2007, Version 1.0) 8 AMIC Technology, Corp. (0°C ≤ TA ≤ 70°C, -25°C ≤ TA ≤ 85°C, VCC, VCCQ = 3.3V+5% or 3.3V-5%, unless otherwise noted) Symbol Parameter Min. Max. Unit Test Conditions Note ⏐ILI⏐ Input Leakage Current - ±2.0 μA All inputs V IN = GND to VCC ⏐ILO⏐ Output Leakage Current - ±2.0 μA OE = VIH, Vout = GND to VCC ICC1 Supply Current 300 mA Device selected; VCC = max. Iout = 0mA, all inputs = VIH or VIL Cycle time = tKC min. 3, 11 ISB1 Standby Current mA Device deselected; VCC = max. All inputs are fixed. All inputs ≥ VCC - 0.2V or ≤ GND + 0.2V Cycle time = tKC min. ISB2 - 15 mA ZZ ≥ VCC - 0.2V VOL Output Low Voltage - 1.0 V I OL = 8 mA VOH Output High Voltage 1.6 - V I OH = -4 mA Capacitance Symbol Parameter Typ. Max. Unit Conditions CIN Input Capacitance 3 4 pF TA = 25 C; f = 1MHz CI/O Input/Output Capacitance 4 5 pF VCC = 3.3V * These parameters are sampled and not 100% tested.

(April, 2007, Version 1.0) 9 AMIC Technology, Corp. AC Characteristics (0°C ≤ TA ≤ 70°C, -25°C ≤ TA ≤ 85°C, VCC = 3.3V+5% or 3.3V-5%) Symbol Parameter -6.5 -7.5 -8.5 Unit Note TKC Clock Cycle Time 7.5 - 8.5 - 10 - ns TKH Clock High Time 2.5 - 2.8 - 3.0 - ns TKL Clock Low Time 2.5 - 2.8 - 3.0 - ns TKQ Clock to Output Valid - 6.5 - 7.5 - 8.5 ns tKQX Clock to Output Invalid 3.0 - 3.0 - 3.0 - ns tKQLZ Clock to Output in Low-Z 2.5 - 2.5 - 2.5 - ns 5, 6 tKQHZ Clock to Output in High-Z - 3.5 - 3.5 - 5.0 ns 5, 6 tOEQ OE to Output Valid - 3.5 - 3.5 - 5.0 ns 8 tOELZ OE to Output in Low-Z 0 - 0 - 0 - ns 5, 6 tOEHZ OE to Output in High-Z - 3.5 - 3.5 - 5.0 ns 5, 6 Setup Times TAS Address 1.5 - 2.0 - 2.0 - ns 7, 9 tADSS Address Status ( ADSC , ADSP ) 1.5 - 2.0 - 2.0 - ns 7, 9 tADVS Address Advance ( ADV ) 1.5 - 2.0 - 2.0 - ns 7, 9 tWS Write Signals (BW1, BW2 , BW3 , BW4 , BWE , GW ) TDS Data-in 1.5 - 1.5 - 2.0 - ns 7, 9 tCES Chip Enable (CE , CE2, CE2 ) 1.5 - 2.0 - 2.0 - ns 7, 9 Hold Times TAH Address 0.5 0.5 0.5 ns 7, 9 tADSH Address Status ( ADSC , ADSP ) 0.5 0.5 0.5 ns 7, 9 tAAH Address Advance ( ADV ) 0.5 0.5 0.5 ns 7, 9 tWH Write Signal (BW1, BW2 , BW3 ,BW4 , BWE , GW ) 0.5 0.5 0.5 ns 7, 9 TDH Data-in 0.5 0.5 0.5 ns 7, 9 tCEH Chip Enable (CE , CE2, CE2 ) 0.5 0.5 0.5 ns 7, 9

(April, 2007, Version 1.0) 10 AMIC Technology, Corp. Notes: 1. All voltages refer to GND. 2. Overshoot: V IH ≤ +2V for t ≤ tKC/2. Undershoot: V IL ≥ -0.7V for t ≤ tKC/2. Power-up: V IH ≤ +2 and VCC ≤ 1.7V for t ≤ 200ms 3. I CC1 is given with no output current. ICC1 increases with greater output loading and faster cycle times. 4. Test conditions assume the output loading s hown in Figure 1, unless otherwise specified. 5. For output loading, C L = 5pF, as shown in Figure 2. Transition is measured ±150mV from steady state voltage. 6. At any given temperature and voltage condition, t KQHZ is less than tKQLZ and tOEHZ is less than tQELZ. 7. A WRITE cycle is defined by at least one Byte Write enable LOW and ADSP HIGH for the required setup and hold times. A READ cycle is defined by all byte write enables HIGH and ( ADSC or ADV LOW) or ADSP LOW for the required setup and hold times. 8. OE has no effect when a Byte Write enable is sampled LOW. 9. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK when either ADSP or ADSC is LOW and the chip is enabled. All other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each rising edge of CLK when either ADSP or ADSC is LOW to remain enabled. 10. The load used for V OH, VOL testing is shown in Figure 2. AC load current is higher than the given DC values. AC I/O curves are available upon request. 11. "Device Deselected" means device is in POWER-DOWN mode, as defined in the truth table. "Device Selected" means device is active (not in POWER-DOWN mode). 12. MODE pin has an internal pulled-up, and ZZ pin has an internal pulled-down. All of then exhibit an input leakage current of 10 μA. 13. Snooze (ZZ) input is recommended that users plan for f our clock cycles to go into SLEEP mode and four clocks to emerge from SLEEP mode to ensure no data is lost.

(April, 2007, Version 1.0) 11 AMIC Technology, Corp. Timing Waveforms Read Timing Notes: 1. QA(2) refers to output from address A2. Q(A2+1) refers to output from the next internal burst address following A2. CE and CE2 have timing identical to CE . On this diagram, when CE is LOW, CE2 is LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW. 3. Timing is shown assuming that the device wa s not enabled before entering into this sequence. OE does not cause Q to be driven until after the following clock rising edge. CLK ADSP ADSC ADDRESS A1 A2 GW,BWE BW1-BW4 CE (NOTE 2) ADV OE Q(A1) Q(A2) Q(A2+1) Q(A2+2)High-ZDOUT (NOTE 3) tOEHZ tKQX tKQ tKQX BURST READ Deselect cycle ADV suspends burst tADVHtADVS tCEHtCES tWHtWS tAHtAS tADSHtADSS tADSHtADSS tKLtKH tKC (NOTE *1) tOEQ tKQLZ tKQ tOELZ Single READ Don't Care Undefined Q(A2+3) Q(A3) tKQHZ Deselect with CE

(April, 2007, Version 1.0) 12 AMIC Technology, Corp. Timing Waveforms (continued) CLK ADSP ADSC ADDRESS A1 A2 A3 OE D(A2) D(A2+1) D(A2+2) D(A2+3) D(A3) D(A3+1)High-ZDIN tAHtAS tADSHtADSS tADSHtADSS tKLtKH tKC tADSHtADSS ADSC extends burst GW CE (NOTE 2) ADV D(A1) D(A2+1) D(A3+2) DOUT BURST READ Single WRITE Extended BURST WRITE tOEHZ tDHtDS (NOTE 3) (NOTE 4) ADV suspends burst tADVHtADVS tCEHtCES tWHtWS BYTE WRITE signals are ignored for first cycle when ADSP initiates burst tWHtWS BWE,BW1-BW4 (NOTE 5) (NOTE 1) Don't Care Undefined Write Timing Notes: 1. D(A2) refers to output from address A2. D(A2+1) refers to output from the internal burst address immediately following A2. 2. Timing for CE2 and CE2 is identical to that for CE . As shown in the above diagram, when CE is LOW, CE2 is LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW. 3. OE must be HIGH before the input data setup, and hel d HIGH throughout the data hold period. This prevents input/output data contention for the period prior to the time Byte Write enable inputs are sampled. 4. ADV must be HIGH to permit a Write to the loaded address. 5. Byte Write enables are decided by means of a Write truth table.

(April, 2007, Version 1.0) 13 AMIC Technology, Corp. Timing Waveforms (continued) Read/Write Timing Notes: 1. Q(A4) refers to output from address A4. Q(A4+1) refers to output from the next internal burst address following A4. CE2 and CE2 have timing identical to CE . On this diagram, when CE is LOW, CE is LOW and CE2 is HIGH, When CE is HIGH, CE2 is HIGH and CE2 is LOW. 3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP , ADSC , or ADV cycle is performed. 4. Byte Write enables are decided by means of a Write truth table. 5. Back-to-back READs may be controlled by either ADSP or ADSC CLK ADSP ADSC ADDRESS A1 A3 CE (NOTE 2) ADV OE D(A3) D(A5) D(A6)High-ZDIN tCEHtCES tADSHtADSS tKLtKH tKC A2 A4 A5 A6 GW,BWE, BW1-BW4 (NOTE 3) Q(A1) Q(A2) Q(A4) Q(A4+1)DOUT Back-to-Back READs Single WRITE BURST READ Back-to-Back WRIT Es (NOTE 1)tKQ tOELZ tDHtDS tWS tWH tAS tAH Q(A4+2) Q(A4+3) tOEHZ tKQ Don't Care Undefined

(April, 2007, Version 1.0) 14 AMIC Technology, Corp. AC Test Conditions Input Pulse Levels GND to 3V Input Rise and Fall Times 1 ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load See Figures 1 and 2 ZO=50Ω Q RL=50Ω VT=1.5V Figure 1. Output Load Equivalent Figure

Ordering Information

Part No. Access Times (ns) Frequency (MHz) Package A63L83361E-6.5IF 6.5 153 100L Pb-Free LQFP A63L83361E-6.5F 6.5 153 100L Pb-Free LQFP A63L83361E-7.5IF 7.5 133 100L Pb-Free LQFP A63L83361E-7.5F 7.5 133 100L Pb-Free LQFP A63L83361E-8IF 8 117 100L Pb-Free LQFP A63L83361E-8F 8 117 100L Pb-Free LQFP Note: -I is for industrial operating temperature range -25ºC to +85ºC.

(April, 2007, Version 1.0) 15 AMIC Technology, Corp.

Package Information

LQFP 100L Outline Dimensions unit: inches/mm Symbol Dimensions in inches Dimensions in mm c 0.005 - 0.008 0.12 - 0.20 e 0.026 BSC 0.65 BSC L1 0.039 REF 1.00 REF Notes: 1. Dimensions D and E do not include mold protrusion. 2. Dimensions b does not include dambar protrusion. Total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. 5180 100 HD D E HE 13 0 b D y A1A2 ce θ L