A63L7336E-2.6F

A63L7336 AMICC | Alldatasheet

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128K X 36 Bit Synchronous High Speed SRAM with Preliminary Burst Counter and Pipelined Data Output PRELIMINARY (July, 2005, Version 0.0) AMIC Technology, Corp. Document Title 128K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output

Revision History

Rev. No. History Issue Date Remark

0.0 Initial issue July 11, 2005 Preliminary

128K X 36 Bit Synchronous High Speed SRAM with Preliminary Burst Counter and Pipelined Data Output PRELIMINARY (July, 2005, Version 0.0) 1 AMIC Technology, Corp.

Features

(250/227/200/166/150/133 MHZ) „ Single +3.3V+10% or +3.3V-5% power supply „ Synchronous burst function „ Individual Byte Write control and Global Write „ Registered output for pipelined applications „ Three separate chip enables allow wide range of options for CE control, address pipelining „ Selectable BURST mode „ SLEEP mode (ZZ pin) provided „ Available in 100-pin LQFP package General Description The A63L7336 is a high-speed SRAM containing 4.5M bits of bit synchronous memory, organized as 128K words by 36 bits. The A63L7336 combines advanced synchronous peripheral circuitry, 2-bit burst control, input registers, output registers and a 128KX36 SRAM core to provide a wide range of data RAM applications. The positive edge triggered single clock input (CLK) controls all synchronous inputs passing through the registers. Synchronous inputs include all addresses (A0 - A16), all data inputs (I/O 1 - I/O36), active LOW chip enable ( CE ), two additional chip enables (CE2, CE2 ), burst control inputs ( ADSC , ADSP , ADV ), byte write enables ( BWE , BW1 , BW2 , BW3 , BW4 ) and Global Write ( GW ). Asynchronous inputs include output enable ( OE ), clock (CLK), BURST mode (MODE) and SLEEP mode (ZZ). Burst operations can be initiated with either the address status processor ( ADSP ) or address status controller ( ADSC ) input pin. Subsequent burst sequence burst addresses can be internally generated by the A63L7336 and controlled by the burst advance ( ADV ) pin. Write cycles are internally self-timed and synchronous with the rising edge of the clock (CLK). This feature simplifies the write interface. Individual Byte enables allow individual bytes to be written. BW1 controls I/O1 - I/O 9, BW2 controls I/O 10 - I/O 18, BW3 controls I/O19 - I/O 27, and BW4 controls I/O 28 - I/O 36, all on the condition that BWE is LOW. GW LOW causes all bytes to be written.

PRELIMINARY (July, 2005, Version 0.0) 2 AMIC Technology, Corp. Pin Configuration I/O20 I/O21 VCCQ GNDQ I/O22 I/O23 I/O24 I/O25 GNDQ I/O26 I/O27 VCCQ VCC NC I/O34 GND I/O28 I/O29 VCCQ GNDQ I/O30 I/O31 I/O32 I/O33 GNDQ VCCQ I/O35 NC I/O I/O16 VCCQ GNDQ I/O15 I/O14 I/O13 I/O12 GNDQ VCCQ I/O11 I/O10 GND NC VCC ZZ I/O8 I/O7 VCCQ GNDQ I/O I/O5 I/O4 I/O3 GNDQ VCCQ I/O I/O1 A16 A15 A14 A13 A12 A11 A10 VCC GND NC MODE 100 CE2 CLK GND VCC A63L7336E NC ADV ADSP ADSC OE BWE GW CE2 BW1 BW2 BW3 BW4 CE I/O19 I/O36 NC NC NC I/O9

PRELIMINARY (July, 2005, Version 0.0) 3 AMIC Technology, Corp. Block Diagram MODE LOGIC CLK LOGIC ADDRESS REGISTERS BURST LOGIC ADDRESS COUNTER CLR BYTE WRITE ENABLE LOGIC BYTE1 WRITE DRIVER BYTE2 WRITE DRIVER BYTE3 WRITE DRIVER BYTE4 WRITE DRIVER 128KX9X4 MEMORY ARRAY OUTPUT REGISTERS DATA-IN REGISTERS CHIP ENABLE LOGIC PIPELINED ENABLE LOGIC OUTPUT ENABLE LOGIC ZZ MODE ADV CLK ADSC ADSP A0-A16 GW BWE BW1 BW2 BW3 BW4 CE CE2 CE2 OE I/O1 - I/O36

PRELIMINARY (July, 2005, Version 0.0) 4 AMIC Technology, Corp. Pin Description Pin No. Symbol Description 32 – 37, 44 - 50, 81, 82, 99, 100 A0 - A17 Address Inputs

89 CLK Clock

87, 93 - 96 BWE , BW1 - BW4 Byte Write Enables

88 GW Global Write

86 OE Output Enable

92, 97, 98 CE2 ,CE2, CE Chip Enables

83 ADV Burst Address Advance

84 ADSP Processor Address Status

85 ADSC Controller Address Status

31 MODE Burst Mode: HIGH or NC (Interleaved burst)

LOW (Linear burst)

64 ZZ Asynchronous Power-Down (Snooze): HIGH (Sleep)

LOW or NC (Wake up) 19, 22 - 25, 28, 29, 30,51,52, 53, 56 - 59, 62, 63, 68, 69, 72 - 75, 78, 79,80 I/O1- I/O36 Data Inputs/Outputs 15, 41, 65, 91 VCC Power Supply 17, 40, 67, 90 GND Ground 4, 11, 20, 27, 54, 61, 70, 77 VCCQ Isolated Output Buffer Supply 5, 10, 21, 26, 55, 60, 71, 76 GNDQ Isolated Output Buffer Ground

PRELIMINARY (July, 2005, Version 0.0) 5 AMIC Technology, Corp. Synchronous Truth Table (See Notes 1 Through 5) Operation Address Used CE CE2 CE2 ADSP ADSC ADV WRITE OE CLK I/O Operation Deselected Cycle, Power-down NONE H X X X L X X X L-H High-Z Deselected Cycle, Power-down NONE L X L L X X X X L-H High-Z Deselected Cycle, Power-down NONE L H X L X X X X L-H High-Z Deselected Cycle, Power-down NONE L X L H L X X X L-H High-Z Deselected Cycle, Power-down NONE L H X H L X X X L-H High-Z READ Cycle, Begin Burst External L L H L X X X L L-H Dout READ Cycle, Begin Burst External L L H L X X X H L-H High-Z WRITE Cycle, Begin Burst External L L H H L X L X L-H Din READ Cycle, Begin Burst External L L H H L X H L L-H Dout READ Cycle, Begin Burst External L L H H L X H H L-H High-Z READ Cycle, Continue Burst Next X X X H H L H L L-H Dout READ Cycle, Continue Burst Next X X X H H L H H L-H High-Z READ Cycle, Continue Burst Next H X X X H L H L L-H Dout READ Cycle, Continue Burst Next H X X X H L H H L-H High-Z WRITE Cycle, Continue Burst Next X X X H H L L X L-H Din WRITE Cycle, Continue Burst Next H X X X H L L X L-H Din READ Cycle, Suspend Burst Current X X X H H H H L L-H Dout READ Cycle, Suspend Burst Current X X X H H H H H L-H High-Z READ Cycle, Suspend Burst Current H X X X H H H L L-H Dout READ Cycle, Suspend Burst Current H X X X H H H H L-H High-Z WRITE Cycle, Suspend Burst Current X X X H H H L X L-H Din WRITE Cycle, Suspend Burst Current H X X X H H L X L-H Din

PRELIMINARY (July, 2005, Version 0.0) 6 AMIC Technology, Corp. Notes: 1. X = "Disregard", H = Logic High, L = Logic Low. 2. WRITE = L means: 1) Any BWx (BW1, BW2 ,BW3 , or BW4 ) and BWE are low or 2) GW is low. 3. All inputs except OE must be synchronized with setup and hold times around the rising edge (L-H) of CLK. 4. For write cycles that follow read cycles, OE must be HIGH before the input data request setup time and held HIGH throughout the input data hold time. 5. ADSP LOW always initiates an internal Read at the L-H edge of CLK. A Write is performed by setting one or more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. Refer to the Write timing diagram for clarification. Write Truth Table Operation GW BWE BW1 BW2 BW3 BW4 READ H H X X X X READ H L H H H H WRITE Byte 1 H L L H H H WRITE all bytes H L L L L L WRITE all bytes L X X X X X

PRELIMINARY (July, 2005, Version 0.0) 7 AMIC Technology, Corp. Linear Burst Address Table (MODE = LOW) First Address (External) Second Address (Internal) Third Address (Internal) Fourth Address (Internal) Interleaved Burst Address Table (MODE = HIGH or NC) First Address (External) Second Address (Internal) Third Address (Internal) Fourth Address (Internal) Absolute Maximum Ratings* Voltage Relative to GND for any Pin Except VCC (Vin, Power Dissipation (P *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. Recommended DC Operating Conditions (0°C ≤ TA ≤ 70°C, VCC, VCCQ = 3.3V+10% or 3.3V-5%, unless otherwise noted) Symbol Parameter Min. Typ. Max. Unit Note VCC Supply Voltage (Operating Voltage Range) 3.1 3.3 3.6 V VCCQ Isolated Input Buffer Supply 3.1 3.3 VCC V GND Supply Voltage to GND 0.0 - 0.0 V VIH Input High Voltage 2.0 - VCC+0.3 V 1, 2 VIHQ Input High Voltage (I/O Pins) 2.0 - VCC+0.3 V VIL Input Low Voltage -0.3 - 0.8 V 1, 2

PRELIMINARY (July, 2005, Version 0.0) 8 AMIC Technology, Corp. (0°C ≤ TA ≤ 70°C, VCC, VCCQ = 3.3V+10% or 3.3V-5%, unless otherwise noted) Symbol Parameter Min. Max. Unit Test Conditions Note ⏐ILI⏐ Input Leakage Current - ±2.0 µA All inputs V IN = GND to VCC ⏐ILO⏐ Output Leakage Current - ±2.0 µA OE = VIH, Vout = GND to VCC ICC1 Supply Current 400 mA Device selected; VCC = max. Iout = 0mA, all inputs = VIH or VIL Cycle time = tKC min. 3, 11 ISB1 Standby Current mA Device deselected; VCC = max. All inputs are fixed. All inputs ≥ VCC - 0.2V or ≤ GND + 0.2V Cycle time = tKC min. ISB2 - 15 mA ZZ ≥ VCC - 0.2V VOL Output Low Voltage - 0.4 V I OL = 8 mA VOH Output High Voltage 2.4 - V I OH = -4 mA Capacitance Symbol Parameter Typ. Max. Unit Conditions CIN Input Capacitance 3 4 pF TA = 25 C; f = 1MHz CI/O Input/Output Capacitance 4 5 pF VCC = 3.3V * These parameters are sampled and not 100% tested.

PRELIMINARY (July, 2005, Version 0.0) 9 AMIC Technology, Corp. AC Characteristics (0°C ≤ TA ≤ 70°C, VCC = 3.3V+10% or 3.3V-5%) Min Max Min Max Min Max Min Max Min Max Min Max tOELZ OE to Output in Low-Z 0 - 0 - 0 - 0 - 0 - 0 - ns 5, 6 Setup Times tADSS Address Status ( ADSC , ADSP ) tADVS Address Advance ( ADV ) tWS Write Signals (BW1, BW2 , BW3 , BW4 , BWE , GW ) tCES Chip Enable ( CE , CE2, CE2 )

PRELIMINARY (July, 2005, Version 0.0) 10 AMIC Technology, Corp. AC Characteristics (continued) Min Max Min Max Min Max Min Max Min. Max Min Max Hold Times tADVH Address Status ( ADSC , ADSP ) tAAH Address Advance ( ADV ) tWH Write Signal (BW1, BW2 , BW3 , BW4 , BWE , GW ) tCEH Chip Enable ( CE , CE2, CE2 ) Notes: 1. All voltages refer to GND. 2. Overshoot: V IH ≤ +4.6V for t ≤ tKC/2. Undershoot: V IH ≥ -0.7V for t ≤ tKC/2. Power-up: V IH ≤ +3.6 and VCC ≤ 3.1V for t ≤ 200ms 3. I CC is given with no output current. ICC increases with greater output loading and faster cycle times. 4. Test conditions assume the output loading shown in Figure 1, unless otherwise specified. 5. For output loading, C L = 5pF, as shown in Figure 2. Transition is measured ±150mV from steady state voltage. 6. At any given temperature and voltage condition, t KQHZ is less than tKQLZ and tOEHZ is less than tQELZ. 7. A WRITE cycle is defined by at least one Byte Write enable LOW and ADSP HIGH for the required setup and hold times. A READ cycle is defined by all byte write enables HIGH and ( ADSC or ADV LOW) or ADSP LOW for the required setup and hold times. 8. OE has no effect when a Byte Write enable is sampled LOW. 9. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK when either ADSP or ADSC is LOW and the chip is enabled. All other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each rising edge of CLK when either ADSP or ADSC is LOW to remain enabled. 10. The load used for V OH, VOL testing is shown in Figure 2. AC load current is higher than the given DC values. AC I/O curves are available upon request. 11. "Device Deselected" means device is in POWER-DOWN mode, as defined in the truth table. "Device Selected" means device is active (not in POWER-DOWN mode). 12. MODE pin has an internal pulled-up, and ZZ pin has an in ternal pulled-down. All of then exhibit an input leakage current of 10 µA. 13. Snooze (ZZ) input is re commended that users plan for four clock cycl es to go into SLEEP mode and four clocks to emerge from SLEEP mode to ensure no data is lost.

PRELIMINARY (July, 2005, Version 0.0) 11 AMIC Technology, Corp. Timing Waveforms CLK ADSP ADSC ADDRESS A1 A2 A3 GW,BWE BW1-BW4 CE (NOTE *2) ADV OE Q(A1) Q(A2) Q(A2+1) Q(A2+2) Q(A2+3) Q(A2) Q(A2+1)High-ZDOUT tKQLZ (NOTE *3) tKQ tOEHZ tOELZ tOEQ tKQX tKQ Burst wraps around to its initial state tKQHZ Single READ BURST READ Delselected cycle Burst continued with new base address ADV suspends burst tADVHtADVS tCEHtCES tWHtWS tAHtAS tADSHtADSS tADSHtADSS tKLtKH tKC (NOTE *4) Q(A3) (NOTE *1) Read Timing Notes: *1. Q(A2) refers to output from address A2. Q(A2+1) refers to output from the internal burst address immediately following A2. *2. Timing for CE2 and CE2 is identical to that for CE . As shown in this diagram, when CE is LOW, CE2 is LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW. *3. Timing shown assumes that the device was not enabled before entering this sequence. OE does not cause Q to be driven until after the rising edge of the following clock.

PRELIMINARY (July, 2005, Version 0.0) 12 AMIC Technology, Corp. Timing Waveforms (continued) CLK ADSP ADSC ADDRESS A1 A2 A3 OE D(A2) D(A2+1) D(A2+2) D(A2+3) D(A3) D(A3+1)High-ZDIN tAHtAS tADSHtADSS tADSHtADSS tKLtKH tKC tADSHtADSS ADSC extends burst GW CE (NOTE *2) ADV D(A1) D(A2+1) D(A3+2) DOUT BURST READ Single WRITE Extended BURST WRITE tOEHZ tDHtDS (NOTE *3) (NOTE *4) ADV suspends burst tADVHtADVS tCEHtCES tWHtWS BYTE WRITE signals are ignored for first cycle when ADSP initiates burst tWHtWS BWE,BW1-BW4 (NOTE *5) (NOTE *1) Write Timing Notes: *1. D(A2) refers to output from address A2. D(A2+1) refers to output from the internal burst address immediately following A2. *2. Timing for CE2 and CE2 is identical to that for CE . As shown in the above diagram, when CE is LOW, CE2 is LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW. *3. OE must be HIGH before the input data setup, and held HIGH throughout the data hold period. This prevents input/output data contention for the period prior to the time Byte Write enable inputs are sampled. *4. ADV must be HIGH to permit a Write to the loaded address. *5. Byte Write enables are decided by means of a Write truth table.

PRELIMINARY (July, 2005, Version 0.0) 13 AMIC Technology, Corp. Timing Waveforms (continued) CLK ADSP ADSC ADDRESS A1 A3 CE (NOTE *2) ADV OE D(A3) D(A5) D(A6)High-ZDIN tCEHtCES tADSHtADSS tKLtKH tKC A2 A4 A5 A6 GW,BWE, BW1-BW4 (NOTE *3) High-Z Q(A1) Q(A2) Q(A3) Q(A4) Q(A4+1) Q(A4+2) Q(A4+3)DOUT Back-to-Back READs Single WRITE Pass-through READ (NOTE *4) BURST READ Back-to-Back WRITEs (NOTE *1) tKQ tOELZ tDHtDS tOEHZ tKQ tKQLZ tWS tWH tAS tAH Read/Write Timing Notes: *1. Q(A4) refers to output from address A4. Q(A4+1) refe rs to output from the internal burst address immediately following A4. *2. Timing for CE2 and CE2 is identical to that for CE . As shown in this diagram, when CE is LOW, CE2 is LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW. *3. Byte Write enables are decided by means of a Write truth table. *4. Pass-through occurs when data is first written, then Read in sequence.

PRELIMINARY (July, 2005, Version 0.0) 15 AMIC Technology, Corp.

Ordering Information

Part No. Access Times (ns) Frequency (MHz) Package A63L7336E-2.6 2.6 250 100L LQFP A63L7336E-2.6F 2.6 250 100L Pb-Free LQFP A63L7336E-2.8 2.8 225 100L LQFP A63L7336E-2.8F 2.8 225 100L Pb-Free LQFP A63L7336E-3.2 3.2 200 100L LQFP A63L7336E-3.2F 3.2 200 100L Pb-Free LQFP A63L7336E-3.5 3.5 166 100L LQFP A63L7336E-3.5F 3.5 166 100L Pb-Free LQFP A63L7336E-3.8 3.8 150 100L LQFP A63L7336E-3.8F 3.8 150 100L Pb-Free LQFP A63L7336E-4.2 4.2 133 100L LQFP A63L7336E-4.2F 4.2 133 100L Pb-Free LQFP

PRELIMINARY (July, 2005, Version 0.0) 16 AMIC Technology, Corp.

Package Information

LQFP 100L Outline Dimensions unit: inches/mm Symbol Dimensions in inches Dimensions in mm c 0.005 - 0.008 0.12 - 0.20 e 0.026 BSC 0.65 BSC L1 0.039 REF 1.00 REF Notes: 1. Dimensions D and E do not include mold protrusion. 2. Dimensions b does not include dambar protrusion. Total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. 5180 100 HD D E HE 13 0 b D y A1A2 ce θ L