A62S7308BX-55S

A62S7308B AMICC | Alldatasheet

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Preliminary 128K X 8 BIT LOW VOLTAGE CMOS SRAM PRELIMINARY (March, 2001, Version 0.2) AMIC Technology, Inc. Document Title 128K X 8 BIT LOW VOLTAGE CMOS SRAM

Revision History

Rev. No. History Issue Date Remark

0.0 Initial issue September 5, 2000 Preliminary

0.1 Change max. power supply voltage from 3.3V to 3.6V October 12, 2000 Change min. V IH from 2.2V to 2.4V Add feature “ Interfaces directly with 3.3V typ. logic chip” Remove A62S7308B - 10S/SI part

0.2 Add A62S7308B - 55S/SI part March 9, 2001

Change Input Pulse Levels from 0.4V~2.4V to 0V~3.0V in AC Test Conditions table

Preliminary 128K X 8 BIT LOW VOLTAGE CMOS SRAM PRELIMINARY (March, 2001, Version 0.2) 1 AMIC Technology, Inc. NC A14 A12 I/O 0 I/O 1 I/O 2 I/O 3GND I/O 4 I/O 5 I/O 6 I/O 7 A10 A13 CE2 A15 VCC A11 A62S7308BM 16 17 OE CE1 WE A10 GND OE CE1 A16 A62S7308BV (A62S7308BX) A11 A9 2 A13 VCC NC A14 A12 I/O I/O I/O I/O I/O A15 WE CE2 I/O I/O I/O ~~ ~~ A16 1 2 3 4 5 6 A A0 A1 CE2 A3 A6 A8 B I/O 4 A2 WE A4 A7 I/O 0 C I/O 5 NC A5 I/O 1 D VSS VCC E VCC VSS F I/O 6 NC NC I/O 2 G I/O 7 OE CE1 A16 A15 I/O 3 H A9 A10 A11 A12 A13 A14

Features

n Power sup ply range: 2.7V to 3.6V n Access times: 55ns (max.): for VCC = 3.0V to 3.6V 70ns (max.): for VCC = 2.7V to 3.6V n Current: A62S7308B - S series: Operating: 30mA (max.) Standby: 5 µA (max.) A62S7308B - SI series: Operating: 30mA (max.) Standb y: 10 µA (max.) n Extended operating temperature range: - 25 °C to 85 °C for - SI series n Full static operation, no clock or refreshing required n All inputs and outputs are directly TTL compatible n Common I/O using three - state output n Output enable and two chip enable inputs for easy application n Data retention voltage: 2V (min.) n Available in 32 - pin SOP, TSOP, sTSOP (8X 13.4mm) forward type and 36 - ball Mini BGA (6X8) packages n Interfaces directly with 3.3V typ. logic chip General Description The A62S 7308B is a low operating current 1048,576 - bit static random access memory organized as 131,072 words by 8 bits and operates on a low power supply voltage from 2.7V to 3.6V. Inputs and three - state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Two chip enable inputs are provided for power down and a device enable and an output enable input are included for easy interfacing. Data retention is guaranteed at a power supply voltage as low as 2V. Pin Configurations nn SOP nn TSOP/(sTSOP) nn Mini BGA (6X8) Top View (forward type)

PRELIMINARY (March, 2001, Version 0.2) 2 AMIC Technology, Inc. Block Diagram ROW DECODER

512 X 2048

Pin No. Symbol Description

1 NC No Connection

2 - 12, 23, 25 - 28, 31 A0 - A16 Address Inputs 13 - 15 , 17 - 21 I/O 0 - I/O 7 Data Inputs/Outputs

16 GND Ground

22 CE1 Chip Enable 1

24 OE Output Enable

29 WE Write Enable

30 CE2 Chip Enable 2

32 VCC Power Supply

Pin Description - TSOP/sTSOP Pin No. Symbol Description 1 - 4, 7, 10 - 20, 31 A0 - A16 Address Inputs

5 WE Write Enable

6 CE2 Chip Enable 2

8 VCC Power Supply

9 NC No Connection

21 - 23, 25 - 29 I/O 0 - I/O 7 Data Inputs/Outputs

24 GND Ground

30 CE1 Chip Enable 1

32 OE Output Enable

PRELIMINARY (March, 2001, Version 0.2) 3 AMIC Technology, Inc. Recommended DC Operating Conditions (T A = 0 °C to + 70 °C or - 25 °C to 85 °C) Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage 2.7 3.0 3.6 V GND Ground 0 0 0 V V IH Input Hig h Voltage 2.4 - VCC + 0.3 V V IL Input Low Voltage - 0.3 - +0.6 V C L Output Load - - 30 pF TTL Output Load - - 1 - Absolute Maximum Ratings* *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indi cated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. Symbol Parameter A62S7308B-55S/70S A62S7308B-55SI/70SI Unit Conditions Min. Max. Min. Max. ILI Input Leakage Current - 1 - 1 µA V IN = GND to VCC ILO Output Leakage Current - 1 - 1 µA CE1 = V IH or CE2 = V IL or OE = V IH or WE = V IL V I/O = GND to VCC ICC Active Power Supply Current - 3 - 3 mA CE1 = V IL, CE2 = V IH I I/O = 0mA ICC1 Dynamic Operating Current - 30 - 30 mA Min. Cycle, Duty = 100% CE1 = V IL, CE2 = V IH I I/O = 0mA ICC2 Dynamic Operating Current - 3 - 3 mA CE1 = V IL, CE2 = V IH V IH = VCC , V IL = 0V F = 1MHz, II/O = 0mA

PRELIMINARY (March, 2001, Version 0.2) 4 AMIC Technology, Inc. Symbol Parameter A62S7308B-55S/70S A62S7308B-55SI/70SI Unit Conditions Min. Max. Min. Max. ISB - 0.3 - 0.3 mA CE1 = V IH or CE2 = V IL ISB1 Standby Power Supply Current - 5 - 10 µA CE2 ≤ 0.2V, or CE1 ≥ VCC - 0.2V CE2 ≥ VCC - 0.2V V OL Output Low Voltage - 0.4 - 0.4 V I OL = 2.1mA V OH Output High Voltage 2.4 - 2.4 - V I OH = - 1.0mA Truth Table Mode CE1 CE2 OE WE I/O Operation Supply Current Standby H X X X High Z ISB, I SB1 X L X X High Z ISB, I SB1 Output Disable L H H H High Z ICC, ICC1, ICC2 Read L H L H D OUT ICC, ICC1, ICC2 Write L H X L D IN ICC, ICC1, ICC2 N ote: X = H or L Capacitance (T A = 25 °C, f = 1.0MHz) Symbol Parameter Min. Max. Unit Conditions C IN* Input Capacitance 6 pF V IN = 0V C I/O* Input/Output Capacitance 8 pF V I/O = 0V * These parameters are sampled and not 100% tested.

PRELIMINARY (March, 2001, Version 0.2) 5 AMIC Technology, Inc. AC Characteristics (T A = 0 °C to + 70 °C or - 25 °C to 85 °C) Symbol Parameter A62S7308B-55S/SI (VCC = 3.0V to 3.6V) A62S7308B-70S/SI (VCC = 2.7V to 3.6V) Unit Min. Max. Min. Max. Read Cycle tRC Read Cycle Time 55 - 70 - ns tAA Address Access Time - 55 - 70 ns tACE1 Chip Enable Access Time CE1 - 55 - 70 ns tACE2 CE2 - 55 - 70 ns tOE Output Enable to Output Valid - 30 - 35 ns tCLZ1 Chip Enable to Output in Low Z CE1 10 - 10 - ns tCLZ2 CE2 10 - 10 - ns tOLZ Output Enable to Output in Low Z 10 - 5 - ns tCHZ1 Chip Disable to Output in High Z CE1 0 20 0 25 ns tCHZ2 CE2 0 20 0 25 ns tOHZ Output Disable to Output in High Z 0 20 0 25 ns tOH Output Hold from Address Change 5 - 10 - ns Write Cycle tWC Writ e Cycle Time 55 - 70 - ns tCW Chip Enable to End of Write 50 - 60 - ns tAS Address Setup Time 0 - 0 - ns tAW Address Valid to End of Write 50 - 60 - ns tWP Write Pulse Width 40 - 50 - ns tWR Write Recovery Time 0 - 0 - ns tWHZ Write to Output in Hig h Z 0 25 0 30 ns tDW Data to Write Time Overlap 25 - 30 - ns tDH Data Hold from Write Time 0 - 0 - ns tOW Output Active from End of Write 5 - 5 - ns Notes: tCHZ1, t CHZ2, t OHZ and t WHZ are defined as the time at which the outputs achieve the open circui t condition and are not referred to output voltage levels.

PRELIMINARY (March, 2001, Version 0.2) 6 AMIC Technology, Inc. Timing Waveforms Read Cycle 1(1) tRC Address CE2 D OUT tAA tOE tOLZ5 tACE1 tCLZ15 tACE2 tCLZ25 tCHZ25 tOHZ5 tCHZ15 tOH OE CE1 Read Cycle 2 (1, 2, 4) tRC tOH tAA tOH Address D OUT

PRELIMINARY (March, 2001, Version 0.2) 7 AMIC Technology, Inc. Timing Waveforms (continued) Read Cycle 3 (1, 3, 4, 6) tCLZ15 tACE1 tCHZ15 CE1 D OUT Read Cycle 4 (1, 4, 7, 8) tCLZ25 tACE2 tCHZ25 CE2 D OUT Notes: 1. WE is high for Read Cycle. 2. Device is continuously enabled CE1 = V IL and CE2 = V IH. 3. Address valid prior to or coincident w ith CE1 transition low. 4. OE = V IL. 5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested. 6. CE2 is high. 7. CE1 is low. 8. Address valid pri or to or coincident with CE2 transition high.

PRELIMINARY (March, 2001, Version 0.2) 8 AMIC Technology, Inc. Timing Waveforms (continued) Write Cycle 1(6) (Write Enable Controlled) tWC Address CE1 CE2 D IN tOW tDHtDW tWHZ tWP2tAS1 (4) tCW5 tAW tWR3 WE D OUT (4)

PRELIMINARY (March, 2001, Version 0.2) 9 AMIC Technology, Inc. Timing Waveforms (continued) Write Cycle 2(6) (Chip Enable Controlled) tWC Address CE1 CE2 D IN tDHtDW (4) (4) tCW5 tAW tWR3 WE D OUT tWHZ7 tWP2 tCW5 tAS1 No tes: 1. t AS is measured from the address valid to the beginning of Write. 2. A Write occurs during the overlap (t WP) of a low CE1 , a high CE2 and a low WE . 3. t WR is measured from the earliest of CE1 or WE going high or CE2 going low to the end of the Write cycle. 4. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transition or after the WE transition, outputs remain in a high impedance state. 5. t CW is measured from the later of CE1 going low or CE2 going high to the end of Write. 6. OE is continuously low. ( OE = V IL) 7. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.

PRELIMINARY (March, 2001, Version 0.2) 10 AMIC Technology, Inc.

• Including scope and jig. * Including scope and jig.

Figure 1. Output Load Figure 2. Output Load for tCLZ1,

PRELIMINARY (March, 2001, Version 0.2) 11 AMIC Technology, Inc. Low VCC Data Retention Waveform (1) ( CE1 Controlled) VCC CE1 tCDR V IH 2.7V tR V IH 2.7V DATA RETENTION MODE V DR ≥ 2V CE1 ≥ V DR - 0.2V Low VCC Data Retention Waveform (2) (CE2 Controlled) VCC CE2 tCDR V IL 2.7V tR V IL 2.7V DATA RETENTION MODE V DR ≥ 2V CE2 ≤ 0.2V

PRELIMINARY (March, 2001, Version 0.2) 12 AMIC Technology, Inc.

Ordering Information

Part No. Access Time (ns) Operating Current Max. (mA) Standby Current Max. (µµA) Package A62S7308BM - 55S 5 32L SOP A62S7308BM - 55SI 10 32L SOP A62S7308BV - 55S 5 32L TSOP A62S7308BV - 55SI 10 32L TSOP A62S7308BX - 55S 5 32L sTSOP A62S7308BX - 55SI 10 32L sTSOP A62S7308BG - 55S 5 36B Mini BGA A62S7308BG - 55SI 55 30 10 36B Mini BGA A62S7308BM - 70S 5 32L SOP A62S7308BM - 70SI 10 32L SOP A62S7308BV - 70S 5 32L TSOP A62S7308BV - 70SI 10 32L TSOP A62S7308BX - 70S 5 32L sTSOP A62S7308BX - 70SI 10 3 2L sTSOP A62S7308BG - 70S 5 36B Mini BGA A62S7308BG - 70SI 70 30 10 36B Mini BGA

PRELIMINARY (March, 2001, Version 0.2) 13 AMIC Technology, Inc.

Package Information

SOP (W.B.) 32L Outline Dimensions unit: inches/mm E H E L L E c See Detail F Detail F 1732 A 1 A 2 A S D Seating Plane D y e b θ Dimensions in inches Dimensions in mm Symbol Min Nom Max Min Nom Max D - 0.805 0.817 - 20.45 20.75 Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension S includes end flash.

PRELIMINARY (March, 2001, Version 0.2) 14 AMIC Technology, Inc. TSOP 32L TYPE I (8 X 20mm) Outline Dimensions unit: inches/mm e L E L A A 2 c D y Detail "A" S A 1 b H D D E θ Detail "A" Dimensions in inches Dimensions in mm Symbol Min Nom Max Min Nom Max A 1 0.002 - 0.006 0.05 - 0.15 c 0.004 - 0.008 0.11 - 0.20 E - 0.315 0.319 - 8.00 8.10 e 0.020 BSC 0.50 BSC Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3 . Dimension S includes end flash.

PRELIMINARY (March, 2001, Version 0.2) 15 AMIC Technology, Inc. sTSOP 32L TYPE I (8 X 13.4mm) Outline Dimensions unit: inches/mm e Detail "A" D 0.076MM Detail "A" S b D 1 E D L E L A A 2 c θ A 1 SEATING PLANE Dimensions in inches Dimensions in mm Symbol Min Nom Max Min Nom Max e 0.020 TYP 0.50 TYP S 0.0109 TYP 0.278 TYP θ 0 ° 3 ° 5 ° 0 ° 3 ° 5 ° Notes: 1. The maximum value of dimension D 1 includes end flash. 2. Dimension E does not include resin fins. 3. Dimensio n S includes end flash.

PRELIMINARY (March, 2001, Version 0.2) 16 AMIC Technology, Inc. Mini BGA 6X8 (36 BALLS) Outline Dimensions unit : millimeter(mm) Symbol Min Typ Max A - 0.75 - B 5.90 6.00 6.10 B1 - 3.75 - C 7.90 8.00 8.10 C1 - 5.25 - D 0.30 0.35 0.40 E 1.00 1.10 1.20 E1 - 0.36 - E2 - 0.22 - 123456 A B C D E F G H Bottom View Pin A1 Index Diameter D Solder Ball A A Top View Pin A1 Index B C 0.10 E D