A62S6316 AMICC | Alldatasheet

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Preliminary 64K X 16 BIT LOW VOLTAGE CMOS SRAM PRELIMINARY (August, 2002, Version 0.5) AMIC Technology, Inc. Document Title 64K X 16 BIT LOW VOLTAGE CMOS SRAM

Revision History

Rev. No. History Issue Date Remark

0.0 Initial issue October 8, 1998 Preliminary

0.1 Change access times from 70/100 ns to 55/70 ns(max.) February 12, 1999 Change dynamic operating current from 80/70mA to 40mA Modify TSOP 44L (Type II) package outline drawing

0.2 Modify truth table June 9, 1999

0.3 Change dynamic operating current from 40mA to 50mA(max.) June 21, 1999

0.4 Modify TSOP 44L (Type II) package outline drawing and November 9, 1999

0.5 Add mini BGA package outline dimensions symbol E 2 min. August 12, 2002 and max.

Preliminary 64K X 16 BIT LOW VOLTAGE CMOS SRAM PRELIMINARY (August, 2002, Version 0.5) 1 AMIC Technology, Inc.

Features

n Operating voltage: 2.7V to 3.3V n Access times: 55/70 ns (max.) n Current: A62S6316-S series: Operating: 50mA (max.) Standby: 15µA (max.) A62S6316-SI series: Operating: 50mA (max.) Standby: 30µA (max.) n Extended operating temperature range : -25°C to 85°C for -SI series n Full static operation, no clock or refreshing required n All inputs and outputs are directly TTL-compatible n Common I/O using three-state output n Data retention voltage: 2V (min.) n Available in 44 -pin TSOP and 48 -ball Mini BGA (6X8) packages. General Description The A62S6316 is a low operating current 1,048,576 -bit static random access memory organized as 65,536 words by 16 bits and operates on low power supply voltage from 2.7V to 3.3V. It is built using AMIC’s high performance CMOS process. Inputs and three -state outputs are TTL compatible and allow for direct interfacing with common system bus structures. The chip enable input is provided for POWER -DOWN, device enable . Two byte enable inputs and an output enable input are included for easy interfacing. Data retention is guaranteed at a power supply voltage as low as 2V. Pin Configuration n TSOP (Type II) 1A4 CE I/O0 I/O1 I/O2 I/O3 VCC GND I/O4 I/O5 I/O6 I/O7 OE HB LB I/O15 I/O14 I/O13 I/O12 VCC GND I/O11 I/O10 I/O9 I/O8 A62S6316V WE A15 A14 A13 A12 NC NC A10 A11 NC n Mini BGA (6X8) Top View 1 2 3 4 5 6 A LB OE A0 A1 A2 NC B I/O8 HB A3 A4 CS I/O0 C I/O9 I/O10 A5 A6 I/O1 I/O2 D VSS I/O11 NC A7 I/O3 VCC E VCC I/O12 NC NC I/O4 VSS F I/O14 I/O13 A14 A15 I/O5 I/O6 G I/O15 NC A12 A13 WE I/O7 H NC A8 A9 A10 A11 NC A62S6316G

PRELIMINARY (August, 2002, Version 0.5) 2 AMIC Technology, Inc. Block Diagram DECODER

512 X 2048

PRELIMINARY (August, 2002, Version 0.5) 3 AMIC Technology, Inc. Pin Description - TSOP Pin No. Symbol Description 1 - 5, 18 - 21, 24 - 27,42 - 44 A0 - A15 Address Inputs

6 CE Chip Enable Input

7 - 10, 13 - 16, 29 - 32, 35 - 38 I/O0 - I/O15 Data Input/Outputs

17 WE Write Enable Input

39 LB Byte Enable Input (I/O0 to I/O7)

40 HB Byte Enable Input (I/O8 to I/O15)

41 OE Output Enable Input

11, 33 VCC Power 12, 34 GND Ground 22 , 23, 28 NC No Connection Recommended DC Operating Conditions (TA = 0°C to + 70°C or -25°C to 85°C) Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage 2.7 3.0 3.3 V GND Ground 0 0 0 V VIH Input High Voltage 2.2 - VCC + 0.3 V VIL Input Low Voltage -0.3 - +0.6 V CL Output Load - - 30 pF TTL Output Load - - 1 -

PRELIMINARY (August, 2002, Version 0.5) 4 AMIC Technology, Inc. Absolute Maximum Ratings* *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functio nal operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. Symbol Parameter A62S6316-55S/70S A62S6316-55SI/70SI Unit Conditions Min. Max. Min. Max. ILI Input Leakage Current - 1 - 1 µA VIN = GND to VCC ILO Output Leakage Current µA CE = VIH or LB = VIH or HB = VIH or OE = VIH or WE = VIH VI/O = GND to VCC ICC Active Power Supply Current - 5 - 5 mA CE = VIL, II/O = 0mA ICC1 - 50 - 50 mA Min. Cycle, Duty = 100% CE = VIL, II/O = 0mA ICC2 Dynamic Operating Current - 20 - 20 mA CE = VIL, VIH = VCC, VIL = 0V, f = 1MHz, II/O = 0 mA ISB - 0.5 - 0.5 mA CE = VIH ISB1 Standby Power Supply Current - 15 - 30 µA CE ≥ VCC - 0.2V VIN ≥ 0V VOL Output Low Voltage - 0.4 - 0.4 V IOL = 2.1mA VOH Output High Voltage 2.2 - 2.2 - V IOH = -1.0mA

PRELIMINARY (August, 2002, Version 0.5) 5 AMIC Technology, Inc. Truth Table CE OE WE LB HB I/O0 to I/O7 Mode I/O8 to I/O15 Mode VCC Current H X X X X Not selected Not selected ISB1, ISB L L Read Read ICC1, ICC2, ICC L L H L H Read High - Z ICC1, ICC2, ICC H L High - Z Read ICC1, ICC2, ICC L L Write Write ICC1, ICC2, ICC L X L L H Write Not Write/Hi - Z ICC1, ICC2, ICC H L Not Write/Hi - Z Write ICC1, ICC2, ICC L X High - Z High - Z ICC1, ICC2, ICC L H H X L High - Z High - Z ICC1, ICC2, ICC X X X H H Not selected Not selected ISB1, ISB Note: X = H or L Capacitance (TA = 25°C, f = 1.0MHz) Symbol Parameter Min. Max. Unit Conditions CIN* Input Capacitance - 6 pF VIN = 0V CI/O* Input/Output Capacitance - 8 pF VI/O = 0V * These parameters are sampled and not 100% tested.

PRELIMINARY (August, 2002, Version 0.5) 6 AMIC Technology, Inc. AC Characteristics (TA = 0°C to +70°C or -25°C to 85°C, VCC = 2.7V to 3.3V) Symbol Parameter A62S6316-55S/SI A62S6316-70S/SI Unit Min. Max. Min. Max. Read Cycle tRC Read Cycle Time 55 - 70 - ns tAA Address Access Time - 55 - 70 ns tACE Chip Enable Access Time - 55 - 70 ns tBE Byte Enable Access Time - 55 - 70 ns tOE Output Enable to Output Valid - 30 - 35 ns tCLZ Chip Enable to Output in Low Z 10 - 10 - ns tBLZ Byte Enable to Output in Low Z 5 - 5 - ns tOLZ Output Enable to Output in Low Z 5 - 5 - ns tCHZ Chip Disable to Output in High Z - 20 - 25 ns tBHZ Byte Disable to Output in High Z - 20 - 25 ns tOHZ Output Disable to Output in High Z - 20 - 25 ns tOH Output Hold from Address Change 5 - 10 - ns Write Cycle tWC Write Cycle Time 55 - 70 - ns tCW Chip Enable to End of Write 50 - 60 - ns tBW Byte Enable to End of Write 50 - 60 - ns tAS Address Setup Time 0 - 0 - ns tAW Address Valid to End of Write 50 - 60 - ns tWP Write Pulse Width 40 - 50 - ns tWR Write Recovery Time 0 - 0 - ns tWHZ Write to Output in High Z - 25 - 30 ns tDW Data to Write Time Overlap 25 - 30 - ns tDH Data Hold from Write Time 0 - 0 - ns tOW Output Active from End of Write 5 - 5 - ns Note: tCHZ, tBHZ and t OHZ and t WHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels.

PRELIMINARY (August, 2002, Version 0.5) 7 AMIC Technology, Inc. Timing Waveforms Read Cycle 1(1, 2, 4) tRC tOH tAA tOH Address DOUT Read Cycle 2(1, 2, 3) tRC tAA Address tACE tCHZ5 CE HB, LB tBHZ5 OE tCLZ5 tBE tBLZ5 tOE tOLZ5 tOHZ5 DOUT Notes: 1. WE is high for Read Cycle. 2. Device is continuously enabled CE = VIL, HB = VIL and, or LB = VIL. 3. Address valid prior to or coincident with CE and ( HB and, or LB ) transition low. 4. OE = VIL. 5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.

PRELIMINARY (August, 2002, Version 0.5) 8 AMIC Technology, Inc. Timing Waveforms (continued) Write Cycle 1 (Write Enable Controlled) tWC tAW Address DATA IN DATA OUT WE HB, LB CE tWR3 tCW tBW tAS1 tWP2 tDW tDH tOW tWHZ4

PRELIMINARY (August, 2002, Version 0.5) 9 AMIC Technology, Inc. Timing Waveforms (continued) Write Cycle 2 (Chip Enable Controlled) tWC tAW Address DATA IN DATA OUT WE HB, LB CE tWR3 tCW2 tBW tAS1 tWP tDW tDH tOW tWHZ4

PRELIMINARY (August, 2002, Version 0.5) 10 AMIC Technology, Inc. Timing Waveforms (continued) Write Cycle 3 (Byte Enable Controlled) tWC tAW Address DATA IN DATA OUT WE HB, LB CE tWR3 tCW tBW2tAS1 tWP tDW tDH tOW tWHZ4 Notes: 1. tAS is measured from the address valid to the beginning of Write. 2. A Write occurs during the overlap (t WP, tBW) of a low CE , WE and ( HB and, or LB ). 3. tWR is measured from the earliest of CE or WE or ( HB and, or LB ) going high to the end of the Write cycle. 4. OE level is high or low. 5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.

PRELIMINARY (August, 2002, Version 0.5) 11 AMIC Technology, Inc.

  • Including scope and jig. * Including scope and jig.

Figure 1. Output Load Figure 2. Output Load for tCLZ, tOLZ,

PRELIMINARY (August, 2002, Version 0.5) 12 AMIC Technology, Inc. Low VCC Data Retention Waveform VCC CE tCDR VIH 2.7V tR VIH 2.7V DATA RETENTION MODE VDR ≥ 2V CE ≥ VDR - 0.2V tVR

Ordering Information

Part No. Access Time (ns) Operating Current Max. (mA) Standby Current Max. (mmA) Package A62S6316V-55S 50 15 44L TSOP A62S6316V-55SI 50 30 44L TSOP A62S6316G-55S 50 15 48B Mini BGA A62S6316G-55SI 50 30 48B Mini BGA A62S6316V-70S 50 15 44L TSOP A62S6316V-70SI 50 30 44L TSOP A62S6316G-70S 50 15 48B Mini BGA A62S6316G-70SI 50 30 48B Mini BGA

PRELIMINARY (August, 2002, Version 0.5) 13 AMIC Technology, Inc.

Package Information

TSOP 44L (Type II) Outline Dimensions unit: inches/mm E c ZD D y e D b L L θ A1 A2 A Dimensions in inches Dimensions in mm Symbol Min Nom Max Min Nom Max A1 0.002 - 0.006 0.05 - 0.15 b 0.012 - 0.018 0.30 - 0.45 c 0.005 - 0.008 0.12 - 0.21 ZD 0.032 REF 0.805 REF L1 0.031 REF 0.80 REF e 0.031 BSC 0.80 BSC θ 0° - 5° 0° - 5° Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E1 does not include resin fins. 3. Dimension ZD includes end flash.

PRELIMINARY (August, 2002, Version 0.5) 14 AMIC Technology, Inc. Mini BGA 6X8 (48 BALLS) Outline Dimensions unit : millimeter(mm) Symbol Min Typ Max A - 0.75 - B 5.90 6.00 6.10 B1 - 3.75 - C 7.90 8.00 8.10 C1 - 5.25 - D 0.30 0.35 0.40 E 1.00 1.10 1.20 E1 - 0.36 - E2 0.17 0.22 0.27 123456 A B C D E F G H Bottom View Pin A1 Index Diameter D Solder Ball A A Top View Pin A1 Index B C 0.10 E D