A62L256 AMICC | Alldatasheet

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Preliminary 32K X 8 BIT LOW VOLTAGE CMOS SRAM PRELIMINARY (November, 2001, Version 1.4) AMIC Technology, Inc. Document Title 32K X 8 BIT LOW VOLTAGE CMOS SRAM

Revision History

Rev. No. History Issue Date Remark

1.0 Initial issue September 01, 1997

1.1 Modify 28-pin DIP, SOP and TSOP packages outline January 20, 1998

dimensions.

1.2 Modify 28-pin SOP and TSOP packages outline drawings June 17, 1998

1.3 Add -LLU type April 11, 2001

Change operating voltage Vccmax from 3.3V to 3.6V

1.4 Add Product Family in page 1 November 30, 2001

Add ICC2(typ.) ICCDR(typ.) Change ISB1(typ.) ICCDR(max.) Change ordering information from ICC1 to ICC2

Preliminary 32K X 8 BIT LOW VOLTAGE CMOS SRAM PRELIMINARY (November, 2001, Version 1.4) 2 AMIC Technology, Inc.

Features

n External Operating Voltage: 2.7V to 3.6V n Access times: 55ns (max.): for VCC = 3.0V to 3.6V 70ns (max.): for VCC = 2.7V to 3.6V n Current: Operating (ICC1): -55 series 18mA (typ.) -70 series 12mA (typ.) Standby (ISB1): 0.05µA (typ.) n Extended operating temperature range: -40º C to +85º C for -LLU series n Full static operation, no clock or refreshing required n All inputs and outputs are directly TTL-compatible n Common I/O using three-state output n Data retention voltage: 2.0V (min.) n Available in 28-pin DIP, SOP and TSOP (forward and reverse type) packages General Description The A62L256 is a low operating current 262,144 -bit static random access memory organized as 32,768 words by 8 bits and operates on a low power voltage: 2.7V to 3.6V. Inputs and three -state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Minimum standby power is drawn by this device when CE is at a high level, independent of the other input levels. Data retention is guaranteed at a power supply voltage as low as 2.0V. Product Family Power Dissipation Product Family Operating Temperature VCC Range Speed Data Retention (ICCDR, Typ.) Standby (ISB1, Typ.) Operating (ICC2, Typ.) Package Type A62L256 -40°C ~ +85°C 2.7V~3.6V 55ns / 70ns 0.02µA 0.05µA 1mA 28L DIP 28L SOP 28L TSOP 1. Typical values are measured at VCC = 3.0V, TA = 25°C and not 100% tested. 2. Data retention current VCC = 2.0V. Pin Configurations n DIP n SOP n TSOP A14 A12 I/O0 I/O1 I/O2 GND I/O3 I/O4 I/O5 I/O6 I/O7 CE OE A11 A13 WE VCC A10 A62L256 14 15

28 A14

PRELIMINARY (November, 2001, Version 1.4) 3 AMIC Technology, Inc. Block Diagram ROW DECODER

512 X 512

Pin Descriptions - DIP/SOP Pin No. Symbol Description 1-10, 21, 23-26 A0 - A14 Address Input 11-13, 15-19 I/O0 - I/O7 Data Input/Output

14 GND Ground

20 CE Chip Enable

22 OE Output Enable

27 WE Write Enable

28 VCC Power Supply

Pin No. Symbol Description

1 OE Output Enable

2-5, 8-17, 28 A0 - A14 Address Input

7 VCC Power Supply

6 WE Write Enable

18-20, 22-26 I/O0 - I/O7 Data Input/Output

21 GND Ground

27 CE Chip Enable

PRELIMINARY (November, 2001, Version 1.4) 4 AMIC Technology, Inc. Recommended DC Operating Conditions (TA = 0°C to + 70°C or -40°C to +85°C) Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage 2.7 3.0 3.6 V GND Ground 0 0 0 V VIH Input High Voltage VCC * 0.7 - VCC + 0.3 V VIL Input Low Voltage -0.3 0 +0.3 V Absolute Maximum Ratings* *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only. Functional operation of this device at these or any oth er conditions above those indicated in the operational sections of this specification is not implied and exposure to absolute maximum rating conditions for extended periods may affect device reliability. Symbol Parameter A62L256-55LL/55LLU A62L256-70LL/70LLU Unit Conditions ILI Input Leakage Current - - 1 - - 1 µA VIN = GND to VCC ILO Output Leakage Current - - 1 - - 1 µA CE = VIH or WE = VIL VI/O = GND to VCC ICC1 Dynamic Operating Current - *18 25 - **12 20 mA Min. Cycle, Duty = 100% CE = VIL, II/O = 0mA ICC2 Dynamic Operating Current mA CE = VIL, VIH = VCC VIL = 0V, f = 1 MHz II/O = 0 mA Typical values are measured at VCC = 3.0V, TA = 25°C and not 100% tested. * Testing condition : TA = 25°C, VCC = 3.0V, Cycle Time = 55 ns ** Testing condition : TA = 25°C, VCC = 3.0V, Cycle Time = 70 ns

PRELIMINARY (November, 2001, Version 1.4) 5 AMIC Technology, Inc. Symbol Parameter A62L256-55LL/70LL A62L256-55LLU/70LLU Unit Conditions ISB Supply Current - - 50 - - 50 µA CE = VIH ISB1 Standby Power - 0.05 2 - 0.05 5 µA CE ≥ VCC - 0.2V VIN ≥ 0V VOL Output Low Voltage VOH Output High Voltage VCC - 0.3 - - VCC - 0.3 - - V IOH = -1.0mA Typical values are measured at VCC = 3.0V, TA = 25°C and not 100% tested. Truth Table Mode CE OE WE I/O Operation Supply Current Standby H X X High Z ISB, ISB1 Output Disable L H H High Z ICC, ICC1, ICC2 Read L L H DOUT ICC, ICC1, ICC2 Write L X L DIN ICC, ICC1, ICC2 Note: X: H or L Capacitance (TA = 25°C, f = 1.0 MHz) Symbol Parameter Min. Max. Unit Conditions CIN* Input Capacitance 6 pF VIN = 0V CI/O* Input/Output Capacitance 8 pF VI/O = 0V These parameters are sampled and not 100% tested.

PRELIMINARY (November, 2001, Version 1.4) 6 AMIC Technology, Inc. AC Characteristics (TA = 0°C to +70°C or -40º C to +85º C) Symbol Parameter A62L256-55LL/LLU (VCC = 3.0V to 3.6V) A62L256-70LL/LLU (VCC = 2.7V to 3.6V) Unit Min. Max. Min. Max. Read Cycle tRC Read Cycle Time 55 - 70 - ns tAA Address Access Time - 55 - 70 ns tACE Chip Enable Access Time - 55 - 70 ns tOE Output Enable to Output Valid - 30 - 35 ns tCLZ Chip Enable to Output in Low Z 10 - 10 - ns tOLZ Output Enable to Output in Low Z 5 - 5 - ns tCHZ Chip Disable to Output in High Z - 20 - 25 ns tOHZ Output Disable to Output in High Z - 20 - 25 ns tOH Output Hold from Address Change 5 - 10 - ns Write Cycle tWC Write Cycle Time 55 - 70 - ns tCW Chip Enable to End of Write 50 - 60 - ns tAS Address Set up Time 0 - 0 - ns tAW Address Valid to End of Write 50 - 60 - ns tWP Write Pulse Width 40 - 50 - ns tWR Write Recovery Time 0 - 0 - ns tWHZ Write to Output in High Z - 25 - 25 ns tDW Data to Write Time Overlap 25 - 30 - ns tDH Data Hold from Write Time 0 - 0 - ns tOW Output Active from End of Write 5 - 5 - ns Notes: tCHZ, t OHZ and t WHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels.

PRELIMINARY (November, 2001, Version 1.4) 7 AMIC Technology, Inc. Timing Waveforms Read Cycle 1 (1) tRC tAA tOH Address DOUT tOHZ5 tCHZ5 tACE tCLZ5 tOLZ5 tOE CE OE Read Cycle 2 (1, 2, 4) tRC tOH tAA tOH Address DOUT

PRELIMINARY (November, 2001, Version 1.4) 8 AMIC Technology, Inc. Timing Waveforms (continued) Read Cycle 3 (1, 3, 4) tCLZ 5 tACE tCHZ 5 CE DOUT Notes: 1. WE is high for Read Cycle. 2. Device is continuously enabled, CE = VIL. 3. Address valid prior to or coincident with CE transition low. 4. OE = VIL. 5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested. Write Cycle 1 (6) (Write Enable Controlled) tWC Address CE DIN tOW 7 tDHtDW tWHZ 7 tWP2tAS1 (4) tCW5 tAW tWR3 WE DOUT

PRELIMINARY (November, 2001, Version 1.4) 9 AMIC Technology, Inc. Timing Waveforms (continued) Write Cycle 2 (6) (Chip Enable Controlled) tWC Address CE DIN tDHtDW (4) tCW5 tAW tWR3 WE DOUT tWHZ7 tWP2 tAS1 Notes: 1. tAS is measured from the address valid to the beginning of Write. 2. A Write occurs during the overlap (t WP) of a low CE and a low WE . 3. tWR is measured form the earliest of CE or WE going high to the end of the Write cycle. 4. If the CE low transition occurs simultaneously with the WE low transition or after the WE transition, outputs remain in a high impedance state. 5. tCW is measured from the later of CE going low to the end of Write. 6. OE level is high or low. 7. Transition is measured ±500mV from steady. This parameter is sampled and not 100% tested.

PRELIMINARY (November, 2001, Version 1.4) 10 AMIC Technology, Inc. Figure 1. Output Load Typical values are measured at TA = 25°C.

PRELIMINARY (November, 2001, Version 1.4) 11 AMIC Technology, Inc.

Ordering Information

Part No. Access Time (ns) Operating Current (ICC2) Max. (mA) Standby Current (ISB1) Max. (µA) Package A62L256-55LL 3 2 28L DIP A62L256M-55LL 55 3 2 28L SOP A62L256V-55LL 3 2 28L TSOP (Forward) A62L256R-55LL 3 2 28L TSOP (Reverse) A62L256-70LL 3 2 28L DIP A62L256M-70LL 70 3 2 28L SOP A62L256V-70LL 3 2 28L TSOP (Forward) A62L256R-70LL 3 2 28L TSOP (Reverse) A62L256-55LLU 3 5 28L DIP A62L256M-55LLU 55 3 5 28L SOP A62L256V-55LLU 3 5 28L TSOP (Forward) A62L256R-55LLU 3 5 28L TSOP (Reverse) A62L256-70LLU 3 5 28L DIP A62L256M-70LLU 70 3 5 28L SOP A62L256V-70LLU 3 5 28L TSOP (Forward) A62L256R-70LLU 3 5 28L TSOP (Reverse)

PRELIMINARY (November, 2001, Version 1.4) 12 AMIC Technology, Inc.

Package Information

P-DIP 28L Outline Dimensions unit: inches/mm S AL E eA D C α B Base Plane Seating Plane Dimensions in inches Dimensions in mm Symbol Min Nom Max Min Nom Max D - 1.460 1.470 - 37.08 37.34 Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E1 does not include resin fins. 3. Dimension S includes end flash.

PRELIMINARY (November, 2001, Version 1.4) 13 AMIC Technology, Inc. SOP (W.B.) 28L Outline Dimensions unit: inches/mm E H L c See Detail F Detail F B 1528 A1 A2 A S D Seating Plane D y ey θ Dimensions in inches Dimensions in mm Symbol Min Nom Max Min Nom Max D - 0.713 0.728 - 18.11 18.49 ο 0° - 8° 0° - 8° Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension S includes end flash.

PRELIMINARY (November, 2001, Version 1.4) 14 AMIC Technology, Inc. TSOP 28L TYPE I (8 X 13.4mm) Outline Dimensions unit: inches/mm Dimensions in inches Dimensions in mm Symbol Min Nom Max Min Nom Max c 0.005 - 0.008 0.12 - 0.21 e 0.022 BSC 0.55 BSC S 0.017 TYP 0.425 TYP θ 0° - 5° 0° - 5° Notes: 1. The maximum value of dimension D1 includes end flash. 2. Dimension E does not include resin fins. 3. Dimension S includes end flash. E e D L A c Detail "A" D y Detail "A" S b θ