A627308

A627308 AMICC | Alldatasheet

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Technical content

Preliminary 128K X 8 BIT CMOS SRAM PRELIMINARY (February, 2001, Version 0.2) AMIC Technology, Inc. Document Title 128K X 8 BIT CMOS SRAM

Revision History

Rev. No. History Issue Date Remark

0.0 Initial issue August 15, 2000 Preliminary

0.1 Omit 100ns grade items October 25, 2000

Change I CC1 from 70mA to 45mA Change I SB1 from 25 µA to 15 µA 0 .2 Change I SB1 from 15 µA to 25 µA February 6, 2001

Preliminary 128K X 8 BIT CMOS SRAM PRELIMINARY (February, 2001, Version 0.2) 1 AMIC Technology, Inc. NC A14 A12 I/O 0 I/O 1 I/O 2 I/O 3GND I/O 4 I/O 5 I/O 6 I/O 7 A10 A13 CE2 A15 VCC A11 A627308M 16 17 OE CE1 WE A10 GND OE CE1 A16 A627308V (A627308X) A11 A9 2 A13 VCC NC A14 A12 I/O I/O I/O I/O I/O A15 WE CE2 I/O I/O I/O ~~ ~~ A16

Features

n Power supply range: 4.5V to 5.5V n Access times: 70 ns (max.) n Current: Operating: 45mA (max.) Standby: 25 µA (max.) n Full static operation, no clock or refreshing required n All inputs and outputs are directly TTL compatible n Common I/O using three - state output n Output enable and two chip enable inputs for easy application n Data retention voltage: 2V (mi n.) n Available in 32 - pin SOP, TSOP, sTSOP (8X 13.4mm) forward type packages General Description The A627308 is a low operating current 1048,576 - bit static random access memory organized as 131,072 words by 8 bits and operates on a power supply voltage from 4.5V to 5.5V. Inputs and three - state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Two chip enable inputs are provided for power down and a write enable and an output enable input are included for easy i nterfacing. Data retention is guaranteed at a power supply voltage as low as 2V. Pin Configurations nn SOP nn TSOP/(sTSOP) (forward type)

P RELIMINARY (February, 2001, Version 0.2) 2 AMIC Technology, Inc. Block Diagram ROW DECODER

512 X 2048

Pin No. Symbol Description 2 - 12, 23, 25 - 28, 31 A0 - A16 Address Inputs 13 - 15, 17 - 21 I/O 0 - I/O 7 Data Inputs/Outputs

22 CE1 Chip Enable 1

30 CE2 Chip Enable 2

24 OE Output Enable

29 WE Write Enable

32 VCC Po wer Supply

16 GND Ground

1 NC No Connection

Pin Description - TSOP/sTSOP Pin No. Symbol Description 1 - 4, 7, 10 - 20, 31 A0 - A16 Address Inputs 21 - 23, 25 - 29 I/O 0 - I/O 7 Data Inputs/Outputs

30 CE1 Chip Enable 1

6 CE2 Ch ip Enable 2

32 OE Output Enable

5 WE Write Enable

8 VCC Power Supply

24 GND Ground

9 NC No Connection

P RELIMINARY (February, 2001, Version 0.2) 3 AMIC Technology, Inc. Recommended DC Operating Conditions (T A = 0 °C to + 70 °C) Symbol Parameter Min. Typ. Max. Unit VCC Suppl y Voltage 4.5 5.0 5.5 V GND Ground 0 0 0 V V IH Input High Voltage 2.2 - VCC + 0.5 V V IL Input Low Voltage - 0.5 - +0.8 V C L Output Load - - 30 pF TTL Output Load - - 1 - Absolute Maximum Ratings* 7.0V *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. Symbol Parameter A627308-70S Unit Conditions Min. Max. ILI Input Leakage Current - 1 µA V IN = GND to VCC ILO Output Leakage Current - 1 µA CE1 = V IH o r CE2 = V IL or OE = V IH or WE = V IL V I/O = GND to VCC ICC Active Power Supply Current - 7 mA CE1 = V IL, CE2 = V IH I I/O = 0mA ICC1 Dynamic Operating Current - 45 mA Min. Cycle, Duty = 100% CE1 = V IL, CE2 = V IH I I/O = 0mA ICC2 Dynamic Operating Current - 7 mA CE1 = V IL, CE2 = V IH V IH = VCC , V IL = 0V F = 1MHz, II/O = 0mA

P RELIMINARY (February, 2001, Version 0.2) 4 AMIC Technology, Inc. Symbol Parameter A627308-70S Unit Conditions Min. Max. ISB - 0.5 mA CE1 = V IH or CE2 = V IL ISB1 Standby Power Supply Current - 25 µA CE2 ≤ 0.2V, or CE1 ≥ VCC - 0.2V V OL Output Low Voltage - 0.4 V I OL = 2.1mA V OH Output High Voltage 2.4 - V I OH = - 1.0mA Truth Table Mode CE1 CE2 OE WE I/O Operation Supply Current Standby H X X X High Z ISB, I SB1 X L X X High Z ISB, I SB1 Output Disable L H H H High Z ICC, ICC1, ICC2 Rea d L H L H D OUT ICC, ICC1, ICC2 Write L H X L D IN ICC, ICC1, I CC2 Note: X = H or L Capacitance (T A = 25 °C, f = 1.0MHz) Symbol Parameter Min. Max. Unit Conditions C IN* Input Capacitance - 6 pF V IN = 0V C I/O* Input/Output Capacitance - 8 pF V I/O = 0V * These parameters are sampled and not 100% tested.

P RELIMINARY (February, 2001, Version 0.2) 5 AMIC Technology, Inc. AC Characteristics (T A = 0 °C to + 70 °, VCC = 5.0V ±10%) Symbol Parameter A627308-70S Unit Min. Max. Read Cycle tRC Read Cycle Time 70 - ns tAA Address Access Time - 70 ns tACE1 Chip Enable Acce ss Time CE1 - 70 ns tACE2 CE2 - 70 ns tOE Output Enable to Output Valid - 35 ns tCLZ1 Chip Enable to Output in Low Z CE1 10 - ns tCLZ2 CE2 10 - ns tOLZ Output Enable to Output in Low Z 5 - ns tCHZ1 Chip Disab le to Output in High Z CE1 0 25 ns tCHZ2 CE2 0 25 ns tOHZ Output Disable to Output in High Z 0 25 ns tOH Output Hold from Address Change 10 - ns Write Cycle tWC Write Cycle Time 70 - ns tCW Chip Enable to End of Write 60 - ns tAS Address Setup Time 0 - ns tAW Address Valid to End of Write 60 - ns tWP Write Pulse Width 50 - ns tWR Write Recovery Time 0 - ns tWHZ Write to Output in High Z 0 30 ns tDW Data to Write Time Overlap 30 - ns tDH Data Hold from Write Time 0 - ns tOW Output Active from End of Write 5 - ns Notes: tCHZ1, t CHZ2, t OHZ and t WHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels.

P RELIMINARY (February, 2001, Version 0.2) 6 AMIC Technology, Inc. Timing Waveforms Read Cycle 1(1) tRC Address CE2 D OUT tAA tOE tOLZ5 tACE1 tCLZ15 tACE2 tCLZ25 tCHZ25 tOHZ5 tCHZ15 tOH OE CE1 Read Cycle 2 (1, 2, 4) tRC tOH tAA tOH Address D OUT

P RELIMINARY (February, 2001, Version 0.2) 7 AMIC Technology, Inc. Timing Waveforms (continued) Read Cycle 3 (1, 3, 4, 6) tCLZ15 tACE1 tCHZ15 CE1 D OUT Read Cycle 4 (1, 4, 7, 8) tCLZ25 tACE2 tCHZ25 CE2 D OUT Notes: 1. WE is high for Read Cycle. 2. Device is continuously enabled CE1 = V IL and CE2 = V IH. 3. Address valid prior to or coincident with CE1 transition low. 4. OE = V IL. 5. Transition is measured ±50 0mV from steady state. This parameter is sampled and not 100% tested. 6. CE2 is high. 7. CE1 is low. 8. Address valid prior to or coincident with CE2 transition high.

P RELIMINARY (February, 2001, Version 0.2) 8 AMIC Technology, Inc. Timing Waveforms (continued) Write Cycle 1(6) (Write Enable Controlled) tWC Address CE1 CE2 D IN tOW tDHtDW tWHZ tWP2tAS1 (4) tCW5 tAW tWR3 WE D OUT (4)

P RELIMINARY (February, 2001, Version 0.2) 9 AMIC Technology, Inc. Timing Waveforms (continued) Write Cycle 2(6) (Chip Enable Controlled) tWC Address CE1 CE2 D IN tDHtDW (4) (4) tCW5 tAW tWR3 WE D OUT tWHZ7 tWP2 tCW5 tAS1 Notes: 1. t AS is measured from the address valid to the beginning of Write. 2. A Write occurs during the over lap (t WP) of a low CE1 , a high CE2 and a low WE . 3. t WR is measured from the earliest of CE1 or WE going high or CE2 going low to the end of the Write cycle. 4. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transition or after the WE transition, outputs remain in a high impedance state. 5. t CW is measured from th e later of CE1 going low or CE2 going high to the end of Write. 6. OE is continuously low. ( OE = V IL) 7. Transition is measured ±500mV from steady state. This parameter is sampled and not 100 % tested.

P RELIMINARY (February, 2001, Version 0.2) 10 AMIC Technology, Inc.

• Including scope and jig. * Including scope and jig.

Figure 1. Output Load Figure 2. Output Load for tCLZ1,

P RELIMINARY (February, 2001, Version 0.2) 11 AMIC Technology, Inc. Low VCC Data Retention Waveform (1) ( CE1 Controlled) VCC CE1 tCDR V IH 4.5V tR V IH 4.5V DATA RETENTION MODE V DR ≥ 2V CE1 ≥ V DR - 0.2V tVR Low VCC Data Retention Waveform (2) (CE2 Controlled) VCC CE2 tCDR V IL 4.5V tR V IL 4.5V DATA RETENTION MODE V DR ≥ 2V CE2 ≤ 0.2V tVR

P RELIMINARY (February, 2001, Version 0.2) 12 AMIC Technology, Inc.

Ordering Information

Part No. Access Time (ns) Operating Current Max. (mA) Standby Current Max. (µµA) Package A627308M - 70S 32L SOP A627308V - 70S 32L TSOP A627308X - 70S 70 45 25 32L sTSOP

P RELIMINARY (February, 2001, Version 0.2) 13 AMIC Technology, Inc.

Package Information

SOP (W.B.) 32L Outline Dimensions unit: inches/mm E H E L L E c See Detail F Detail F 1732 A 1 A 2 A S D Seating Plane D y e b θ Dimensions in inches Dimensions in mm Symbol Min Nom Max Min Nom Max D - 0.805 0.817 - 20.45 20.75 Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension S includes end flash.

P RELIMINARY (February, 2001, Version 0.2) 14 AMIC Technology, Inc. TSOP 32L TYPE I (8 X 20mm) Outline Dimensions unit: inches/mm e L E L A A 2 c D y Detail "A" S A 1 b H D D E θ Detail "A" Dimensions in inches Dimensions in mm Symbol Min Nom Max Min Nom Max A 1 0.002 - 0.006 0.05 - 0.15 c 0.004 - 0.008 0.11 - 0.20 E - 0.315 0.319 - 8.00 8.10 e 0.020 BSC 0.50 BSC Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension S includes end flash.

P RELIMINARY (February, 2001, Version 0.2) 15 AMIC Technology, Inc. sTSOP 32L TYPE I (8 X 13.4mm) Outline Dimensions unit: inches/mm e Detail "A" D 0.076MM Detail "A" S b D 1 E D L E L A A 2 c θ A 1 SEATING PLANE Dimensions in inches Dimensions in mm Symbol Min Nom Max Min Nom Max e 0.020 TYP 0.50 TYP S 0.0109 TYP 0.278 TYP θ 0 ° 3 ° 5 ° 0 ° 3 ° 5 ° Notes: 1. The maximum value of dimension D 1 includes end flash. 2. Dimension E does not include resin fins. 3. Dimension S includes end flash.