A617308S-15

A617308 AMICC | Alldatasheet

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Technical content

Preliminary 128K X 8 BIT HIGH SPEED CMOS SRAM PRELIMINARY (January, 2000, Version 0.2 ) AMIC Technology, Inc. Document Title 128K X 8 BIT HIGH SPEED CMOS SRAM

Revision History

Rev. No. History Issue Date Remark

0.0 Initial issue September 17, 1999 Preliminary

0.1 Change V DR(Max.) from 3.6V to 5.5V November 30, 1999 Add 32-pin SOP package Modify 32-pin SOJ package outline drawing and Dimensions

0.2 Add 15ns part January 19, 2000

Change operating current from 180mA to 150mA (Max.) Change V DR(Min.) from 2V to 3V Remove 32-pin SOP package

Preliminary 128K X 8 BIT HIGH SPEED CMOS SRAM PRELIMINARY (January, 2000, Version 0.2 ) 1 AMIC Technology, Inc.

Features

nAcc ess times: 10/12/15 ns (max.) nCurrent: Operating: 150mA (max.) Standby: 12mA (max.) nFull static operation, no clock or refreshing required nAll inputs and outputs are directly TTL compatible nCommon I/O using three-state output nData retention v oltage: 3V (min.) nAvailable in 32-pin SOJ and TSOP packages General Description The A617308 is a high-speed, low-power 1,048,576-bit static random access memory organized as 131,072 words by 8 bits and operates on a single 5V power supply. It is built using high performance CMOS process. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Minimum standby power is drawn by this device when chip enable is disable, independent of the other input levels. Data retention is guaranteed at a power supply voltage as low as 3V. Pin Configurations n SOJ nn TSOP A10 GND OE CE1 A11 A9 2 A13 VCC NC A14 A12 I/O I/O I/O I/O I/O A15 WE CE2 I/O I/O I/O ~~ ~~ A16 A617308V NC A14 A12 I/O 0 I/O 1 I/O 2 I/O 3GND I/O 4 I/O 5 I/O 6 I/O 7 A10 A13 CE2 A15 VCC A11 A617308S 16 17 OE CE1 WE A16

PRELIMINARY (January, 2000, Version 0.2) 2 AMIC Technology, Inc. Block Diagram Pin Descriptions – SOJ Pin No. Symbol Description 2 - 12, 23, 25 - 28, 31 A0 - A16 Address Inputs 13 - 15, 17 - 21 I/O 0 - I/O 7 Data Inputs/Outputs

22 CE1 Chip Enable 1

30 CE2 Chip Enable 2

24 OE Output Enable

29 WE Write Enable

32 VCC Power Supply

16 GND Ground

1 NC No Connection

Pin No. Symbol Description 1 - 4, 7, 10 - 20, 31 A0 - A16 Address Inputs 21 - 23, 25 - 29 I/O 0 - I/O 7 Data Inputs/Outputs

30 CE1 Chip Enable 1

6 CE2 Chip Enable 2

32 OE Output Enable

5 WE Write Enable

8 VCC Power Supply

24 GND Ground

9 NC No Connection

1,048,576-BIT MEMORY ARRAY I/O CONTROL CONTROL LOGICCE1 A16 OE WE I/O 0 - I/O 7 CE2

PRELIMINARY (January, 2000, Version 0.2 ) 3 AMIC Technology, Inc. Recommended DC Operating Conditions (T A = 0 °C to + 70 °C) Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage 4.5 5.0 5.5 V GND Ground 0 0 0 V V IH Input High Voltage 2.2 - VCC + 0.5 V V IL Input Low (1) Voltage -0.5 0 +0.8 V C L Output Load - - 30 pF Absolute Maximum Ratings* *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. Symbol Parameter A617308-10/12/15 Unit Conditions Min. Max. ILI Input Leakage - 5 µA V IN = GND to VCC ILO Output Leakage - 5 µA 1CE = V IH, CE2= V IL or OE = V IH V I/O = GND to VCC ICC1 (2) Dynamic Operating Current - 150 mA 1CE = V IL, CE2 = V IH , I I/O = 0 mA Min. Cycle, Duty = 100% ISB - 35 mA 1CE = V IH or CE2 = V IL ISB1 Standby Power Supply Current - 12 mA 1CE ≥ VCC - 0.2V, CE2 ≤ 0.2V V IN ≥ VCC -0.2V or V IN ≤ 0.2V V OL Output Low Voltage - 0.4 V IOL = 8 mA V OH Output High Voltage 2.4 - V IOH = -4 mA Notes: 1. V IL = -3.0V for pulses less than 20 ns. 2. ICC1 is dependent on output loading, cycle rates, and Read/Write patterns.

PRELIMINARY (January, 2000, Version 0.2) 4 AMIC Technology, Inc. Truth Table Mode 1CE CE2 OE WE I/O Operation Supply Current H X X X High Z ISB, I SB1 Standby X L X X High Z ISB, I SB1 Output Disable L H H H High Z ICC1 Read L H L H D OUT ICC1 Write L H X L D IN ICC1 Note: X = H or L Capacitance (T A = 25 °C, f = 1.0MHz) Symbol Parameter Min. Max. Unit Conditions C IN* Input Capacitance - 8 pF V IN = 0V C I/O* Input/Output Capacitance - 8 pF V I/O = 0V * These parameters are sampled and not 100% tested. AC Characteristics (T A = 0 °C to +70 °C, VCC = 5V ± 10%) Symbol Parameter A617308-10 A617308-12 A617308-15 Unit Read Cycle t RC Read Cycle Time 10 - 12 - 15 - ns t AA Address Access Time - 10 - 12 - 15 ns tACE Chip Enable Access Time - 10 - 12 - 15 ns tOE Output Enable to Output Valid - 5 - 6 - 8 ns tCLZ Chip Enable to Output in Low Z 3 - 3 - 3 - ns tOLZ Output Enable to Output in Low Z 0 - 0 - 0 - ns tCHZ Chip Disable Output in High Z 0 5 0 6 - 8 ns tOHZ Output Disable to Output in High Z 0 5 0 6 0 8 ns t OH Output Hold from Address Change 3 - 3 - 3 - ns

PRELIMINARY (January, 2000, Version 0.2) 5 AMIC Technology, Inc. AC Characteristics (continued) Symbol Parameter A617308-10 A617308-12 A617308-15 Unit Write Cycle tWC Write Cycle Time 10 - 12 - 15 - ns tCW Chip Enable to End of Write 9 - 10 - 12 - ns tAS Address Setup Time of Write 0 - 0 - 0 - ns tAW Address Valid to End of Write 9 - 10 - 12 - ns tWP Write Pulse Width 9 - 10 - 12 - ns tWR Write Recovery Time 0 - 0 - 0 - ns tWHZ Write to Output in High Z 0 5 0 6 0 8 ns tDW Data to Write Time Overlap 5 - 6 - 7 - ns tDH Data Hold from Write Time 0 - 0 - 0 - ns tOW Output Active from End of Write 3 - 3 - 3 - ns Notes: tCHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. Timing Waveforms Read Cycle 1(1) tRC Address CE2 D OUT tAA tOE tOLZ5 tACE tCHZ5 tOHZ5 tOH OE CE1 tCLZ5

PRELIMINARY (January, 2000, Version 0.2) 6 AMIC Technology, Inc. Timing Waveforms (continued) Read Cycle 2(1, 2, 4) tRC tOH tAA tOH Address D OUT Read Cycle 3(1, 3, 4, 6) tCLZ5 tACE tCHZ5 D OUT CE1

PRELIMINARY (January, 2000, Version 0.2) 7 AMIC Technology, Inc. Timing Waveforms (continued) Read Cycle 4(1, 4, 7, 8) tCLZ5 tACE tCHZ5 D OUT CE2 Notes: 1. WE is high for Read Cycle. 2. Device is continuously enabled, CE1 = V IL and CE2= V IH 3. Address valid prior to or coincident with CE1 transition low. 4. OE = V IL. 5. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested. 6. CE2 is high. 7. CE1 is low. 8. Address valid prior to or coincident with CE2 transition high. Write Cycle 1(6) (Write Enable Controlled) tWC Address CE1 CE2 D IN tDHtDW tWP2tAS1 (4) tCW5 tAW tWR3 WE D OUT (4) tOW7 tWHZ7

PRELIMINARY (January, 2000, Version 0.2) 8 AMIC Technology, Inc. Timing Waveforms (continued) Write Cycle 2 (Chip Enable Controlled) tWC Address CE1 CE2 D IN tDHtDW (4) tCW5 tAW tWR3 WE D OUT tWHZ7 tWP2 tAS1 (4) Notes: 1. tAS is measured from the address valid to the beginning of Write. 2. A Wri te occurs during the overlap ( tWP) of a low CE1 , a high CE2 and a low WE . 3. tWR is measured from the earliest of CE1 or WE going high or CE2 going low to the end of the Write cycle. 4. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transition or after the WE transition, outputs remain in a high impedance state. 5. tCW is measured from the later of CE1 going low or CE2 going high to the end of Write. 6. OE is continuously low. ( OE = V IL) 7. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested.

PRELIMINARY (January, 2000, Version 0.2) 9 AMIC Technology, Inc. Figure 1. Output Load Figure 2. Output Load for tCLZ, tOLZ,

PRELIMINARY (January, 2000, Version 0.2) 10 AMIC Technology, Inc. Low VCC Data Retention Waveform (1) (CE1 controlled) VCC CE1 tCDR V IH 4.5V tR V IH 4.5V DATA RETENTION MODE V DR > 3.0V CE1 > V DR - 0.2V Low VCC Data Retention Waveform (2) (CE2 controlled) VCC CE2 tCDR V IL 4.5V tR V IL 4.5V DATA RETENTION MODE V DR > 3.0V CE2 < 0.2V

Ordering Information

Part No. Access Time (ns) Operating Current Max. (mA) Standby Current Max. (mA) Package A617308S-10 10 150 12 32L SOJ A617308S-12 12 150 12 32L SOJ A617308S-15 15 150 12 32L SOJ A617308V-10 10 150 12 32L TSOP A617308V-12 12 150 12 32L TSOP A617308V-15 15 150 12 32L TSOP

PRELIMINARY (January, 2000, Version 0.2) 11 AMIC Technology, Inc.

Package Information

SOJ 32L Outline Dimensions unit: inches/mm Dimensions in inches Dimensions in mmSymbol Min Nom Max Min Nom Max Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension E 1 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash. A 1 A 2 A e E 2 C 1732 S Seating Plane D y b 1 b E 1 D Min 0.025" 0.004 E yy

PRELIMINARY (January, 2000, Version 0.2) 12 AMIC Technology, Inc. TSOP 32L TYPE I (8 X 20mm) Outline Dimensions unit: inches/mm e L E L A A 2 c D y Detail "A" S A 1 b H D D E θ Detail "A" Dimensions in inches Dimensions in mm Symbol Min Nom Max Min Nom Max A 1 0.002 - 0.006 0.05 - 0.15 c 0.004 - 0.008 0.11 - 0.20 E - 0.315 0.319 - 8.00 8.10 e 0.020 BSC 0.50 BSC Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension S includes end flash.