A6173081 AMICC | Alldatasheet

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Preliminary 128K X 8 BIT HIGH SPEED CMOS SRAM PRELIMINARY (July, 2000, Version 0.0 ) AMIC Technology, Inc. Document Title 128K X 8 BIT HIGH SPEED CMOS SRAM

Revision History

Rev. No. History Issue Date Remark

0.0 Initial issue July 14, 2000 Preliminary

Preliminary 128K X 8 BIT HIGH SPEED CMOS SRAM PRELIMINARY (July, 2000, Version 0.0 ) 1 AMIC Technology, Inc.

Features

n Supply voltage: 5V ±10% nAccess times: 12/15 ns (max.) nCurrent: Ope rating: -12: 170mA (max.) -15: 165mA (max.) Standby: TTL: 25mA (max.) CMOS: 8mA (max.) nFull static operation, no clock or refreshing required nAll inputs and outputs are directly TTL compatible nCommon I/O using three-state output nData reten tion voltage: 3V (min.) nAvailable in 32-pin 300mil / 400mil SOJ packages General Description The A6173081 is a high-speed 1,048,576-bit static random access memory organized as 131,072 words by 8 bits and operates on a 5V power supply. It is built using high performance CMOS process. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Minimum standby power is drawn by this device when chip enable is disable, independent of the other input levels. Data retention is guaranteed at a power supply voltage as low as 3V. Pin Configurations n SOJ I/O 0 I/O 1 VCC GND I/O 2 I/O 3 A8A7 A10 A11 A12 I/O 5 I/O 6 I/O 7 A14 A15 A16 GND A6173081S(SW) 16 17 VCC I/O 4 OE CE WE A13

PRELIMINARY (July, 2000, Version 0.0) 2 AMIC Technology, Inc. Block Diagram Pin Descriptions – SOJ Pin No. Symbol Description 1-4, 13-21, 29-32 A0 - A16 Address Inputs 6-7, 10-11, 22-23, 26-27 I/O 0 - I/O 7 Data Inputs/Outputs

5 CE Chip Enable

28 OE Output Enable

12 WE Write Enable

8, 24 VCC Power Supply 9, 25 GND Ground ADDRESS DECODER 1,048,576-BIT MEMORY ARRAY I/O CONTROL CONTROL LOGIC A16 OE WE I/O 0 - I/O 7 CE

PRELIMINARY (July, 2000, Version 0.0) 3 AMIC Technology, Inc. Recommended DC Operating Conditions (T A = 0 °C to + 70 °C) Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage 4.5 5.0 5.5 V GND Ground 0 0 0 V V IH Input High Voltage 2.2 - VCC + 0.5 V V IL Input Low (1) Voltage -0.5 0 +0.8 V C L Output Load - - 30 pF Absolute Maximum Ratings* *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. Symbol Parameter A6173081-12 A6173081-15 Unit Conditions Min. Max. Min. Max. ILI Input Leakage - 2 - 2 µA V IN = GND to VCC ILO Output Leakage - 2 - 2 µA CE = V IH, OE = V IH V I/O = GND to VCC ICC1 (2) Dynamic Operating Current - 170 - 165 mA CE = V IL, I I/O = 0 mA Min. Cycle, Duty = 100% ISB - 25 - 25 mA CE = V IH ISB1 Standby Power Supply Current - 8 - 8 mA CE ≥ VCC - 0.2V, V IN ≥ VCC -0.2V or V IN ≤ 0.2V V OL Output Low Voltage - 0.4 - 0.4 V IOL = 8 mA V OH Output High Voltage 2.4 - 2.4 - V IOH = -4 mA Notes: 1. V IL = -3.0V for pulses less than 20 ns. 2. ICC1 is dependent on output loading, cycle rates, and Read/Write patterns.

PRELIMINARY (July, 2000, Version 0.0) 4 AMIC Technology, Inc. Truth Table Mode CE OE WE I/O Operation Supply Current Standby H X X High Z ISB, I SB1 Output Disable L H H High Z ICC1 Read L L H D OUT ICC1 Write L X L D IN ICC1 Note: X = H or L Capacitance (T A = 25 °C, f = 1.0MHz) Symbol Parameter Min. Max. Unit Conditions C IN* Input Capacitance - 8 pF V IN = 0V C I/O* Input/Output Capacitance - 8 pF V I/O = 0V * These parameters are sampled and not 100% tested. AC Characteristics (T A = 0 °C to +70 °C, VCC = 5V ± 10%) Symbol Parameter A6173081-12 A6173081-15 Unit Min. Max. Min. Max. Read Cycle tRC Read Cycle Time 12 - 15 - ns tAA Address Access Time - 12 - 15 ns tACE Chip Enable Access Time - 12 - 15 ns tOE Output Enable to Output Valid - 6 - 8 ns tCLZ Chip Enable to Output in Low Z 3 - 3 - ns tOLZ Output Enable to Output in Low Z 0 - 0 - ns tCHZ Chip Disable Output in High Z 0 6 - 8 ns tOHZ Output Disable to Output in High Z 0 6 0 8 ns t OH Output Hold from Address Change 3 - 3 - ns

PRELIMINARY (July, 2000, Version 0.0) 5 AMIC Technology, Inc. AC Characteristics (continued) Symbol Parameter A6173081-12 A6173081-15 Unit Min. Max. Min. Max. Write Cycle tWC Write Cycle Time 12 - 15 - ns tCW Chip Enable to End of Write 10 - 12 - ns tAS Address Setup Time of Write 0 - 0 - ns tAW Address Valid to End of Write 10 - 12 - ns tWP Write Pulse Width 10 - 12 - ns tWR Write Recovery Time 0 - 0 - ns tWHZ Write to Output in High Z 0 6 0 8 ns tDW Data to Write Time Overlap 6 - 7 - ns tDH Data Hold from Write Time 0 - 0 - ns tOW Output Active from End of Write 3 - 3 - ns Notes: tCHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. Timing Waveforms Read Cycle 1(1) tRC Address D OUT tAA tOE tOLZ5 tACE tCLZ5 tCHZ5 tOH OE tOHZ5 CE

PRELIMINARY (July, 2000, Version 0.0) 6 AMIC Technology, Inc. Timing Waveforms (continued) Read Cycle 2(1, 2, 4) tRC tOH tAA tOH Address D OUT Read Cycle 3(1, 3, 4,) tCLZ5 tACE tCHZ5 D OUT CE Notes: 1. WE is high for Read Cycle. 2. Device is continuously enabled, CE = V IL. 3. Address valid prior to or coincident with CE transition low. 4. OE = V IL. 5. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested.

PRELIMINARY (July, 2000, Version 0.0) 7 AMIC Technology, Inc. Timing Waveforms (continued) Write Cycle 1(6) (Write Enable Controlled) tWC Address D IN tOW7 tDHtDW tWHZ7 tWP2tAS1 (4) tCW5 tAW tWR3 D OUT WE CE Write Cycle 2 (Chip Enable Controlled) tWC Address D IN tDW tWHZ7 tAW tWR3 D OUT tDH (4) tWP2 tCW5tAS1 CE WE Notes: 1. tAS is measured from the address valid to the beginning of Write. 2. A Write occurs during the overlap ( tWP) of a low CE and a low WE . 3. tWR is measured from the earliest of CE or WE going high to the end of the Write cycle 4. If the CE low transition occurs simultaneously with the WE low transition or after the WE transition, outputs remain in a high impedance state. 5. tCW is measured from the later of CE going low to the end of Write. 6. OE is continuously low. ( OE = V IL) 7. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested.

PRELIMINARY (July, 2000, Version 0.0) 8 AMIC Technology, Inc. Figure 1. Output Load Figure 2. Output Load for tCLZ, tOLZ,

PRELIMINARY (July, 2000, Version 0.0) 9 AMIC Technology, Inc. Low VCC Data Retention Waveform VCC CE tCDR V IH 4.5V tR V IH 4.5V DATA RETENTION MODE V DR ³ > 3.0V CE ³ > V DR - 0.2V

Ordering Information

Part No. Access Time (ns) Operating Current Max. (mA) CMOS Standby Max. (mA) Package A6173081S-12 32L 300mil SOJ A6173081SW-12 12 170 8 32L 400mil SOJ A6173081S-15 32L 300mil SOJ A6173081SW-15 15 165 8 32L 400mil SOJ

PRELIMINARY (July, 2000, Version 0.0) 10 AMIC Technology, Inc.

Package Information

SOJ 32L(300mil) Outline Dimensions unit: inches/mm Dimensions in inches Dimensions in mmSymbol Min Nom Max Min Nom Max Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension E 1 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash. A 1 A 2 A e E 2 C 1732 S Seating Plane D y b 1 b E 1 D Min 0.025" 0.004 E yy

PRELIMINARY (July, 2000, Version 0.0 ) 11 AMIC Technology, Inc. SOJ 32L (400mil) Outline Dimensions unit: inches/mm Dimensions in inches Dimensions in mmSymbol Min Nom Max Min Nom Max Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension E 1 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash. A 1 A 2 A e E 2 C 1732 S Seating Plane D y b 1 b E 1 D Min 0.025" 0.004 E yy θ