A615308 AMICC | Alldatasheet
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Preliminary 32K X 8 BIT HIGH SPEED CMOS SRAM PR ELIMINARY ( January , 200 1 , Version 0.0) AMIC Technology, Inc. Document Title 32K X 8 BIT HIGH SPEED CMOS SRAM
Revision History
Rev. No. History Issue Date Remark
0.0 Initial issue January 17, 2001
Preliminary 32K X 8 BIT HIGH SPEED CMOS SRAM PRELIMINARY ( January , 200 1 , Version 0.0) 1 AMIC Technology, Inc.
Features
n Access times: 12 ns (max.) n Current: Operating: 150mA (max.) Standby: 12mA (max.) n Fu ll static operation, no clock or refreshing required n All inputs and outputs are directly TTL compatible n Common I/O using three - state output n Data retention voltage: 2V (min.) n Available in 28 - pin SOJ and TSOP packages General Description The A615 308 is a high - speed 262,144 - bit static random access memory organized as 32,768 words by 8 bits and operates on a single 5V power supply. It is built using high performance CMOS process. Inputs and three - state outputs are TTL compatible and allow for direc t interfacing with common system bus structures. Minimum standby power is drawn by this device when CE is at a high level, independent of the other input levels. Data retention is guaranteed at a power supply voltage as low as 2V. Pin Configurations n SOJ nn TSOP A14 A12 I/O 0 I/O 1 I/O 2 GND I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CE OE A11 A13 WE VCC A10 A615308S 14 15 A615308V A11 2 A13 A14 A12 I/O 6 I/O 5 I/O 4 I/O 3 GND I/O 2 I/O 1 I/O 0 A10 VCC I/O 7 OE WE CE ~~~~
PRELIMINARY ( January , 200 1 , Version 0.0) 2 AMIC Technology, Inc. Block Diagram ROW DECODER
512 X 512
Pin No. Symbol Description 1 - 10, 21, 23 - 26 A0 - A14 Address Inputs 11 - 13, 15 - 19 I/O 0 - I/O 7 Data Inputs/Outputs
20 CE Chip Enable
22 OE Output Enable
27 WE Write Enable
28 VCC Power Supply
14 GND Ground
Pin No. Symbol Description 2 - 5, 8 - 17, 28 A0 - A14 Address Inputs 18 - 20, 22 - 26 I/O 0 - I/O 7 Data Inputs/Outputs
27 CE Chip Enable
1 OE Output Enable
6 WE Write Enable
7 VCC Power Supply
21 GND Ground
PRELIMINARY ( January , 200 1 , Version 0.0) 3 AMIC Technology, Inc. Recommended DC Operating Conditions (T A = 0 °C to + 70 °C) Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage 4.5 5.0 5.5 V GND Ground 0 0 0 V V IH Input High Voltage 2.2 3.5 VCC + 0.5 V V IL Input Low (1) Voltage - 0.5 0 +0.8 V C L Output Load - - 30 pF Absolute Maximum Ratings* *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Funct ional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device re liability. Symbol Parameter A615308-12 Unit Conditions Min. Max. ILI Input Leakage - 2 µA V IN = GND to VCC ILO Output Leakage - 2 µA CE = V IH or OE = V IH V I/O = GND to VCC ICC1 (2) Dynamic Operating Current - 150 mA CE = V IL, I I/O = 0 mA Min. Cycle, Duty = 100% ISB - 3 5 mA CE = V IH ISB1 Standby Power Supply Current mA CE ≥ VCC - 0.2V V IN ≥ VCC - 0.2V or V IN ≤ 0.2V V OL Output Low Voltage - 0.4 V IOL = 8 mA V OH Output High Voltage 2.4 - V IOH = - 4 mA Notes: 1. V IL = - 3.0V for pulses less than 20 ns. 2. ICC1 is dependent on output loading, cycle rates, and Read/Write patterns.
PRELIMINARY ( January , 200 1 , Version 0.0) 4 AMIC Technology, Inc. Truth Table Mode CE OE WE I/O Operation Supply Current Standby H X X High Z ISB, I SB1 Output Disable L H H High Z ICC1 Read L L H D OUT ICC1 Write L X L D IN ICC1 Note: X = H or L Capacitance (T A = 25 °C, f = 1.0MHz) Symbol Parameter Min. Max. Unit Conditions C IN* Input Capacitance - 10 pF V IN = 0V C I/O* Input/Output Capacit ance - 10 pF V I/O = 0V * These parameters are sampled and not 100% tested. AC Characteristics (T A = 0 °C to +70 °C, VCC = 5V ± 10%) Symbol Parameter A615308-12 Unit Min. Max. Read Cycle t RC Read Cycle Time 12 - ns t AA Address Access Time - 12 n s t ACE Chip Enable Access Time - 12 ns t OE Output Enable to Output Valid - 6 ns t CLZ Chip Enable to Output in Low Z 3 - ns t OLZ Output Enable to Output in Low Z 0 - ns t CHZ Chip Disable Output in High Z 0 6 ns t OHZ Output Disable to Outpu t in High Z 0 6 ns t OH Output Hold from Address Change 3 - ns
PRELIMINARY ( January , 200 1 , Version 0.0) 5 AMIC Technology, Inc. AC Characteristics (continued) Symbol Parameter A615308-12 Unit Min. Max. Write Cycle tWC Write Cycle Time 12 - ns tCW Chip Enable to End of Write 10 - ns tAS Address Setup Time of Write 0 - ns tAW Address Valid to End of Write 10 - ns tWP Write Pulse Width 10 - ns tWR Write Recovery Time 0 - ns tWHZ Write to Output in High Z 0 6 ns tDW Data to Write Time Overlap 6 - ns tDH Data Hold from Write Time 0 - ns tOW Output Active f rom End of Write 3 - ns Notes: tCHZ, t OHZ and t WHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levles. Timing Waveforms Read Cycle 1(1) tRC Address D OUT tAA tOE tOLZ5 tACE tCLZ5 tCHZ5 tOH OE tOHZ5 CE
PRELIMINARY ( January , 200 1 , Version 0.0) 6 AMIC Technology, Inc. Timing Waveforms (continued) Read Cycle 2(1, 2, 4) tRC tOH tAA tOH Address D OUT Read Cycle 3(1, 3, 4,) tCLZ5 tACE tCHZ5 D OUT CE Notes: 1. WE is high for Read Cycle. 2. Device is continuously enabled, CE = V IL. 3. Address valid prior to or coincident with CE transition low. 4. OE = V IL. 5. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested.
PRELIMINARY ( January , 200 1 , Version 0.0) 7 AMIC Technology, Inc. Timing Waveforms (continued) Write Cycle 1(6) (Write Enable Controlled) tWC Address D IN tOW7 tDHtDW tWHZ7 tWP2tAS1 (4) tCW5 tAW tWR3 D OUT WE CE Write Cycle 2 (Chip Enable Controlled) tWC Address D IN tDW tWHZ7 tAW tWR3 D OUT tDH (4) tWP2 tCW5tAS1 CE WE Notes: 1. t AS is measured from the address valid to the beginning of Write. 2. A Write occurs during the overlap ( tWP) of a low CE and a low WE . 3. t WR is measured from the earliest of CE or WE going high to the end of the Write cycle 4. If the CE low transitio n occurs simultaneously with the WE low transition or after the WE transition, outputs remain in a high impedance state. 5. t CW is measured from the later of CE going low to the end of Wr ite. 6. OE is continuously low. ( OE = V IL) 7. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested.
PRELIMINARY ( January , 200 1 , Version 0.0) 8 AMIC Technology, Inc. Figure 1. Output Load Figure 2. Output Load for tCLZ, tOLZ,
PRELIMINARY ( January , 200 1 , Version 0.0) 9 AMIC Technology, Inc. Low VCC Data Retention Waveform VCC tCDR V IH 4.5V tR V IH 4.5V DATA RETENTION MODE V DR ≥ 2.0V CE ≥ V DR - 0.2V CE
Ordering Information
Part No. Access Time (ns) Operating Current Max. (mA) Standby Current Max. (mA) Package A615308S - 12 12 150 12 28L SOJ A615308V - 12 12 150 12 28L TSOP
PRELIMINARY ( January , 200 1 , Version 0.0) 10 AMIC Technology, Inc.
Package Information
SOJ 28L Outline Dimensions unit: inches/mm E H E A 1 A 2 A e e 1 C 1528 S D Seating Plane D y L b 1 b Dimensions in inches Dimensions in mm Symbol Min Nom Max Min Nom Max b 1 0.028 TYP 0.71 TYP b 0.018 TYP 0.46 TYP C 0.010 TYP 0.25 TYP D - 0.710 0.730 - 18.03 18.54 e 0.050 BSC 1.27 BSC Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension e 1 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash.
PRELIMINARY ( January , 200 1 , Version 0.0) 11 AMIC Technology, Inc. TSOP 28L TYPE I (8 X 13.4mm) Outline Dimensions unit: inches/mm Dimensions in inches Dimensions in mm Symbol Min Nom Max Min Nom Max c 0.005 - 0.008 0.12 - 0.21 e 0.022 BSC 0.55 BSC S 0.017 TYP 0.425 TYP Notes: 1. The maximum value of dimension D 1 includes end flash. 2. Dimensi on E does not include resin fins. 3. Dimension S includes end flash. D 1 E e D L A A 2 c Detail "A" D y Detail "A" S A 1 b θ