A422604 AMICC | Alldatasheet

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4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE (March, 2009, Version 1.0) AMIC Technology, Corp. Document Title 4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE

Revision History

Rev. No. History Issue Date Remark

0.0 Initial issue July 23, 2003

1.0 Remove 24/26-pin TSOP type II package March 26, 2009 Final

4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE (March, 2009, Version 1.0) 1 AMIC Technology, Corp.

Features

„ Organization: 4,194,304 words X 4 bits „ Part Identification - A422604 (2K Ref.) „ Single 5.0V power supply/built-in VBB generator „ Low power consumption - Operating: 120mA (-50 max) - Standby: 1.0mA (TTL), 0.5mA (CMOS), 0.5mA (Self-refresh current) „ High speed - 50/60 ns RAS access time - 22/27 ns column address access time - 13/15 ns CAS access time - 20/24 ns EDO Page Mode Cycle Time „ Fast Page Mode with Extended Data Out „ 2K Refresh Cycle in 32ms „ Read-modify-write, RAS -only, CAS -before- RAS , Hidden refresh capability „ TTL-compatible, three-state I/O „ JEDEC standard packages - 300mil, 24/26-pin SOJ General Description The A422604 is a new generation randomly accessed memory for graphics, organized in a 4,194,304-word by 4- bit configuration. This product can execute Write and Read operation via CAS pin. The A422604 offers an accelerated Fast Page Mode cycle with a feature called Extended Data Out (EDO). Pin Configuration „ SOJ VCC I/O0 I/O1 CAS I/O2 I/O3 VSS A422604SOE WE RAS A10 VCC NC VSS This allow random access of up to 2048(2K Ref.) words within a row at a 50/42 MHz EDO cycle, making the A422604 ideally suited for graphics, digital signal processing and high performance computing systems. Pin Descriptions Symbol Description A0 - A10 Address Inputs (2K product) I/O0 - I/O3 Data Input/Output RAS Row Address Strobe CAS Column Address Strobe WE Write Enable OE Output Enable VCC 5.0V Power Supply VSS Ground NC No Connection

(March, 2009, Version 1.0) 2 AMIC Technology, Corp. Selection Guide Symbol Description -50 -60 Unit tRAC Maximum RAS Access Time 50 60 ns tAA Maximum Column Address Access Time 22 27 ns tCAC Maximum CAS Access Time 13 15 ns tOEA Maximum Output Enable ( OE ) Access Time 13 15 ns tRC Minimum Read or Write Cycle Time 84 100 ns tPC Minimum EDO Cycle Time 20 24 ns Functional Description The A422604 reads and writes dat a by multiplexing an 22-bit address into a 11-bit(2K) row and column address. RAS and CAS are used to strobe the row address and the column address, respectively. A Read cycle is performed by holding the WE signal high during RAS / CAS operation. A Write cycle is executed by holding the WE signal low during RAS /CAS operation; the input data is latched by the falling edge of WE or CAS , whichever occurs later. The data inputs and outputs are routed through 4 common I/O pins, with RAS , CAS , WE and OE controlling the in direction. EDO Page Mode operation all 2048(2K) columns within a selected row to be randomly accessed at a high data rate. A EDO Page Mode cycle is initiated with a row address latched by RAS followed by a column address latched by CAS . While holding RAS low, CAS can be toggled to strobe changing column addresses, thus achieving shorter cycle times. The A422604 offers an accelerated Fast Page Mode cycle through a feature called Extended Data Out, which keeps the output drivers on during the CAS precharge time (tcp). Since data can be output after CAS goes high, the user is not required to wait for valid dat a to appear before starting the next access cycle. Data-out will remain valid as long as RAS and OE are low, and WE is high; this is the only characteristic which differentiates Extended Data Out operation from a standard Read or Fast Page Read. A memory cycle is terminated by returning both RAS and CAS high. Memory cell data will retain its correct state by maintaining power and accessing all 2048(2K) combinations of the 11-bit(2K) row addresses, regardless of sequence, at least once every 32ms through any RAS cycle (Read, Write) or RAS Refresh cycle ( RAS -only, CBR, or Hidden). The CBR Refresh cycle automatically controls the row addresses by invoking the refresh counter and controller. Power-On The initial application of t he VCC supply requires a 200 µs wait followed by a minimum of any eight initialization cycles containing a RAS clock. During Power-On, the VCC current is dependent on the input levels of RAS and CAS . It is recommended that RAS and CAS track with VCC or be held at a valid VIH during Power-On to avoid current surges.

(March, 2009, Version 1.0) 3 AMIC Technology, Corp. Block Diagram Recommended Operating Conditions (Ta = 0°C to +70°C) Symbol Description Min. Typ. Max. Unit VCC Power Supply 4.5 5.0 5.5 V VSS Input High Volt age 0.0 0.0 0.0 V VIH Input High Voltage 2.4 - VCC + 1.0 V VIL Input Low Voltage -0.5 - 0.8 V Control Clocks VBB Generator Refresh Timer Refresh control Refresh Counter Row Address Buffer Col. Address Buffer Row Decoder Column Decoder Memory Array 4,194,304 X 4 Cells Sense Amps & I/O Data in Buffer Data out Buffer Vcc Vss RAS CAS WE A0~A10 A0~A10 I/O0 to I/O3 OE

(March, 2009, Version 1.0) 4 AMIC Technology, Corp. Truth Table Function RAS CAS WE OE Address I/Os Standby H H X X X High-Z Read: Word L L H L Row/Col. Data Out Read L L H L Row/Col. Data Out Write: Word (Early) L L L X Row/Col. Data In Write (Early) L L L X Row/Col. Data In Read-Write L L H→L L →H Row/Col. Data Out → Data In EDO-Page-Mode Read: Hi-Z -First cycle -Subsequent Cycles L L H→L H→L H H H→L H→L Row/Col. Col. Data Out Data Out EDO-Page-Mode Write(Early) -First cycle -Subsequent Cycles L L H→L H→L L L X X Row/Col. Col. Data In Data In EDO-Page-Mode Read-Write -First cycle -Subsequent Cycles L L H→L H→L H→L H→L L→H L→H Row/Col. Col. Data Out → Data In Data Out → Data In Hidden Refresh Read L→H→L L H L Row/Col. Data Out Hidden Refresh Write L→H→L L L X Row/Col. Data In → High-Z RAS -Only Refresh L H X X Row High-Z CBR Refresh H→L L X X X High-Z Self Refresh H→L L H X X High-Z

(March, 2009, Version 1.0) 5 AMIC Technology, Corp. Absolute Maximum Ratings* *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operat ional sections of these specification is not impli ed or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. -50 -60 Symbol Parameter Min. Max. Min. Max. Unit Test Conditions Notes IIL Input Leakage Current -5 +5 -5 +5 μA 0V ≤ Vin ≤ Vin + 0.2V Pins not under Test = 0V IOL Output Leakage Current -5 +5 -5 +5 μA DOUT disabled, 0V ≤ Vout ≤ + VCC ICC1 Operating Power Supply Current - 120 - 115 mA RAS ,UCAS ,LCAS Address cycling; tRC = min. 1, 2 ICC2 TTL Standby Power Supply Current - 1.0 - 1.0 mA RAS =UCAS =LCAS=VIH ICC3 Average Power Supply Current, RAS Refresh Mode - 120 - 115 mA RAS cycling, UCAS =LCAS = VIH, tRC = min. ICC4 EDO Page Mode Average Power Supply Current - 90 - 85 mA RAS = VIL, UCAS ,LCAS Address cycling; tPC = min. 1, 2 ICC5 CAS -before-RAS Refresh Power Supply Current - 120 - 115 mA RAS , UCAS , LCAS cycling; tRC = min. ICC6 CMOS Standby Power Supply Current - 0.5 - 0.5 mA RAS =UCAS =LCAS = VCC - 0.2V ICC7 Self Refresh Mode Current - 0.5 - 0.5 mA RAS = CAS ≤ VSS+0.2V All other input high levels are VCC-0.2V or input low levels are VSS +0.2V VOH 2.4 - 2.4 - V I OUT = -5.0mA VOL Output Voltage - 0.4 - 0.4 V I OUT = 4.2mA

(March, 2009, Version 1.0) 6 AMIC Technology, Corp. AC Characteristics (VCC = 5.0V ±10%, VSS = 0V, Ta = 0°C to +70°C) Test Conditions: Input timing reference level: VIH/VIL=2.4V/0.8V Output reference level: VOH/VOL=2.0V/0.8V Output Load: 2TTL gate + CL (50pF) Assumed t T=2ns -50 -60 Std Symbol Parameter Min. Max. Min. Max. Unit Notes t T Transition Time (Rise and Fall) 1 50 1 50 ns 4, 5 1 t RC Random Read or Write Cycle Time 84 - 100 - ns 2 t RP RAS Precharge Time 30 - 36 - ns 3 t RAS RAS Pulse Width 50 10K 60 10K ns 4 t CAS CAS Pulse Width 8 10K 10 10K ns 5 t RCD RAS to CAS Delay Time 11 37 13 45 ns 6 6 t RAD RAS to Column Address Delay Time 9 28 11 33 ns 7 7 t RSH CAS to RAS Hold Time 8 - 10 - ns 8 t CSH CAS Hold Time 37 - 41 - ns 9 t CRP CAS to RAS Precharge Time 5 - 5 - ns 10 t ASR Row Address Setup Time 0 - 0 - ns 11 t RAH Row Address Hold Time 8 - 10 - ns 12 t CLZ CAS to Output in Low Z 3 - 3 - ns 8 13 t RAC Access Time from RAS - 50 - 60 ns 6,7 14 t CAC Access Time from CAS - 13 - 15 ns 6, 12 15 t AA Access Time from Column Address - 22 - 27 ns 7, 12 16 t OEA Access Time from OE - 13 - 15 ns 17 t AR Column Address Hold Time from RAS 45 - 55 - ns 18 t RCS Read Command Setup Time 0 - 0 - ns 19 t RCH Read Command Hold Time 0 - 0 - ns 9 20 t RRH Read Command Hold Time Reference to RAS 0 - 0 - ns 9

(March, 2009, Version 1.0) 7 AMIC Technology, Corp. AC Characteristics (continued) (VCC = 5.0V ±10%, VSS = 0V, Ta = 0°C to +70°C) Test Conditions: Input timing reference level: VIH/VIL=2.4V/0.8V Output reference level: VOH/VOL=2.0V/0.8V Output Load: 2TTL gate + CL (50pF) Assumed t T=2ns -50 -60 Std Symbol Parameter Min. Max. Min. Max. Unit Notes 21 t RAL Column Address to RAS Lead Time 22 - 27 - ns 22 t COH Output Hold After CAS Low 3 - 4 - ns 23 t OFF Output Buffer Turn-Off Delay Time - 3 - 5 ns 8, 10 24 t ASC Column Address Setup Time 0 - 0 - ns 25 t CAH Column Address Hold Time 8 - 10 - ns 26 t OES OE Low to CAS High Set Up 10 - 10 - ns 27 t WCS Write Command Setup Time 0 - 0 - ns 11 28 t WCH Write Command Hold Time 8 - 10 - ns 11 29 t WCR Write Command Hold Time to RAS 45 - 55 - ns 30 t WP Write Command Pulse Width 8 - 10 - ns 31 t RWL Write Command to RAS Lead Time 13 - 15 - ns 32 t CWL Write Command to CAS Lead Time 8 - 10 - ns 33 t DS Data-in setup Time 0 - 0 - ns 34 t DH Data-in Hold Time 8 - 10 - ns 35 t DHR Data-in Hold Time to RAS 45 - 55 - ns 36 t RWC Read-Modify-Write Cycle Time 114 - 135 - ns 37 t RWD RAS to WE Delay Time (Read-Modify-Write) 65 - 78 - ns 11 38 t CWD CAS to WE Delay Time (Read-Modify-Write) 28 - 33 - ns 11 39 t AWD Column Address to WE Delay Time (Read-Modify-Write) 37 - 45 - ns 11 40 t OEH OE Hold Time from WE 8 - 10 - ns

(March, 2009, Version 1.0) 8 AMIC Technology, Corp. AC Characteristics (continued) (VCC = 5.0V ± 10%, VSS = 0V, Ta = 0°C to +70°C) Test Conditions: Input timing reference level: VIH/VIL=2.4V/0.8V Output reference level: VOH/VOL=2.0V/0.8V Output Load: 2TTL gate + CL (50pF) Assumed t T=2ns -50 -60 Std Symbol Parameter Min. Max. Min. Max. Unit Notes 41 t OEP OE High Pulse Width 5 - 5 - ns 42 t PC Read or Write Cycle Time (EDO Page) 20 - 24 - ns 13 43 t CPA Access Time from CAS Precharge (EDO Page) - 23 - 27 ns 12 44 t CP CAS Precharge Time (EDO Page) 8 - 10 - ns 45 t PCM EDO Page Mode RMW Cycle Time 50 - 59 - ns 46 t CRW EDO Page Mode CAS Pulse Width (RMW) 38 - 45 - ns 47 t RASP RAS Pulse Width (EDO Page) 50 100K 60 100K ns 48 t CSR CAS Setup Time ( CAS -before-RAS ) 5 - 5 - ns 3 49 t CHR CAS Hold Time ( CAS -before-RAS ) 10 - 10 - ns 3 50 t RPC RAS to CAS Precharge Time ( CAS -before-RAS ) 5 - 5 - ns 51 t OEZ Output Buffer Turn-off Delay from OE - 3 - 5 ns 8 52 t RASS RAS pulse width (C -B-R self-refresh) 100 - 100 - μs 53 t RPS RAS precharge time (C -B-R self-refresh) 84 - 100 - ns 54 t CHS CAS hold time (C -B-R self-refresh) -50 - -50 - ns

(March, 2009, Version 1.0) 9 AMIC Technology, Corp. Notes: 1. I CC1, ICC3, ICC4, and ICC5 depend on cycle rate. 2. I CC1 and ICC4 depend on output loading. Specified values are obtained with the outputs open. 3. An initial pause of 200 μs is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal refresh counter, a minimum of 8 CAS -before-RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after extended periods of bias without. 4. AC Characteristics assume t T = 2ns. All AC parameters are measured wi th a load equivalent to two TTL load and 50pF, V IL (min.) ≥ GND and VIH (max.) ≤ VCC. 5. V IH (min.) and V IL (max.) are reference levels for measuring timi ng of input signals. Transition times are measured between V IH and VIL. point only. If t RCD is greater than the specified tRCD (max.) limit, then access time is controlled exclusively by tCAC. point only. If t RAD is greater than the specified tRAD (max.) limit, then access time is controlled exclusively by tAA. 8. Assumes three state test load (5pF and a 500 Ω Thevenin equivalent). 9. Either t RCH or tRRH must be satisfied for a read cycle. 10. t OFF (max.) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels. 11. t WCS, t WCH, t RWD, t CWD and t AWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If t WCS ≥ t WCS (min.) and t WCH ≥ t WCH (min.), the cycle is an early write cycle and data-out pins will remain open circuit, hi gh impedance, throughout t he entire cycle. If t RWD ≥ t RWD (min.) , t CWD ≥ t CWD (min.) and t AWD ≥ t AWD (min.), the cycle is a read-modify-write cy cle and the data out will c ontain data read from the selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate. 12. Access time is determined by the longer of t AA or tCAC or tCPA. 13. t ASC ≥ tCP to achieve tPC (min.) and tCPA (max.) values.

(March, 2009, Version 1.0) 10 AMIC Technology, Corp. Word Read Cycle tRAS(3) tRP(2) tRC(1) tCRP(9) tCSH(8) tRCD(5) tRSH(7) tCAS(4) tASR(10) tCRP(9) tRAH(11) tASC(24) tCAH(25) tRAD(6) tRAL(21) tRCH(19) tRRH(20) tAR(17) tRCS(18) tOEA(16) tRAC(13) tAA(15) tCAC(14) tCLZ(12) tOEZ(51) tOFF(23) High-Z : High or Low Valid Data-out Row Address Column Address I/O0 ~ I/O3 OE WE Address CAS RAS

(March, 2009, Version 1.0) 11 AMIC Technology, Corp. Word Write Cycle (Early Write) tRAS(3) tRP(2) tRC(1) tCRP(9) tCSH(8) tRCD(5) tRSH(7) tCAS(4) tASR(10) tCRP(9) tRAH(11) tASC(24) tCAH(25) tRAD(6) tRAL(21) tWCH(28) : High or Low Row Address Column Address I/O0 ~ I/O3 OE Address CAS RAS tAR(17) tCWL(32) tRWL(31) tWP(30) tWCS(27) Valid Data-in tDS(33) tDH(34) WE tWCR(29) tDHR(35)

(March, 2009, Version 1.0) 12 AMIC Technology, Corp. Word Write Cycle (Late Write) tRAS(3) tRP(2) tRC(1) tCRP(9) tCSH(8) tRCD(5) tRSH(7) tCAS(4) tASR(10) tCRP(9) tASC(24) tCAH(25) tRAD(6) tRAL(21) Row Address Column AddressAddress CAS RAS tAR(17) tCWL(32) tRWL(31) tWP(30) tRAH(11) tOEH(40) tDS(33) tDH(34) I/O0 ~ I/O3 : High or Low OE WE High-Z Vaild Data-in tWCR(29) tDHR(35)

(March, 2009, Version 1.0) 13 AMIC Technology, Corp. Word Read-Modify-Write Cycle tRAS(3) tRP(2) tRWC(36) tCRP(9) tCSH(8) tRCD(5) tRSH(7) tASR(10) tCRP(9) tRAH(11) tCAH(25) tRAD(6) Row Address Column AddressAddress CAS RAS tAR(17) tRWL(31) tASC(24) tCWL(32) tAWD(39) tCWD38) tRWD(37) tWP(30) tOEA(16) tOEZ(51) tCLZ(12) tCAC(14) tAA(15) tRAC(13) tDS(33) tDH(34) High-Z Data-out Data-in : High or Low I/O0 ~ I/O3 OE WE tOEH(40) tRCS(18)

(March, 2009, Version 1.0) 14 AMIC Technology, Corp. EDO Page Mode Word Read Cycle tRASP(47) tRP(2) RAS CAS tCAS(4)tCAS(4)tCAS(4) tRCD(5) tCSH(8) tCRP(9) tCRP(9) tPC(42) tRSH(7) tASR(10) tRAH(11) tRAD(6) tAR(16) tRAL(21) Address OE WE I/O0 ~ I/O3 : High or Low tASC(24) tCP(44) tCSH(8) tASC(24) tCAH(25) tCAH(25) Row Column Column Column tRCH(19)tRCS(18)tRCS(18) tRCH(25) tRCS(18) tCAH(25) tRRH(20) tOFF(23) tOEZ(51) tAA(15) tOEA(16) tOEP(41) tCAC(14) tCLZ(12) tOEZ(51) tCPA(43) tOES(26) tAA(15) tOEA(16) tCOH(22) tCAC(14)tRAC(13) tCAC(14) tCLZ(12) Data-out Data-out Data-out

(March, 2009, Version 1.0) 15 AMIC Technology, Corp. EDO Page Mode Early Word Write Cycle tRASP(47) tRP(2) RAS CAS tCAS(4)tCP(44)tCAS(4)tCP(44)tCAS(4) tRCD(5) tCSH(8) tCRP(9) tCRP(9) tPC(42) tRSH(7) tASR(10) tRAH(11) tRAD(6) tASC(24) tCAH(25) tASC(24) tCAH(25) tCAH(25) tASC(24) tRAL(21) Row Column ColumnAddress WE tCWL(32) tWCH(28) tWCS(27) tWCS(27) Column tCWL(32) tWCH(28) tWCS(27) tWCH(28) tCWL(32) tRWL(31) tWP(30) tWP(30) tWP(30) tDH(34) tDS(33) tDH(34) tDS(33) tDS(33) tDH(34) Data-in Data-in Data-in I/O0 ~ I/O3 OE : High or Low

(March, 2009, Version 1.0) 16 AMIC Technology, Corp. EDO Page Mode Word Read-Modify-Write Cycle tRASP(47) RAS tCRW(46)tCP(44)tCRW(46)tCP(44)tCRW(46) tRCD(5) tCSH(8) tCRP(9) tCRP(9) tPCM(45) tRSH(7) tRP(2) tASR(10) tRAH(11) tRAD(6) tASC(24) tCAH(25) tASC(24) tCAH(25) tASC(24) tCAH(25) tRAL(21) tRCS(18) tCWD(38) tRWD(37) tCWL(32) tCWD(38) tCWL(32) tCWD(38) tCWL(32) tRWL(31) tOEA(16) tOEA(16) tOEA(16) tWP(30) tWP(30) tWP(30) tAWD(39) tAWD(39) tAWD(39) tCAC(14) tAA(15) tRAC(13) tOEZ(51) tDS(33) tAA(15) tCPA(43) tDH(34) tOEZ(51) tDS(33) tDH(34) tOEZ(51) tDS(33) tDH(34) tAA(15) tCPA(43) tCLZ(12) tCLZ(12) tCLZ(12) High-Z : High or Low I/O0 ~ I/O3 OE WE Address CAS Data-out Data-in Data-out Data-in Data-out Data-in Row Column Column Column tOEH(40)

(March, 2009, Version 1.0) 17 AMIC Technology, Corp. RAS Only Refresh Cycle CAS Before RAS Refresh Cycle tRAS(3) tRP(2) tRC(1) RAS tCRP(9) tRPC(50) tASR(10) tRAH(11) Address : High or Low Row Note: WE, OE = Don't care. CAS tRAS(3) tRP(2) tRC(1) RAS tRP(2) tRPC(50) tPC(44) tCSR(48) tCHR(49) tOFF(23) I/O0 ~ I/O3 CAS High-Z : High or LowNote: WE, OE, Address = Don't care.

(March, 2009, Version 1.0) 18 AMIC Technology, Corp. Hidden Refresh Cycle (Word Read) tRAS(3) tRP(2) tRC(1) tCRP(9) tAR(17) tRCD(5) tASR(10) tCRP(9) tASC(24) tCAH(25) tRAD(6) A0~A8 UCAS RAS tRAH(11) tRRH(20)tRCS(18) I/O0 ~ I/O15 : High or Low OE High-Z tRAS(3) tRP(2) tCHR(49) tRC(1) tRSH(7) tRAL(21) tCAC(14) tOFF(23) tAA(15) tCLZ(12) tRAC(13) WE Row Column Valid Data-out LCAS tOEZ(51) tOEA(16)

(March, 2009, Version 1.0) 19 AMIC Technology, Corp. Hidden Refresh Cycle (Early Word Write) tRAS(3) tRP(2) tRC(1) tCRP(9) tAR(17) tRCD(5) tASR(10) tCRP(9) tASC(24) tCAH(25) tRAD(6) Address RAS tRAH(11) : High or Low OE tRAS(3) tRP(2) tCHR(49) tRC(1) tRSH(7) tRAL(21) WE Row Column tWCS(27) tWCH(28) tWP(30) tDS(33) tDH(34) Valid Data-in I/O0 ~ I/O3 CAS

(March, 2009, Version 1.0) 20 AMIC Technology, Corp. EDO Page Mode Read-Early-Write Cycle (Pseudo Read-Modify-Write) RAS : High or Low I/O0 ~ I/O3 OE WE Address CAS tRP(2)tRASP(47) tCRP(9) tCSH(8) tRCD(5) tCAS(4) tCP(44) tCAS(4) tCP(44) tCAS(4) tCPR(9) tRSH(7)tPC(42)tPC(42) Row Column Column tRAL(21) tCAH(25)tASC(24)tCAH(25)tASC(24) tCAH(25)tASC(24) tASR(10) tRAH(11) tRAD(6) Column tRCS(18) tRCH(19) tWCS(27) tWCH(28) Data-out Data-out Data-in tDH(34) tDS(33) tAA(15) tCAP(43) tCAC(14) tCOH(22) tAA(15) tRAC(13) tCAC(14) tOEA(16)

(March, 2009, Version 1.0) 21 AMIC Technology, Corp. Self Refresh Mode „ Self Refresh Mode. a. Entering the Self Refresh Mode: The A422604 Self Refresh Mode is entered by using CAS before RAS cycle and holding RAS and CAS signal "low" longer than 100μs. b. Continuing the Self Refresh Mode: The Self Refresh Mode is continued by holding RAS "low" after entering the Self Refresh Mode. It does not depend on CAS being "high" or "low" after entering the Self Refresh Mode continue the Self Refresh Mode. c. Exiting the Self Refresh Mode: The A422604 exits the Self Refresh Mode when the RAS signal is brought "high". tRASS(52)tRP(2) tCRP(9)tCSR(48)tRPC(50) RAS tRPS(53) tCHS(54) tASR(10) tCP(44) tOFF(23) A0 ~ A10 : High or Low High-Z I/O0 ~ I/O3 UCAS LCAS ROW COL Note: WE, OE = Don't care.

(March, 2009, Version 1.0) 22 AMIC Technology, Corp. Capacitance (Ta = Room Temperature, VCC = 5.0V ± 10%) Symbol Signals Parameter Max. Unit Test Conditions CIN1 A0 - A10 5 pF Vin = 0V CIN2 RAS , CAS, WE , OE Input Capacitance 7 pF Vin = 0V CI/O I/O 0 - I/O3 I/O Capacitance 10 pF Vin = Vout = 0V Ordering Codes Package RAS Access Time 60ns Refresh Cycle Self-Refresh SOJ 24/26L (300mil) A422604S-60 2K Yes

(March, 2009, Version 1.0) 23 AMIC Technology, Corp.

Package Information

SOJ 24/26L (300mil) Outline Dimensions unit: inches/mm E e 1324 S y b 19 18 16 7 Pin 1 Identifier - y - Seating Plane 0.004 A A A θ D C Dimensions in inches Dimensions in mm Symbol Min Nom Max Min Nom Max D - 0.675 0.686 - 17.15 17.42 Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E1 does not include resin fins. 3. Dimension E2 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash.