A400DT90VF

AM29SL400D AMD | Alldatasheet

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The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig- inally developed the specification, these products will be offered to customers of both AMD and Fujitsu. Continuity of Specifications There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary. Continuity of Ordering Part Numbers AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions. Am29SL400D Data Sheet Publication Number Am29SL400D Revision A Amendment +1 Issue Date April 13, 2005

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This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. Pubication Am29SL400D Revision A Amendment +1 Issue Date: April 13, 2005 Visit www.amd.com for the latest information. Am29SL400D 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 1.8 Volt-only Super Low Voltage Flash Memory DISTINCTIVE CHARACTERISTICS ■ Single power supply operation — 1.65 to 1.95 V for read, program, and erase operations — Ideal for battery-powered applications ■ Manufactured on 0.23 µm process technology ■ High performance — Access times as fast as 90 ns ■ Ultra low power consumption (typical values at

5 MHz)

— 0.2 µA Automatic Sleep Mode current — 0.2 µA standby mode current — 5 mA read current — 15 mA program/erase current ■ Flexible sector architecture — One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and seven 64 Kbyte sectors (byte mode) — One 8 Kword, two 4 Kword, one 16 Kword, and seven 32 Kword sectors (word mode) — Supports full chip erase — Sector Protection features: A hardware method of locking a sector to prevent any program or erase operations within that sector Sectors can be locked in-system or via programming equipment Temporary Sector Unprotect feature allows code changes in previously locked sectors ■ Unlock Bypass Program Command — Reduces overall programming time when issuing multiple program command sequences ■ Top or bottom boot block configurations available ■ Minimum 1,000,000 erase cycle guarantee per sector ■ 20-year data retention at 125 ■ Package option — 48-ball FBGA ■ Compatibility with JEDEC standards — Pinout and software compatible with single-power supply Flash — Superior inadvertent write protection ■ Data# Polling and toggle bits — Provides a software method of detecting program or erase operation completion ■ Ready/Busy# pin (RY/BY#) — Provides a hardware method of detecting program or erase cycle completion ■ Erase Suspend/Erase Resume — Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation ■ Hardware reset pin (RESET#) — Hardware method to reset the device to reading array data

2 Am29SL400D Rev. A Amend. +1 April 13, 2005 ADVANCE INFORMATION GENERAL DESCRIPTION The Am29SL400D is an 4Mbit, 1.8 V volt-only Flash memory organized as 524,288 bytes or 262,144 words. The device is offered in a 48-ball FBGA package. The word-wide data (x16) appears on DQ15–DQ0; the byte-wide (x8) data appears on DQ7–DQ0. This device is designed to be programmed and erased in-system with a single 1.8 volt V CC supply. No VPP is required for write or erase operations. The device can also be pro- grammed in standard EPROM programmers. The standard device offers access times of 90, 100, and 120 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. The device requires only a single 1.8 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard . Com- mands are written to the command register using stan- dard microprocessor write timings. Register contents serve as input to an internal state-machine that con- trols the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that auto- matically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facili- tates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm—an internal algorithm that automati- cally preprograms the array (if it is not already pro- grammed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low V CC detector that automatically inhibits write opera- tions during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved in-system or via pro- gramming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode . The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes. AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection.

4 Am29SL400D Rev. A Amend. +1 April 13, 2005 ADVANCE INFORMATION PRODUCT SELECTOR GUIDE Note: See “AC Characteristics” for full specifications. BLOCK DIAGRAM Family Part Number Am29SL400D Speed Options Standard Voltage Range V CC = 1.65–1.95 V 90 100 120 Max access time, ns (tACC) 90 100 120 Max CE# access time, ns (tCE) 90 100 120 Max OE# access time, ns (tOE)3 0 3 5 5 0 Input/Output Buffers X-Decoder Y-Decoder Chip Enable Output Enable Logic Erase Voltage Generator PGM Voltage Generator TimerVCC Detector State Control Command Register VCC VSS WE# BYTE# CE# OE# STB STB DQ0–DQ15 (A-1) Sector Switches RY/BY# RESET# Data Latch Y-Gating Cell Matrix Address LatchA0–A17

April 13, 2005 Rev. A Amend. +1 Am29SL400D 5 ADVANCE INFORMATION CONNECTION DIAGRAM Special Handling Instructions for FBGA Packages Special handling is required for Flash Memory products in molded packages (TSOP , BGA, PLCC, PDIP , SSOP). The package and/or data integrity may be compromised if the package body is exposed to tem- peratures about 150 °C for prolonged periods of time. A1 B1 C1 D1 E1 F1 G1 H1 A2 B2 C2 D2 E2 F2 G2 H2 A3 B3 C3 D3 E3 F3 G3 H3 A4 B4 C4 D4 E4 F4 G4 H4 A5 B5 C5 D5 E5 F5 G5 H5 A6 B6 C6 D6 E6 F6 G6 H6 DQ15/A-1 V SSBYTE#A16A15A14A12A13 DQ13 DQ6DQ14DQ7A11A10A8A9 VCC DQ4DQ12DQ5NCNCRESET#WE# DQ11 DQ3DQ10DQ2NCNCNCRY/BY# DQ9 DQ1DQ8DQ0A5A6A17A7 OE# V SSCE#A0A1A2A4A3 48-Ball FBGA (T op View, Balls Facing Down)

6 Am29SL400D Rev. A Amend. +1 April 13, 2005 ADVANCE INFORMATION PIN CONFIGURATION A0–A17 = 18 addresses DQ0–DQ14 = 15 data inputs/outputs DQ15/A-1 = DQ15 (data input/output, word mode), A-1 (LSB address input, byte mode) BYTE# = Selects 8-bit or 16-bit mode CE# = Chip enable OE# = Output enable WE# = Write enable RESET# = Hardware reset pin, active low RY/BY# = Ready/Busy# output VCC = 1.65–1.95 V single power supply VSS = Device ground NC = Pin not connected internally LOGIC SYMBOL 16 or 8 DQ0–DQ15 (A-1) A0–A17 CE# OE# WE# RESET# BYTE# RY/BY#

April 13, 2005 Rev. A Amend. +1 Am29SL400D 7 ADVANCE INFORMATION

ORDERING INFORMATION

AMD standard products are available in several packages and operating ranges. The order number (Valid Combi- nation) is formed by a combination of the elements below. Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combi- nations. Am29SL400D T 90 E C TEMPERATURE RANGE C = Commercial (0°C to +70°C) D = Commercial (0°C to +70°C) with Pb-free Package I = Industrial (–40 °C to +85°C) F = Industrial (–40 °C to +85°C) with Pb-free Package PACKAGE TYPE WA = 48-Ball Fine-Pitch Ball Grid Array (FBGA) 0.80 mm pitch, 6 x 8 mm package (FBA048) SPEED OPTION See Product Selector Guide and Valid Combinations BOOT CODE SECTOR ARCHITECTURE T = Top Sector B = Bottom Sector DEVICE NUMBER/DESCRIPTION Am29SL400D

4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS Flash Memory

1.8 Volt-only Read, Program, and Erase

Valid Combinations for FBGA Packages Order Number Package Marking AM29SL400DT90, AM29SL400DB90 WAC, WAI, WAD, WAF A400DT90V , A400DB90V C, I, D, F AM29SL400DT100, AM29SL400DB100 A400DT10V , A400DB10V AM29SL400DT120, AM29SL400DB120 A400DT12V , A400DB12V

each of these operations in further detail. Table 1. Am29SL400D Device Bus Operations

1. Addresses are A17:A0 in word mode (BYTE# = V IH), A17:A-1 in byte mode (BYTE# = VIL).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector

Protection/Unprotection” section. used as an input for the LSB (A-1) address function. register contents are altered.

0.2 V XX VCC ±

0.2 V X High-Z High-Z High-Z

April 13, 2005 Rev. A Amend. +1 Am29SL400D 9 ADVANCE INFORMATION See “ Reading Array Data, on page 13 for more infor- mation. Refer to the AC Read Operations table for timing specifications and to Figure 13, on page 26 for the timing diagram. I CC1 in the DC Characteristics table represents the active current specification for reading array data. Writing Commands/Command Sequences To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to V IL, and OE# to VIH. For program operations, the BYTE# pin determines whether the device accepts program data in bytes or words. Refer to Word/Byte Configuration, on page 8 for more information. The device features an Unlock Bypass mode to facili- tate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The Word/Byte Program Command Sequence, on page 14 has details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sec- tors, or the entire device. Tables 2 and 3 indicate the address space that each sector occupies. A “sector address” consists of the address bits required to uniquely select a sector. The Command Definitions, on page 17 has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autose- lect Command Sequence sections for more informa- tion. I CC2 in the DC Characteristics table represents the active current specification for the write mode. The AC Characteristics, on page 26 contains timing specifica- tion tables and timing diagrams for write operations. Program and Erase Operation Status During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7–DQ0. Standard read cycle timings and I CC read specifications apply. Refer to Write Operation Status, on page 18 for more information, and to AC Characteristics, on page 26 for timing diagrams. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, inde- pendent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V CC ± 0.2 V. (Note that this is a more restricted voltage range than V IH.) If CE# and RESET# are held at VIH, but not within VCC ± 0.2 V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (t CE) for read access when the device is in either of these standby modes, before it is ready to read data. The device also enters the standby mode when the RESET# pin is driven low. Refer to the next section, RESET#: Hardware Reset Pin. If the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. I CC3 in the DC Characteristics table represents the standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for t ACC + 50 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. I CC4 in the DC Characteristics table represents the automatic sleep mode current specification. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of reset- ting the device to reading array data. When the RESET# pin is driven low for at least a period of t RP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at V SS±0.2 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.2 V, the standby current will be greater.

Table 2. Am29SL400DT Top Boot Block Sector Address Table Table 3. Am29SL400DB Bottom Boot Block Sector Address Table section for more information.

through the command register. command register, as shown in Table 5 on page 17 . Table 4. Am29SL400D Autoselect Codes (High Voltage Method) L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care. tected prior to the first sector unprotect write cycle. The device is shipped with all sectors unprotected. AMD representative for details. the timing diagrams, for this feature.

Figure 1. In-system Sector Protection/Unprotection Algorithms

Figure 2. Temporar y Sector Unprotect Operation WE# do not initiate a write cycle. reset to reading array data on power-up. sequence resets the device to reading array data. Characteristics, on page 26. page 26 shows the timing diagram.

1. All protected sectors unprotected.
2. All previously protected sectors are protected once

14 Am29SL400D Rev. A Amend. +1 April 13, 2005 ADVANCE INFORMATION before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is com- plete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend). If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Sus- pend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. Table 5 on page 17 shows the address and data requirements. This method is an alternative to that shown in Table 4 on page 11 , which is intended for PROM programmers and requires V ID on address bit A9. The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. The device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. A read cycle at address XX00h retrieves the manufacturer code. A read cycle at address 01h in word mode (or 02h in byte mode) returns the device code. A read cycle containing a sector address (SA) and the address 02h in word mode (or 04h in byte mode) returns 01h if that sector is protected, or 00h if it is unprotected. Refer to Table 2 on page 10 and Table 3 on page 10 for valid sector addresses. The system must write the reset command to exit the autoselect mode and return to reading array data. Word/Byte Program Command Sequence The system may program the device by word or byte, depending on the state of the BYTE# pin. Program- ming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or tim- ings. The device automatically generates the program pulses and verifies the programmed cell margin. Table 5 on page 17 shows the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. See Write Operation Status, on page 18 for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program- ming operation. The Byte Program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a “0” back to a “1”. Attempting to do so may halt the operation and set DQ5 to “1”, or cause the Data# Polling algorithm to indicate the operation was suc- cessful. However, a succeeding read will show that the data is still “0”. Only erase operations can convert a “0” to a “1”. Unlock Bypass Command Sequence The unlock bypass feature allows the system to program bytes or words to the device faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is pro- grammed in the same manner. This mode dispenses with the initial two unlock cycles required in the stan- dard program command sequence, resulting in faster total programming time. Write Operation Status, on page 18 shows the requirements for the command sequence. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the data 90h; the second cycle the data 00h. Addresses are don’t cares. The device then returns to reading array data. Figure 3, on page 15 illustrates the algorithm for the program operation. See the Erase/Program

Table 5. Am29SL400D Co mmand Definitions RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. rising edge of WE# or CE# pulse, whichever happens first. erased. Address bits A17–A12 uniquely select any sector.

1. See Table 1 on page 8 for description of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles are
4. Data bits DQ15–DQ8 are don’t cares for unlock and command
5. Address bits A17–A11 are don’t cares for unlock and command

cycles, unless SA or PA required.

1. No unlock or command cycles required when reading array data,
2. The Reset command is required to return to reading array data

the device is providing status data).

1. The fourth cycle of the autoselect command sequence is a read
2. The data is 00h for an unprotected sector and 01h for a protected
3. The Unlock Bypass command is required prior to the Unlock
4. The Unlock Bypass Reset command is required to return to

reading array data when the device is in the unlock bypass mode.

1. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode.

1. The Erase Resume command is valid only during the Erase Suspend

a program or erase operation is complete or in progress. These three bits are discussed first. pleted, or whether the device is in Erase Suspend. 1 µs, then the device returns to reading array data. Suspend mode, Data# Polling produces a “1” on DQ7. the selected sectors that are protected. Algorithms), illustrates this. on DQ7. Figure 5 shows the Data# Polling algorithm.

1. VA = Valid address for programming. During a sector

address is any non-protected sector address.

1. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5. Figure 5. Data# Polling Algorithm

determine the status of the operation (top of Figure 6). Sequence, on page 15 section. accepted the command sequence, and then read DQ3. pend) are ignored until the erase operation is complete.

1. Read toggle bit twice to determine whether or not it is
2. Recheck toggle bit because it may stop toggling as DQ5

Figure 6. Toggle Bit Algorithm

Table 6. Write Operation Status

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

See DQ5: Exceeded Timing Limits, on page 20 for more information.

1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

April 13, 2005 Rev. A Amend. +1 Am29SL400D 23 ADVANCE INFORMATION DC CHARACTERISTICS CMOS Compatible Notes: 1. The I CC current listed is typically less than 1 mA/MHz, with OE# at V IH. T ypical VCC is 2.0 V. 2. The maximum I CC specifications are tested with VCC = VCCmax. 3. I CC active while Embedded Erase or Embedded Program is in progress. 4. Automatic sleep mode enables the low power mode when addresses remain stable for t ACC + 50 ns. 5. Not 100% tested. Parameter Description Test Conditions Min Typ Max Unit ILI Input Load Current VIN = VSS to VCC, VCC = VCC max ±1.0 µA ILIT A9 Input Load Current V CC = VCC max; A9 = 11.0 V 35 µA ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC max ±1.0 µA ICC1 VCC Active Read Current (Notes 1, 2) CE# = VIL, OE# = VIH, Byte Mode

5 MHz 5 10

1 MHz 1 3

CE# = VIL, OE# = VIH, Word Mode (Notes 2, 3, 5) CE# = VIL, OE# = VIH 15 30 mA ICC3 VCC Standby Current (Note 2) CE#, RESET# = V CC ± 0.2 V 0.2 5 µA ICC4 VCC Reset Current (Note 2) RESET# = V SS ± 0.2 V 0.2 5 µA ICC5 Automatic Sleep Mode (Notes 2, 3) VIH = VCC ± 0.2 V; VIL = VSS ± 0.2 V 0.2 5 µA VIL Input Low Voltage –0.5 0.3 x V CC V VIH Input High Voltage 0.7 x V CC VCC + 0.3 V VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 2.0 V 9.0 11.0 V VOL1 Output Low Voltage IOL = 2.0 mA, VCC = VCC min 0.25 V VOL2 IOL = 100 µA, VCC = VCC min 0.1 V VOH1 Output High Voltage IOH = –2.0 mA, VCC = VCC min 0.85 x V CC V VOH2 IOH = –100 µA, VCC = VCC min V CC–0.1 V VLKO Low VCC Lock-Out Voltage (Note 4) 1.2 1.5 V

26 Am29SL400D Rev. A Amend. +1 April 13, 2005 ADVANCE INFORMATION AC CHARACTERISTICS Read Operations Notes: 1. Not 100% tested. 2. See Figure 11, on page 25 and Table 7 on page 25 for test specifications. Parameter

Description

JEDEC Std Test Setup 90 100 120 Unit tAVAV tRC Read Cycle Time (Note 1) Min 90 100 120 ns tAVQV tACC Address to Output Delay CE# = VIL OE# = VIL Max 90 100 120 ns tELQV tCE Chip Enable to Output Delay OE# = V IL Max 90 100 120 ns tGLQV tOE Output Enable to Output Delay Max 30 35 50 ns tEHQZ tDF Chip Enable to Output High Z (Note 1) Max 16 ns tGHQZ tDF Output Enable to Output High Z (Note 1) Max 16 ns tOEH Output Enable Hold Time (Note 1) Read Min 0 ns Toggle and Data# Polling Min 30 ns tAXQX tOH Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First (Note 1) Min 0 ns tCE Outputs WE# Addresses CE# OE# HIGH Z Output Valid HIGH Z Addresses Stable tRC tACC tOEH tOE

0 VRY/BY#

RESET# tDF tOH Figure 13. Read Operations Timings

Figure 14. RESET# Timings

April 13, 2005 Rev. A Amend. +1 Am29SL400D 29 ADVANCE INFORMATION AC CHARACTERISTICS Erase/Program Operations Notes: 1. Not 100% tested. 2. See Erase and Programming Performance, on page 37 for more information. Parameter Speed Options JEDEC Std. Description 90 100 120 Unit tAVAV tWC Write Cycle Time (Note 1) Min 90 100 120 ns tAVWL tAS Address Setup Time Min 0 ns tWLAX tAH A d d r e s s H o l d T i m e M i n 4 55 06 0 n s tDVWH tDS Data Setup Time Min 45 50 60 ns tWHDX tDH Data Hold Time Min 0 ns tOES Output Enable Setup Time Min 0 ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tELWL tCS CE# Setup Time Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 45 50 60 ns tWHWL tWPH Write Pulse Width High Min 30 ns tWHWH1 tWHWH1 Programming Operation (Notes 1, 2) Byte Typ 5 µs Word Typ 7 tWHWH2 tWHWH2 Sector Erase Operation (Notes 1, 2) Typ 0.7 sec tVCS VCC Setup Time Min 50 µs tRB Recovery Time from RY/BY# Min 0 ns tBUSY Program/Erase Valid to RY/BY# Delay Min 200 ns

1. PA = program address, PD = program data, D OUT is the true data at the program address.
2. Illustration shows device in word mode.

Figure 17. Program Operation Timings

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).
2. Illustration shows device in word mode.

Figure 18. Chip/Sector Erase Operation Timings

Figure 23. Sector Protect/Unprotect Timing Diagram

April 13, 2005 Rev. A Amend. +1 Am29SL400D 35 ADVANCE INFORMATION AC CHARACTERISTICS Alternate CE# Controlled Erase/Program Operations Notes: 1. Not 100% tested. 2. See Erase and Programming Performance, on page 37 for more information. Parameter JEDEC Std. 90 100 120 Unit tAVAV tWC Write Cycle Time (Note 1) Min 90 100 120 ns tAVEL tAS Address Setup Time Min 0 ns tELAX tAH Address Hold Time Min 45 50 60 ns tDVEH tDS Data Setup Time Min 45 50 60 ns tEHDX tDH Data Hold Time Min 0 ns tOES Output Enable Setup Time Min 0 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE# Pulse Width Min 45 50 60 ns tEHEL tCPH CE# Pulse Width High Min 30 ns tWHWH1 tWHWH1 Programming Operation (Notes 1, 2) Byte Typ 5 µs Word Typ 7 tWHWH2 tWHWH2 Sector Erase Operation (Notes 1, 2) Typ 0.7 sec

1. PA = program address, PD = program data, DQ7# = complement of the data written, D OUT = data written
2. Figure indicates the last two bus cycles of command sequence.
3. Word mode address used as an example.

Figure 24. Alternate CE# Contro lled Write Operation Timings

April 13, 2005 Rev. A Amend. +1 Am29SL400D 37 ADVANCE INFORMATION ERASE AND PROGRAMMING PERFORMANCE Notes: 1. Typical program and erase times assume the following conditions: 25 °C, 1.8 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90°C, V CC = 1.8 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algor ithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 5 on page 17 for further information on command definitions. 6. The device has a minimum guaranteed erase and program cycle endurance of 1,000,000 cycles. LATCHUP CHARACTERISTICS Includes all pins except VCC. Test conditions: VCC = 1.8 V , one pin at a time. TSOP PIN AND BGA PACKAGE CAPACITANCE Notes: 1. Sampled, not 100% tested. 2. T est conditions TA = 25°C, f = 1.0 MHz. DATA RETENTION Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 0.7 15 s Excludes 00h programming prior to erasure (Note 4)Chip Erase Time 38 s Byte Programming Time 10 300 µs Excludes system level overhead (Note 5) Word Programming Time 12 360 µs Chip Programming Time (Note 3) Byte Mode 5 40 s Word Mode 3.5 30 s Description Min Max Input voltage with respect to V SS on all pins except I/O pins (including A9, OE#, and RESET#) –1.0 V 11.0 V Input voltage with respect to V SS on all I/O pins –0.5 V V CC + 0.5 V VCC Current –100 mA +100 mA Parameter Symbol Parameter Description Test Setup Typ Max Unit CIN Input Capacitance V IN = 0 TSOP 6 7.5 pF Fine-pitch BGA 4.2 5.0 pF COUT Output Capacitance V OUT = 0 TSOP 8.5 12 pF Fine-pitch BGA 5.4 6.5 pF CIN2 Control Pin Capacitance V IN = 0 TSOP 7.5 9 pF Fine-pitch BGA 3.9 4.7 pF Parameter Test Conditions Min Unit Minimum Pattern Data Retention Time 150°C 10 Years 125°C 20 Years

38 Am29SL400D Rev. A Amend. +1 April 13, 2005 ADVANCE INFORMATION PHYSICAL DIMENSIONS FBA048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 6 x 8 mm Package Dwg rev AF; 10/99

April 13, 2005 Rev. A Amend. +1 Am29SL400D 39 ADVANCE INFORMATION REVISION SUMMARY Revision A (February 12, 2004) Initial release. Revision A+1 (April 13, 2005) Added Commercial and Industrial Pb-free options. Valid Combination Table, Added package designators for Pb-free options. Global Added Colophon. Updated Trademark. Added Cover Page. Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limita- tion, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufac tured as con- templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in we apon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion LLC will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semic onductor devices have an inherent chance of failure. Y ou must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign T rade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au- thorization by the respective government entity will be required for export of those products. Trademarks Copyright ©2003-2005 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification pur poses only and may be trademarks of their respective companies .