AM29SL400C AMD | Alldatasheet

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Publication Number Am29SL400C_00 Revision A Amendment 6 Issue Date January 23, 2007 The following document contains information on Spansion memory products. Although the document is marked with the name of the company that orig inally developed the specification, Spansion will continue to offer these products to existing customers. Continuity of Specifications There is no change to this data sheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal data sheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary. Continuity of Ordering Part Numbers Spansion continues to support existing part numbers beginning with “Am” and “MBM”. To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local sales office for additional information about Spansion memory solutions. Am29SL400C Data Sheet

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This Data Sheet states AMD’s current specifications regarding the Products described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Publication# Am29SL400C_00 Rev: A Amendment: 6 Issue Date: January 23, 2007 Am29SL400C 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 1.8 Volt-only Super Low Voltage Flash Memory Distinctive Characteristics ■ Single power supply operation — 1.65 to 2.2 V for read, program, and erase operations — Ideal for battery-powered applications ■ Manufactured on 0.32 µm process technology ■ High performance — Access times as fast as 100 ns ■ Ultra low power consumption (typical values at

5 MHz)

— 1 µA Automatic Sleep Mode current — 1 µA standby mode current — 5 mA read current — 20 mA program/erase current ■ Flexible sector architecture — One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and seven

64 Kbyte sectors (byte mode)

— One 8 Kword, two 4 Kword, one 16 Kword, and seven

32 Kword sectors (word mode)

— Supports full chip erase — Sector Protection features: A hardware method of locking a sector to prevent any program or erase operations within that sector Sectors can be locked in-system or via programming equipment Temporary Sector Unprotect feature allows code changes in previously locked sectors ■ Unlock Bypass Program Command — Reduces overall programming time when issuing multiple program command sequences ■ Top or bottom boot block configurations available ■ Embedded Algorithms — Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors — Embedded Program algorithm automatically writes and verifies data at specified addresses ■ Minimum 1,000,000 erase cycle guarantee per sector ■ 20-year data retention at 125°C ■ Package option — 48-ball FBGA — 48-pin TSOP ■ Compatibility with JEDEC standards — Pinout and software compatible with single-power supply Flash — Superior inadvertent write protection ■ Data# Polling and toggle bits — Provides a software method of detecting program or erase operation completion ■ Ready/Busy# pin (RY/BY#) — Provides a hardware method of detecting program or erase cycle completion ■ Erase Suspend/Erase Resume — Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation ■ Hardware reset pin (RESET#) — Hardware method to reset the device to reading array data

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The Am29SL400C is an 4Mbit, 1.8 V volt-only Flash memory organized as 524,288 bytes or 262,144 words. The device is offered in 48-pin TSOP and 48-ball FBGA packages. The word-wide data (x16) appears on DQ15–DQ0; the byte-wide (x8) data appears on DQ7–DQ0. This device is designed to be programmed and erased in-sys tem with a single 1.8 volt V CC supply. No VPP is required for write or erase operations. The device can also be programmed in standard EPROM programmers. The standard device offers access times of 100, 110, 120, and 150 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. The device requires only a single 1.8 volt power supply for both read and write functions. Internally generated and regu- lated voltages are provided for the program and erase opera- tions. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard . Commands are written to the command register using standard micro- processor write timings. Register contents serve as input to an internal state-machine that controls the erase and pro- gramming circuitry. Write cycles also internally latch ad- dresses and data needed for the programming and erase operations. Reading data out of the device is similar to read- ing from other Flash or EPROM devices. Device programming occurs by executing the program com- mand sequence. This initiates the Embedded Program al- gorithm—an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command se- quence. This initiates the Embedded Erase algorithm—an internal algorithm that automatically preprograms the array (if it is not already programm ed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase op- eration is complete by observing the RY/BY# pin, or by read- ing the DQ7 (Data# Polling) and DQ6 (toggle) status bits . After a program or erase cycle has been completed, the de- vice is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed witho ut affecting the data con- tents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low V CC de- tector that automatically inhi bits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combina- tion of the sectors of memory. This can be achieved in-sys- tem or via programming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also rese t the device, enabling the system micropro cessor to read the boot-up firmware from the Flash memory. The device offers two power-saving features. When ad- dresses have been stable for a specified amount of time, the device enters the automatic sleep mode . The system can also place the device into the standby mode . Power con- sumption is greatly reduced in both these modes. AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electri- cally erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection.

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Note: See “AC Characteristics” for full specifications. BLOCK DIAGRAM Family Part Number Am29SL400C Speed Options Regulated Voltage Range VCC = 1.7–2.2 V -100R Standard Voltage Range VCC = 1.65–2.2 V -110 -120 -150 Max access time, ns (tACC) 100 110 120 150 Max CE# access time, ns (tCE) 100 110 120 150 Max OE# access time, ns (tOE)3 5 4 5 5 0 6 5 Input/Output Buffers X-Decoder Y-Decoder Chip Enable Output Enable Logic Erase Voltage Generator PGM Voltage Generator TimerVCC Detector State Control Command Register VCC VSS WE# BYTE# CE# OE# STB STB DQ0–DQ15 (A-1) Sector Switches RY/BY# RESET# Data Latch Y-Gating Cell Matrix Address LatchA0–A17

January 23, 2007 Am29SL400C_00_A6 Am29SL400C 5 DATA SHEET CONNECTION DIAGRAMS A15 NC A14 A13 A12 A11 A10 NC NC WE# RESET# NC NC RY/BY# A17 A16 DQ2 BYTE# V SS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 Standard TSOP

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Special Handling Instructions for FBGA Packages Special handling is required for Flash Memory products in molded packages (TSOP , BGA, PLCC, PDIP , SSOP). The package and/or data integrity may be compromised if the package body is exposed to temperatures about 150 °C for prolonged periods of time. A1 B1 C1 D1 E1 F1 G1 H1 A2 B2 C2 D2 E2 F2 G2 H2 A3 B3 C3 D3 E3 F3 G3 H3 A4 B4 C4 D4 E4 F4 G4 H4 A5 B5 C5 D5 E5 F5 G5 H5 A6 B6 C6 D6 E6 F6 G6 H6 DQ15/A-1 V SSBYTE#A16A15A14A12A13 DQ13 DQ6DQ14DQ7A11A10A8A9 VCC DQ4DQ12DQ5NCNCRESET#WE# DQ11 DQ3DQ10DQ2NCNCNCRY/BY# DQ9 DQ1DQ8DQ0A5A6A17A7 OE# V SSCE#A0A1A2A4A3 48-Ball FBGA (Top View, Balls Facing Down)

January 23, 2007 Am29SL400C_00_A6 Am29SL400C 7 DATA SHEET PIN CONFIGURATION A0–A17 = 18 addresses DQ0–DQ14 = 15 data inputs/outputs DQ15/A-1 = DQ15 (data input/output, word mode), A-1 (LSB address input, byte mode) BYTE# = Selects 8-bit or 16-bit mode CE# = Chip enable OE# = Output enable WE# = Write enable RESET# = Hardware reset pin, active low RY/BY# = Ready/Busy# output V CC = 1.65–2.2 V single power supply VSS = Device ground NC = Pin not conn ected internally LOGIC SYMBOL 16 or 8 DQ0–DQ15 (A-1) A0–A17 CE# OE# WE# RESET# BYTE# RY/BY#

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ORDERING INFORMATION

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Am29SL400C T 100R E C TEMPERATURE RANGE C = Commercial (0°C to +70°C) D = Commercial (0°C to +70°C) with Pb-free Package F = Industrial (-40°C to +85°C) with Pb-free Package I = Industrial (–40 °C to +85°C) PACKAGE TYPE WA = 48-Ball Fine-Pitch Ball Grid Array (FBGA) 0.80 mm pitch, 6 x 8 mm package (FBA048) E = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS048) SPEED OPTION See Product Selector Guide and Valid Combinations BOOT CODE SECTOR ARCHITECTURE T = Top Sector B = Bottom Sector DEVICE NUMBER/DESCRIPTION Am29SL400C

4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS Flash Memory

1.8 Volt-only Read, Program, and Erase

Valid Combinations for TSOP Packages Order Number AM29SL400CT100R, AM29SL400CB100R EC, EI, ED, EF AM29SL400CT110, AM29SL400CB110 AM29SL400CT120, AM29SL400CB120 AM29SL400CT150, AM29SL400CB150 Valid Combinations for FBGA Packages Order Number Package Marking AM29SL400CT100R, AM29SL400CB100R WAC WAI WAD, WAF A400CT10R, A400CB10R C, I, D, F AM29SL400CT110, AM29SL400CB110 A400CT11V, A400CB11V AM29SL400CT120, AM29SL400CB120 A400CT12V, A400CB12V AM29SL400CT150, AM29SL400CB150 A400CT15V, A400CB15V

these operations in further detail. Table 1. Am29SL400C Device Bus Operations

  1. Addresses are A17:A0 in word mode (BYTE# = V IH), A17:A-1 in byte mode (BYTE# = VIL).
  2. The sector protect and sector unprotec t functions may also be implemented via programming equipment. See the “Sector

Protection/Unprotection” section. tion, DQ15–DQ0 are active and controlled by CE# and OE#. dress inputs produce valid da ta on the device data outputs. mand register contents are altered. See Reading Array Data‚ on page 15 for more information. tions and to Figure 14‚ on page 28 for the timing diagram. current specification for reading array data. to Word/Byte Configuration‚ on page 9 for more information.

0.2 V XX VCC ±

0.2 V X High-Z High-Z High-Z

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The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock By- pass mode, only two write cycles are required to program a word or byte, instead of four. The Word/Byte Program Com- mand Sequence‚ on page 15 has details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sectors, or the entire device. Table 2 on page 11 and Table 3 on page 11 indicate the address space that each sector occu- pies. A sector address consists of the address bits required to uniquely select a sector. Command Definitions‚ on page 18 has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to Autoselect Mode‚ on page 11 and Autoselect Command Sequence‚ on page 15 for more information. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The AC Character- istics‚ on page 28 contains timing spec ification tables and timing diagrams for write operations. Program and Erase Operation Status During an erase or program operation, the system may check the status of the operat ion by reading the status bits on DQ7–DQ0. Standard read cycle timings and I CC read specifications apply. Refer to Write Operation Status‚ on page 19 for more information, and to AC Characteristics‚ on page 28 for timing diagrams. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, cur- rent consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V CC ± 0.2 V. (Note that this is a more restricted voltage range than V IH.) If CE# and RESET# are held at V IH, but not within V CC ± 0.2 V, the de- vice will be in the standby mode, but the standby current will be greater. The device requires standard access time (t CE) for read access when the device is in either of these standby modes, before it is ready to read data. The device also enters the standby mode when the RESET# pin is driven low. Refer to the next section, RESET#: Hard- ware Reset Pin. If the device is deselected during erasure or programming, the device draws active current until the operation is com- pleted. I CC3 in DC Characteristics‚ on page 24 represents the standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption. The device autom atically enables this mode when addresses remain stable for t ACC + 50 ns. The auto- matic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard addres s access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the sys- tem. ICC4 in the DC Characteristics table represents the au- tomatic sleep mode current specification. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of resetting the device to reading arra y data. When the RESET# pin is driven low for at least a period of t RP, the device immedi- ately terminates any operation in progress, tristates all out- put pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the in- ternal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the dur ation of the RESET# pulse. When RESET# is held at V SS±0.2 V, the device draws CMOS standby current (I CC4). If RESET# is held at V IL but not within VSS±0.2 V, the standby current is greater. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, en- abling the system to read t he boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a 0 (busy) until the internal reset op- eration is complete, which requires a time of t READY (during Embedded Algorith ms). The system can thus monitor RY/BY# to determine whether the reset operation is com- plete. If RESET# is asserted when a program or erase oper- ation is not executing (RY/BY# pin is 1), the reset operation is completed within a time of t READY (not during Embedded Algorithms). The system can read data t RH after the RE- SET# pin returns to VIH. Refer to the AC Characteristics tables for RESET# parame- ters and to Figure 15‚ on page 29 for the timing diagram. Output Disable Mode When the OE# input is at V IH, output from the device is dis- abled. The output pins are placed in the high impedance state.

Table 2. Am29SL400CT Top Boot Block Sector Address Table Table 3. Am29SL400CB Bottom Boot Block Sector Address Table accessed in-system through the command register. tails on using the autoselect mode.

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Table 4. Am29SL400C Autoselect Codes (High Voltage Method) L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care. tion/unprotection can be implemented via two methods. Flash™ Service. Contact an AMD representative for details. unprotected. See Autoselect Mode‚ on page 11 for details. tect mode is activated by setting the RESET# pin to V ID.

Figure 1. In-System Sector Protect/

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Figure 2. Temporary Sector Unprotect Operation sequent writes are ignored until V CC is greater than V LKO. do not initiate a write cycle. WE# must be a logical zero while OE# is a logical one. vice does not accept commands on the rising edge of WE#.

  1. All protected sectors unprotected.
  2. All previously pr otected sectors are protected once again.

January 23, 2007 Am29SL400C_00_A6 Am29SL400C 15 DATA SHEET COMMAND DEFINITIONS Writing specific address and data commands or sequences into the command register initiates device operations. Table 5 on page 18 defines the valid register command se- quences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the appropriate timing diagrams in the AC Characteristics sec- tion. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after com- pleting an Embedded Program or Embedded Erase algo- rithm. After the device accepts an Erase Suspend command, the device enters the Erase Su spend mode. The system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See “Erase Suspend/Erase Resume Commands” for more information on this mode. The system must issue the reset comma nd to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect mode. See the Reset Command‚ on page 15 section, next. See also Requirements for Reading Array Data‚ on page 9 for more information. The Read Operations table provides the read parameters, and Figure 14‚ on page 28 shows the timing diagram. Reset Command Writing the reset command to the device resets the device to reading array data. Address bits are don’t care for this com- mand. The reset command may be written between the sequence cycles in an erase command sequence before erasing be- gins. This resets the device to reading array data. Once era- sure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before program- ming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the au- toselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend). If DQ5 goes high during a program or erase operation, writ- ing the reset command returns the device to reading array data (also applies during Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and devices codes, and deter- mine whether or not a sector is protected. Table 5 on page 18 shows the address and data requirements. This method is an alternative to that shown in Table 4 on page 12, which is intended for PROM programmers and requires V ID on address bit A9. The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. The de- vice then enters the autoselec t mode, and the system may read at any address any number of times, without initiating another command sequence. A read cycle at address XX00h retrieves the manufacturer code. A read cycle at ad- dress 01h in word mode (or 02h in byte mode) returns the device code. A read cycle cont aining a sector address (SA) and the address 02h in word mode (or 04h in byte mode) re- turns 01h if that sector is pr otected, or 00h if it is unpro- tected. Refer to Table 2 on page 11 and T a b l e3 o n p a g e1 1 for valid sector addresses. The system must write the reset command to exit the au- toselect mode and return to reading array data. Word/Byte Program Command Sequence The system may program the device by word or byte, de- pending on the state of the BYTE# pin. Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Pro- gram algorithm. The system is not required to provide further controls or timings. The device automatically generates the program pulses and verifies the programmed cell margin. Table 5 on page 18 shows the address and data require- ments for the byte program command sequence. When the Embedded Program algorithm is complete, the de- vice then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. See Write Operation Status‚ on page 19 for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates t he programming operation. The Byte Program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a 0 back to a 1. Attempting to do so may halt the operation and set DQ5 to 1, or cause the Data# Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still 0. Only erase operations can convert a 0 to a 1.

16 Am29SL400C Am29SL400C_00_A6 January 23, 2007

parameters, and Figure 17‚ on page 31 for timing diagrams. Note: See Table 5 for program command sequence. Figure 3. Program Operation does not require the system to preprogram prior to erase. the chip erase command sequence. and addresses are no longer latched. parameters, and to Figure 18 for timing diagrams. sector addresses and commands.

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Table 5. Am29SL400C Command Definitions RA = Address of the memory location to be read. RD = Data read from location RA during read operation. edge of WE# or CE# pulse, whichever happens first. erased. Address bits A17–A12 uniquely select any sector.

  1. See Table 1 for description of bus operations.
  2. All values are in hexadecimal.
  3. Except when reading array or autos elect data, all bus cycles are
  4. Data bits DQ15–DQ8 are don’t cares for unlock and command
  5. Address bits A17–A11 are don’t cares for unlock and command

cycles, unless SA or PA required.

  1. No unlock or command cycles required when reading array data,
  2. The Reset command is required to return to reading array data

the device is providing status data).

  1. The fourth cycle of the autoselect command sequence is a read
  2. The data is 00h for an unprotected sector and 01h for a protected
  3. The Unlock Bypass command is required prior to the Unlock
  4. The Unlock Bypass Reset command is required to return to

reading array data when the device is in the unlock bypass mode.

  1. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode.

  1. The Erase Resume command is valid only during the Erase Suspend

write operation: DQ2, DQ3, DQ5, DQ6, DQ7, and RY/BY#. the program or erase command sequence. tors, and ignores the selected sectors that are protected. (During Embedded Algorithms), illustrates this. DQ7. Figure 5 shows the Data# Polling algorithm.

  1. VA = Valid address for progra mming. During a sector erase

non-protected sector address.

  1. DQ7 should be rechecked even if DQ5 = 1 because DQ7 may

change simultaneously with DQ5. Figure 5. Data# Polling Algorithm

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If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Sus- pend mode.) If the output is high (Ready), the device is ready to read array data (including during the Erase Sus- pend mode), or is in the standby mode. Table 6 on page 22 shows the outputs for RY/BY#. Figure 14‚ on page 28 , Figure 17‚ on page 31 , and Figure 18‚ on page 32 shows RY/BY# for reset, program, and erase operations, respectively. DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Pro- gram or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sec- tor erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle (The system may use either OE# or CE# to control the read cycles). When the operation is complete, DQ6 stops tog- gling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approxi- mately 100 µs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algo- rithm erases the unprotected sectors, and ignores the se- lected sectors that are protected. The system can use DQ6 and DQ 2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the de- vice enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling‚ on page 19). If a program address falls within a protected sector, DQ6 tog- gles for approximately 1 µs af ter the program command se- quence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. Table 6 on page 22 shows the outputs for Toggle Bit I on DQ6. Figure 6‚ on page 21 shows the toggle bit algorithm. Figure 20‚ on page 33 shows the toggle bit timing diagrams. Figure 21 shows the differences between DQ2 and DQ6 in graphical form. See also the subsection on DQ2: Toggle Bit II‚ on page 20. DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the ris- ing edge of the final WE# pulse in the command sequence. The device toggles DQ2 with each OE# or CE# read cycle. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sect ors are selected for erasure. Thus, both status bits are required for sector and mode infor- mation. Refer to Table 6 on page 22 to compare outputs for DQ2 and DQ6. Figure 6‚ on page 21 shows the toggle bit algorithm in flow- chart form, and the section DQ2: Toggle Bit II‚ on page 20 explains the algorithm. See also the DQ6: Toggle Bit I sub- section. Figure 20‚ on page 33 shows the toggle bit timing di- agram. Figure 21‚ on page 34 shows the differences between DQ2 and DQ6 in graphical form. Reading Toggle Bits DQ6/DQ2 Refer to Figure 6‚ on page 21 for the following discussion. Whenever the system initially be gins reading to ggle bit sta- tus, it must read DQ7–DQ0 at least twice in a row to deter- mine whether a toggle bit is toggling . Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase op- eration. The system can r ead array data on DQ7–DQ0 on the following read cycle. However, if after the initial two read cycles, the system deter- mines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the sec- tion on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the de- vice did not completed the operation successfully, and the system must write the reset co mmand to return to reading array data. The remaining scenario is that the system initially deter- mines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the sys- tem must start at the beginning of the algorithm when it re- turns to determine the status of the operation (top of Figure 6‚ on page 21).

“0.” Only an erase operation can change a 0 back to a 1. reset command to return the device to reading array data. check, the last command might not have been accepted. Table 6 on page 22 shows the outputs for DQ3.

  1. Read toggle bit twice to determine whether or not it is toggling.
  2. Recheck toggle bit because it may stop toggling as DQ5

Figure 6. Toggle Bit Algorithm

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Table 6. Write Operation Status

  1. DQ5 switches to 1 when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See DQ5:

Exceeded Timing Limits‚ on page 21 for more information.

  1. DQ7 and DQ2 require a valid addres s when reading status information. Refer to the appropriate subsection for further details.

24 Am29SL400C Am29SL400C_00_A6 January 23, 2007

Notes: 1. The I CC current listed is typically less than 1 mA/MHz, with OE# at VIH. Typical VCC is 2.0 V. 2. The maximum I CC specifications are tested with VCC = VCCmax. 3. I CC active while Embedded Erase or Embedded Program is in progress. 4. Automatic sleep mode enables the low power mode when addresses remain stable for t ACC + 50 ns. 5. Not 100% tested. Parameter Description Test Conditions Min Typ Max Unit ILI Input Load Current VIN = VSS to VCC, VCC = VCC max ±1.0 µA ILIT A9 Input Load Current V CC = VCC max; A9 = 11.0 V 35 µA ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC max ±1.0 µA ICC1 VCC Active Read Current (Notes 1, 2) CE# = VIL, OE# = VIH, Byte Mode

5 MHz 5 10

1 MHz 1 3

CE# = VIL, OE# = VIH, Word Mode (Notes 2, 3, 5) CE# = VIL, OE# = VIH 20 25 mA ICC3 VCC Standby Current (Note 2) CE#, RESET# = VCC ± 0.2 V 1 5 µA ICC4 VCC Reset Current (Note 2) RESET# = VSS ± 0.2 V 1 5 µA ICC5 Automatic Sleep Mode (Notes 2, 3) VIH = VCC ± 0.2 V; VIL = VSS ± 0.2 V 15 µ A VIL Input Low Voltage –0.5 0.2 x V CC V VIH Input High Voltage 0.8 x V CC VCC + 0.3 V VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 2.0 V 9.0 11.0 V VOL1 Output Low Voltage IOL = 2.0 mA, VCC = VCC min 0.25 V VOL2 IOL = 100 μA, VCC = VCC min 0.1 V VOH1 Output High Voltage IOH = –2.0 mA, VCC = VCC min 0.7 x V CC V VOH2 IOH = –100 μA, VCC = VCC min V CC–0.1 V VLKO Low VCC Lock-Out Voltage (Note 4) 1.2 1.5 V

26 Am29SL400C Am29SL400C_00_A6 January 23, 2007

Table 7. Test Specifications Figure 11. Test Setup Figure 12. Input Waveforms

January 23, 2007 Am29SL400C_00_A6 Am29SL400C 27 DATA SHEET AC CHARACTERISTICS Read Operations Notes: 1. Not 100% tested. 2. See Figure 11‚ on page 26 and Table 7 on page 26 for test specifications. Parameter

Description

JEDEC Std. Test Setup -100R -110 -120 -150 Unit tAVAV tRC Read Cycle Time (Note 1) Min 100 110 120 150 ns tAVQV tACC Address to Output Delay CE# = VIL OE# = VIL Max 100 110 120 150 ns tELQV tCE Chip Enable to Output Delay OE# = V IL Max 100 110 120 150 ns tGLQV tOE Output Enable to Output Delay Max 35 45 50 65 ns tEHQZ tDF Chip Enable to Output High Z (Note 1) Max 16 ns tGHQZ tDF Output Enable to Output High Z (Note 1) Max 16 ns tOEH Output Enable Hold Time (Note 1) Read Min 0 ns Toggle and Data# Polling Min 30 ns tAXQX tOH Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First (Note 1) Min 0 ns tCE Outputs WE# Addresses CE# OE# HIGH Z Output Valid HIGH Z Addresses Stable tRC tACC tOEH tOE

0 VRY/BY#

RESET# tDF tOH Figure 13. Read Operations Timings

28 Am29SL400C Am29SL400C_00_A6 January 23, 2007

Figure 14. RESET# Timings

30 Am29SL400C Am29SL400C_00_A6 January 23, 2007

Notes: 1. Not 100% tested. 2. See the Erase and Programming Performance‚ on page 38 section for more information. Parameter Speed Options JEDEC Std Description -100R -110 -120 -150 Unit tAVAV tWC Write Cycle Time (Note 1) Min 100 110 120 150 ns tAVWL tAS Address Setup Time Min 0 ns tWLAX tAH Address Hold Time Min 50 55 60 70 ns tDVWH tDS Data Setup Time Min 50 55 60 70 ns tWHDX tDH Data Hold Time Min 0 ns tOES Output Enable Setup Time Min 0 ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tELWL tCS CE# Setup Time Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 50 55 60 70 ns tWHWL tWPH Write Pulse Width High Min 30 ns tWHWH1 tWHWH1 Programming Operation (Notes 1, 2) Byte Typ 10 µs Word Typ 12 tWHWH2 tWHWH2 Sector Erase Operation (Notes 1, 2) Typ 2 sec tVCS VCC Setup Time Min 50 µs tRB Recovery Time from RY/BY# Min 0 ns tBUSY Program/Erase Valid to RY/BY# Delay Max 200 ns

  1. PA = program address, PD = program data, D OUT is the true data at the program address.
  2. Illustration shows device in word mode.

Figure 17. Program Operation Timings

32 Am29SL400C Am29SL400C_00_A6 January 23, 2007

  1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write Operation Status‚ on page 19.
  2. Illustration shows device in word mode.

Figure 18. Chip/Sector Er ase Operation Timings

34 Am29SL400C Am29SL400C_00_A6 January 23, 2007

Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an erase-suspended sector. Figure 21. DQ2 vs. DQ6 Figure 22. Temporary Sector Unprotect

Figure 23. Sector Protect/U nprotect Timing Diagram

36 Am29SL400C Am29SL400C_00_A6 January 23, 2007

Alternate CE# Controlled Erase/Program Operations Notes: 1. Not 100% tested. 2. See the Erase and Programming Performance‚ on page 38 sec- tion for more information. Parameter JEDEC Std -100R -110 -120 -150 Unit tAVAV tWC Write Cycle Time (Note 1) Min 100 110 120 150 ns tAVEL tAS Address Setup Time Min 0 ns tELAX tAH Address Hold Time Min 50 55 60 70 ns tDVEH tDS Data Setup Time Min 50 55 60 70 ns tEHDX tDH Data Hold Time Min 0 ns tOES Output Enable Setup Time Min 0 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE# Pulse Width Min 50 55 60 70 ns tEHEL tCPH CE# Pulse Width High Min 30 ns tWHWH1 tWHWH1 Programming Operation (Notes 1, 2) Byte Typ 10 µs Word Typ 12 tWHWH2 tWHWH2 Sector Erase Operation (Notes 1, 2) Typ 2 sec

  1. PA = program address, PD = program data, DQ7# = complement of the data written, D OUT = data written
  2. Figure indicates the last two bus cycles of command sequence.
  3. Word mode address used as an example.

Figure 24. Alternate CE# Controlled

38 Am29SL400C Am29SL400C_00_A6 January 23, 2007

ERASE AND PROGRAMMING PERFORMANCE Notes: 1. Typical program and erase times assume the following conditions: 25 °C, 2.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90°C, V CC = 1.8 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute th e two- or four-bus-cycle sequence for the program command. See Table 5 on page 18 for further information on command definitions. 6. The device has a minimum guaranteed erase and program cycle endurance of 1,000,000 cycles. Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 2 15 s Excludes 00h programming prior to erasure (Note 4)Chip Erase Time 38 s Byte Programming Time 10 300 µs Excludes system level overhead (Note 5) Word Programming Time 12 360 µs Chip Programming Time (Note 3) Byte Mode 5 40 s Word Mode 3.5 30 s

January 23, 2007 Am29SL400C_00_A6 Am29SL400C 39 DATA SHEET LATCHUP CHARACTERISTICS Includes all pins except VCC. Test conditions: VCC = 1.8 V, one pin at a time. TSOP PIN AND BGA PACKAGE CAPACITANCE Notes: 1. Sampled, not 100% tested. 2. Test conditions T A = 25°C, f = 1.0 MHz. DATA RETENTION Description Min Max Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) –1.0 V 11.0 V Input voltage with respect to VSS on all I/O pins –0.5 V V CC + 0.5 V VCC Current –100 mA +100 mA Parameter Symbol Parameter Description Test Setup Typ Max Unit CIN Input Capacitance V IN = 0 TSOP 6 7.5 pF Fine-pitch BGA 4.2 5.0 pF COUT Output Capacitance V OUT = 0 TSOP 8.5 12 pF Fine-pitch BGA 5.4 6.5 pF CIN2 Control Pin Capacitance V IN = 0 TSOP 7.5 9 pF Fine-pitch BGA 3.9 4.7 pF Parameter Test Conditions Min Unit Minimum Pattern Data Retention Time 150°C 10 Y ears 125°C 20 Y ears

40 Am29SL400C Am29SL400C_00_A6 January 23, 2007

TS048—48-Pin Standard TSOP Dwg rev AA; 10/99

January 23, 2007 Am29SL400C_00_A6 Am29SL400C 41 DATA SHEET PHYSICAL DIMENSIONS FBA048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 6 x 8 mm Package Dwg rev AF; 10/99

42 Am29SL400C Am29SL400C_00_A6 January 23, 2007

Revision A (August 14, 2002) Initial Release. Revision A+1 (August 28, 2002) Sector Protection/Unprotection Changed beginning of second paragraph from, “The primary Deleted third paragraph. FBB048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 6 x 8 mm package Changed number in row D in table from 9.00 mm to 8.0 mm. Revision A+2 (February 5, 2003) Global Changed fastest speed option fr om 103 ns to 100 ns, regu- lated voltage, added 110 ns speed option standard voltage. General Description Changed first sentenced to indicate 48-pin TSOP package option. Command Definitions, Table 5 Removed TBD markers from device ID, Top Boot Block to 70h. Removed TBD markers from device ID, Bottom Boot Block to FIh. Changed address bits A18–A11 to A17–A11. Physical Dimensions, 48-pin TSOP Changed from Reverse to Standard TSOP package. Revision A+3 (February 26, 2003) Global Added 110 ns speed option. Distinctive Characteristics Updated Automatic Sleep Mode and standby mode current values. Pin Configuration Updated VCC low-end value. Changed WB package type to WA. DC Characteristics, CMOS Compatible Updated V CC Standby and Reset currents Typ values, and Automatic Sleep Mode Typ value. Revision A+4 (March 18, 2003) Ordering Information, Valid Combinations Removed dashes from Order Numbers. Revision A+5 (March 3, 2005) Added Commercial and Industrial Pb-free Package tempera- tures. Valid Combinations for TSOP package Added two package codes. Valid Combination for FBGA package Added two package codes. Global Added Colophon. Updated Trademark information. Revision A6 (January 23, 2007) AC Characteristics Erase and Program Operations table: Changed t BUSY to a maximum specification. Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limita- tion, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as con- templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion Inc. will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. Y ou must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au- thorization by the respective government entity will be required for export of those products. Trademarks Copyright © 2002–2005 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trade- marks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. Copyright © 2006–2007 Spansion Inc. All Rights Reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, HD-SIM, and combinations thereof are trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners.