A29DL32X AMICC | Alldatasheet

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32 Megabit (4M x 8-Bit/2M x 16-Bit) CMOS 3.0 Volt-only, Preliminary Simultaneous Operation Flash Memory PRELIMINARY (May, 2005, Version 0.0) AMIC Technology, Corp. Document Title 4M X 8 Bit / 2M X 16 Bi t CMOS 3.0 Volt-only, Boot Sector Flash Memory

Revision History

Rev. No. History Issue Date Remark

0.0 Initial issue May 25, 2005 Preliminary

32 Megabit (4M x 8-Bit/2M x 16-Bit) CMOS 3.0 Volt-only, Preliminary Simultaneous Operation Flash Memory PRELIMINARY (May, 2005, Version 0.0) 1 AMIC Technology, Corp. DISTINCTIVE CHARACTERISTICS ARCHITECTURAL ADVANTAGES „ Simultaneous Read/Write operations - Data can be continuously read from one bank while executing erase/program functions in other bank - Zero latency between read and write operations „ Multiple bank architectures - Three devices available with different bank sizes (refer to Table 2) „ Package options - 48-ball TFBGA - 48-pin TSOP „ Top or bottom boot block „ Manufactured on 0.18 µm process technology - Compatible with AMD AM29DL32xD device „ Compatible with JEDEC standards - Pinout and software compatible with single-power-supply flash standard PERFORMANCE CHARACTERISTICS „ High performance - Access time as fast as 70ns - Program time: 7µs/word typical utilizing Accelerate function „ Ultra low power consumption (typical values) - 2mA active read current at 1MHz - 10mA active read current at 5MHz - 200nA in standby or automatic sleep mode „ Minimum 1 million write cycles guaranteed per sector „ 20 Year data retention at 125°C - Reliable operation for the life of the system SOFTWARE FEATURES „ Supports Common Flash Memory Interface (CFI) „ Erase Suspend/Erase Resume - Suspends erase operations to allow programming in same bank Data Polling and Toggle Bits - Provides a software method of detecting the status of program or erase cycles „ Unlock Bypass Program command - Reduces overall programming time when issuing multiple program command sequences HARDWARE FEATURES „ Any combination of sectors can be erased „ Ready/ Busy output (RY/BY) - Hardware method for detecting program or erase cycle completion „ Hardware reset pin (RESET) - Hardware method of resetting the internal state machine to reading array data „ WP /ACC input pin - Write protect ( WP ) function allows protection of two outermost boot sectors, r egardless of sector protect status - Acceleration (ACC) functi on accelerates program timing „ Sector protection - Hardware method of locking a sector, either in-system or using programming equipment, to prevent any program or erase operation within that sector - Temporary Sector Unprotect allows changing data in protected sectors in-system „ Software temporary sector/sector block unprotect command „ Software sector protect/unprotect command

PRELIMINARY (May, 2005, Version 0.0) 2 AMIC Technology, Corp. GENERAL DESCRIPTION The A29DL32x family consists of 32 megabit, 3.0 volt-only flash memory devices, organized as 2,097,152 words of 16 bits each or 4,194,304 bytes of 8 bits each. Word mode data appears on I/O 0–I/O15; byte mode data appears on I/O 0–I/O7. The device is designed to be programmed in-system with the standard 3.0 volt VCC supply, and can also be programmed in standard EPROM programmers. The device is available with an access time of 70, 80, 90, or 120 ns. The devices are offered in 48-pin TSOP and 48-ball Fine-pitch TFBGA. Standard control pins—chip enable ( CE ), write enable ( WE ), and output enable ( OE )—control normal read and write operations, and avoid bus contention issues. The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provid ed for the program and erase operations. Simultaneous Read/Write Operations with Zero Latency The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into two banks. The device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from the other bank, with zero latency. This releases the system from waiting for the completion of program or erase operations. The A29DL32x devices use multiple bank architectures to provide flexibility for different applications. Three devices are available with these bank sizes: Device Bank 1 Bank 2 DL322 4 Mb 28 Mb DL323 8 Mb 24 Mb DL324 16 Mb 16 Mb A29DL32x Features The device offers complete compatibility with the JEDEC single-power-supply Flash command set standard . Commands are written to the command register using standard microprocessor write timings. Reading data out of the device is similar to readin g from other Flash or EPROM devices. The host system can detect w hether a program or erase operation is complete by using the device status bits: RY/ BY pin, I/O 7 ( Data Polling) and I/O 6/I/O2 (toggle bits). After a program or erase cycle has been completed, the device automatically returns to reading array data. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. T he device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically i nhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved in-s y s t e m or via programming equipment. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode . The system can also place the device into the standby mode . Power consumption is greatly reduced in both modes.

PRELIMINARY (May, 2005, Version 0.0) 3 AMIC Technology, Corp. Pin Configurations „ TSOP (I) A29DL32xV A14 A13 A12 A11 A10 A20 WE RESET NC WP/ACC RY/BY A18

33 I/O

I/O15 (A-1) VSS BYTE A16A15 A19 24 25

32 I/O 9

„ TFBGA A6 B6 C6 D6 E6 F6 G6 H6 TFBGA Top View, Balls Facing Down A5 B5 C5 D5 E5 F5 G5 H5 A4 B4 C4 D4 E4 F4 G4 H4 A3 B3 C3 D3 E3 F3 G3 H3 A2 B2 C2 D2 E2 F2 G2 H2 A1 B1 C1 D1 E1 F1 G1 H1 A13 A12 A14 A15 A16 BYTE I/O 15(A-1) VSS A9 A8 A10 A11 I/O 7 I/O14 I/O13 I/O6 WE RESET NC A19 I/O 5 I/O12 VCC I/O 4 RY/BY A18 A20 I/O 2 I/O10 I/O11 I/O3 A7 A17 A6 A5 I/O 0 I/O 8 I/O9 I/O1 A3 A4 A2 A1 A0 CE OE VSS WP/ACC

PRELIMINARY (May, 2005, Version 0.0) 4 AMIC Technology, Corp. Block Diagram A0-A20 A0-A20 A0-A20 STATE CONTROL COMMAND REGISTER I/O0-I/O15 RESET WE CE WP/ACC RY/BY Status Control BYTE OE BYTE Upper Bank Address Lower Bank Address I/O0-I/O15 Upper Bank X-Decoder Y-Decoder Latches and Control Logic Upper Bank X-Decoder Y-Decoder Latches and Control Logic I/O0-I/O15 I/O0-I/O15 VCC VSS OE BYTE A0-A20 A0-A20 Pin Descriptions Pin No. Description A0 – A20 Address Inputs I/O0 - I/O14 Data Inputs/Outputs I/O15 Data Input/Output, Word Mode I/O15 (A-1) A-1 LSB Address Input, Byte Mode CE Chip Enable WE Write Enable OE Output Enable WP /ACC Hardware Write Protect/Acceleration Pin RESET Hardware Reset Pin, Active Low BYTE Selects 8-bit or 16-bit Mode RY/BY Ready/BUSY Output VSS Ground VCC 3.0 volt-only single power supply NC Pin Not Connected Internally Logic Symbol A0-A20 CE OE WE RESET BYTE RY/BY I/O0-I/O15(A-1) 16 or 8 WP/ACC

PRELIMINARY (May, 2005, Version 0.0) 5 AMIC Technology, Corp. these operations in further detail. Table 1. A29DL32x Device Bus Operations

  1. Addresses are A20:A0 in word mode (BYTE=VIH), A20: A-1 in byte mode (BYTE=VIL).
  2. The sector protect and sector unpr otect functions may also be implement ed via programming equipment. See the

“Sector/Sector Block Protection and Unprotection” section.

  1. If WP /ACC = V IL, the two outermost boot sect ors remain protected. If WP /ACC = V IH, the two outermost boot sector

Protection and Unprotection”. If WP /ACC = VHH all sectors will be unprotected.

PRELIMINARY (May, 2005, Version 0.0) 6 AMIC Technology, Corp. Word/Byte Configuration The BYTE pin determines whether the I/O pins I/O 15-I/O0 operate in the byte or word configuration. If the BYTE pin is set at logic ”1”, the device is in word configuration, I/O 15-I/O0 are active and controlled by CE and OE . If the BYTE pin is set at logic “0”, the device is in byte configuration, and only I/O 0-I/O7 are active and controlled by CE and OE . I/O8-I/O14 are tri-stated, and I/O 15 pin is used as an input for the LSB(A-1) address function. Requirements for Reading Array Data To read array data from the out puts, the system must drive the CE and OE pins to V IL. CE is the power control and selects the device. OE is the output cont rol and gates array data to the output pins. WE should remain at V IH. The BYTE pin determines whether the device outputs array data in words or bytes. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the devi ce data outputs. Each bank remains enabled for read access until the command register contents are altered. See "Requirements for Reading Array Data" for more information. Refer to the AC Read-Only Operations table for timing specifications and to Figure 11 for the timing waveform, lCC1 in the DC Characteristics table represents the active current specification for reading array data. Writing Commands/Command Sequences To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE and CE to V IL, and OE to VIH. For program operations, the BYTE pin determines whether the device accepts progr am data in bytes or words, Refer to “Word/Byte Configuration” for more information. The device features an Unlock Bypass mode to facilitate faster programming. Once a bank enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The “Word / Byte Program Command Sequence” section has details on programming data to the device using both standard and Unlock Bypass command sequence. An erase operation can erase one sector, multiple sectors, or the entire device. The Sector Address Tables 3-4 indicate the address range that each sect or occupies. The device address space is divided into two banks: Bank 1 contains the boot/parameter sectors, and Bank 2 contains the larger, code sectors of uniform size. A “bank address” is the address bits required to uniquely select a bank. Similarly, a “sector address” is the address bits required to uniquely select a sector. I CC2 in the DC Characteristics table represents the active current specification for the write mode. The "AC Characteristics" section contai ns timing specification tables and timing diagrams for write operations. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This is one of two functions provided by the WP /ACC pin. This function is primarily intended to allow faster manufacturing throughput at the factory. If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlo ck Bypass mode, temporarily unprotects any protected sect ors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing V HH from the WP /ACC pin returns the device to normal operation. Note that the WP /ACC pin must not be at VHH for operations other than accelerated program- ming, or device damage may result. In addition, the WP /ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Autoselect Functions If the system writes the autos elect command sequence, the device enters the autoselect m ode. The system can then read autoselect codes from the in ternal register (which is separate from the memory array) on I/O 7-I/O0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autoselect Command Sequence sections for more information. Simultaneous Read/Write Operations with Zero Latency This device is capable of r eading data from one bank of memory while programming or er asing in the other bank of memory. An erase operation may also be suspended to read from or program to another location within the same bank (except the sector being erased). Figure 18 shows how read and write cycles may be initiat ed for simultaneous operation w i t h z e r o l a t e n c y . ICC6 and I CC7 in the DC Characteristics table represent the current spec ifications for read-while-pro- gram and read-while-erase, respectively. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatl y reduced, and the outputs are placed in the high impedanc e state, indepen dent of the OE input. The device enters the CMOS standby mode when the CE & RESET pins are both held at VCC ± 0.3V. (Note that this is a more restricted voltage range than V IH.) If CE and RESET are held at V IH, but not within VCC ± 0.3V, the device will be in the standby mode, but the st andby current will be greater. The device requires the standard access time (t CE) for read access when the device is in ei ther of these standby modes, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active curr ent until the operation is completed. ICC3 in the DC Characteristics t ables represent the standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption. The device autom atically enables this mode when addresses remain stable for t ACC +30ns. The automatic

PRELIMINARY (May, 2005, Version 0.0) 7 AMIC Technology, Corp. Current is reduced fo r the duration of the RESET pulse. within VSS ± 0.3V, the standby current will be greater. the RESET pin return to VIH. Table 2. A29DL32x Device Bank Divisions

64 Kbyte/32 Kword

PRELIMINARY (May, 2005, Version 0.0) 8 AMIC Technology, Corp. Table 3 Sector Addresses for Top Boot Sector Devices A29DL324T A29DL323T A29DL322T Sector Sector Address A20–A12 Sector Size (Kbytes/Kwords) (x8) Address Range (x16) Address Range SA0 000000XXX 64/32 000000 h-00FFFFh 000000h–007FFFh SA1 000001XXX 64/32 010000 h-01FFFFh 008000h–00FFFFh SA2 000010XXX 64/32 020000h-02FFFFh 010000h–017FFFh SA3 000011XXX 64/32 030000 h-03FFFFh 018000h–1FFFFFh SA4 000100XXX 64/32 040000 h-04FFFFh 020000h–027FFFh SA5 000101XXX 64/32 050000h-05FFFFh 028000h–02FFFFh SA6 000110XXX 64/32 060000 h-06FFFFh 030000h–037FFFh SA7 000111XXX 64/32 070000h-07FFFFh 038000h–03FFFFh SA8 001000XXX 64/32 080000 h-08FFFFh 040000h–047FFFh SA9 001001XXX 64/32 090000h-09FFFFh 048000h–04FFFFh SA10 001010XXX 64/32 0A00 00h-0AFFFFh 050000h–057FFFh SA11 001011XXX 64/32 0B00 00h-0BFFFFh 058000h–05FFFFh SA12 001100XXX 64/32 0C0000 h-0CFFFFh 060000h–067FFFh SA13 001101XXX 64/32 0D0000h-0DFFFFh 068000h–06FFFFh SA14 001110XXX 64/32 0E00 00h-0EFFFFh 070000h–077FFFh SA15 001111XXX 64/32 0F0000h-0FFFFFh 078000h–07FFFFh SA16 010000XXX 64/ 32 100000h-10FFFFh 080000h–087FFFh SA17 010001XXX 64/32 110000h-11FFFFh 088000h–08FFFFh SA18 010010XXX 64/ 32 120000h-12FFFFh 090000h–097FFFh SA19 010011XXX 64/32 130000h-13FFFFh 098000h–09FFFFh SA20 010100XXX 64/32 140000h-14FFFFh 0A0000h–0A7FFFh SA21 010101XXX 64/32 150000h-15FFFFh 0A8000h–0AFFFFh SA22 010110XXX 64/32 160000h-16FFFFh 0B0000h–0B7FFFh SA23 010111XXX 64/32 170000h-17FFFFh 0B8000h–0BFFFFh SA24 011000XXX 64/32 180000h-18FFFFh 0C0000h–0C7FFFh SA25 011001XXX 64/32 190000h-19FFFFh 0C8000h–0CFFFFh SA26 011010XXX 64/32 1A00 00h-1AFFFFh 0D0000h–0D7FFFh SA27 011011XXX 64/32 1B00 00h-1BFFFFh 0D8000h–0DFFFFh SA28 011100XXX 64/32 1C0000h-1CFFFFh 0E0000h–0E7FFFh SA29 011101XXX 64/32 1D0000h-1DFFFFh 0E8000h–0EFFFFh SA30 011110XXX 64/32 1E00 00h-1EFFFFh 0F0000h–0F7FFFh Bank 2 SA31 011111XXX 64/32 1F0000h-1FFFFFh 0F8000h–0FFFFFh SA32 100000XXX 64/32 200000h-20FFFFh 100000h–107FFFh SA33 100001XXX 64/32 210000h-21FFFFh 108000h–10FFFFh SA34 100010XXX 64/32 220000h-22FFFFh 110000h–117FFFh SA35 100011XXX 64/32 230000h-23FFFFh 118000h–11FFFFh SA36 100100XXX 64/32 240000h-24FFFFh 120000h–127FFFh SA37 100101XXX 64/32 250000h-25FFFFh 128000h–12FFFFh SA38 100110XXX 64/32 260000h-26FFFFh 130000h–137FFFh SA39 100111XXX 64/32 270000h-27FFFFh 138000h–13FFFFh SA40 101000XXX 64/ 32 280000h-28FFFFh 140000h–147FFFh SA41 101001XXX 64/32 290000h-29FFFFh 148000h–14FFFFh SA42 101010XXX 64/32 2A00 00h-2AFFFFh 150000h–157FFFh SA43 101011XXX 64/32 2B00 00h-2BFFFFh 158000h–15FFFFh SA44 101100XXX 64/32 2C0000 h-2CFFFFh 160000h–167FFFh SA45 101101XXX 64/32 2D0000h-2DFFFFh 168000h–16FFFFh SA46 101110XXX 64/32 2E00 00h-2EFFFFh 170000h–177FFFh Bank 1 Bank 2 Bank 2 SA47 101111XXX 64/32 2F0000h-2FFFFFh 178000h–17FFFFh

PRELIMINARY (May, 2005, Version 0.0) 9 AMIC Technology, Corp. Table 3 Sector Addresses for Top Boot Sector Devices A29DL324T A29DL323T A29DL322T Sector Sector Address A20–A12 Sector Size (Kbytes/Kwords) (x8) Address Range (x16) Address Range SA48 110000XXX 64/32 300000h-30FFFFh 180000h–187FFFh SA49 110001XXX 64/32 310000h-31FFFFh 188000h–18FFFFh SA50 110010XXX 64/32 320000h-32FFFFh 190000h–197FFFh SA51 110011XXX 64/32 330000h-33FFFFh 198000h–19FFFFh SA52 110100XXX 64/32 340000h-34FFFFh 1A0000h–1A7FFFh SA53 110101XXX 64/32 350000h-35FFFFh 1A8000h–1AFFFFh SA54 110110XXX 64/32 360000h-36FFFFh 1B0000h–1B7FFFh Bank 2 SA55 110111XXX 64/32 370000h-37FFFFh 1B8000h–1BFFFFh SA56 111000XXX 64/32 380000h-38FFFFh 1C0000h–1C7FFFh SA57 111001XXX 64/32 390000h-39FFFFh 1C8000h–1CFFFFh SA58 111010XXX 64/32 3A0000h-3AFFFFh 1D0000h–1D7FFFh SA59 111011XXX 64/32 3B0000h-3BFFFFh 1D8000h–1DFFFFh SA60 111100XXX 64/32 3C0000h-3CFFFFh 1E0000h–1E7FFFh SA61 111101XXX 64/32 3D0000h-3DFFFFh 1E8000h–1EFFFFh SA62 111110XXX 64/32 3E0000h-3EFFFFh 1F 0000h–1F7FFFh SA63 111111000 8/4 3F0000h-3FFFFFh 1F8000h–1F8FFFh SA64 111111001 8/4 3F2000h-3F3FFFh 1F9000h–1F9FFFh SA65 111111010 8/4 3F4000h-3F5FFFh 1FA000h–1FAFFFh SA66 111111011 8/4 3F6000h-3F7FFFh 1FB000h–1FBFFFh SA67 111111100 8/4 3F8000h-3F9FFFh 1FC000h–1FCFFFh SA68 111111101 8/4 3FA000h-3FBFFFh 1FD000h–1FDFFFh SA69 111111110 8/4 3FC000h-3FDFFFh 1FE000h–1FEFFFh Bank 1 Bank 1 Bank 1 SA70 111111111 8/4 3FE000h-3FFFFFh 1FF000h–1FFFFFh The address range is A20: A-1in byte mode ( BYTE=VIL) or A20:A0 in word mode (BYTE=VIH). The bank address bits are A20- A18 for A29DL322T, A20 and A19 for A29DL323T, and A20 for A29DL324T.

PRELIMINARY (May, 2005, Version 0.0) 10 AMIC Technology, Corp. Table 4. Sector Addresses for Bottom Boot Sector Devices

PRELIMINARY (May, 2005, Version 0.0) 11 AMIC Technology, Corp. A29DL324U A29DL323U A29DL322U Sector Sector Address A20–A12 Sector Size (Kbytes/Kwords) (x8) Address Range (x16) Address Range SA48 101001XXX 64/32 290000h-29FFFFh 148000h-14FFFFh SA49 101010XXX 64/32 2A0000h-2AFFFFh 150000h-157FFFh SA50 101011XXX 64/ 32 2B0000h-2BFFFFh 158000h-15FFFFh SA51 101100XXX 64/32 2C0000h-2CFFFFh 160000h-167FFFh SA52 101101XXX 64/32 2D0000h-2DFFFFh 168000h-16FFFFh SA53 101110XXX 64/ 32 2E0000h-2EFFFFh 170000h-177FFFh SA54 101111XXX 64/32 2F0000h-2FFFFFh 178000h-17FFFFh SA55 110000XXX 64/32 300000h-30FFFFh 180000h-187FFFh SA56 110001XXX 64/32 310000h-31FFFFh 188000h-18FFFFh SA57 110010XXX 64/32 320000h-32FFFFh 190000h-197FFFh SA58 110011XXX 64/32 330000h-33FFFFh 198000h-19FFFFh SA59 110100XXX 64/32 340000h-34FFFFh 1A0000h-1A7FFFh SA60 110101XXX 64/32 350000h-35FFFFh 1A8000h-1AFFFFh SA61 110110XXX 64/32 360000h-36FFFFh 1B0000h-1B7FFFh SA62 110111XXX 64/ 32 370000h-37FFFFh 1B8000h-1BFFFFh SA63 111000XXX 64/32 380000h-38FFFFh 1C0000h-1C7FFFh SA64 111001XXX 64/32 390000h-39FFFFh 1C8000h-1CFFFFh SA65 111010XXX 64/32 3A0000h-3AFFFFh 1D0000h-1D7FFFh SA66 111011XXX 64/32 3B0000h-3BFFFFh 1D8000h-1DFFFFh SA67 111100XXX 64/32 3C0000h-3CFFFFh 1E0000h-1E7FFFh SA68 111101XXX 64/32 3D0000 h-3DFFFFh 1E8000h-1EFFFFh SA69 111110XXX 64/32 3E00 00h-3EFFFFh 1F0000h-1F7FFFh Bank 2 Bank 2 Bank 2 SA70 111111XXX 64/32 3F0000h-3FFFFFh 1F8000h-1FFFFFh Note: The address range is A20: A-1in byte mode (BYTE=VIL) or A20:A0 in word mode (BYTE=VIH). The bank address bits are A20- A18 for A29DL322U, A20 and A19 for A29DL323U, and A20 for A29DL324U.

PRELIMINARY (May, 2005, Version 0.0) 12 AMIC Technology, Corp. also be accessed in-system through the command register. must appear on the appropriate highest order address bits. corresponding identifier code on I/O7 - I/O0. Table 5. A29DL32x Autoselect Codes (High Voltage Method) Note: The autoselect codes may also be accessed in-system via command sequences.

PRELIMINARY (May, 2005, Version 0.0) 13 AMIC Technology, Corp. unprotected at the same time (see Tables 6 and 7). Table 6. Top Boot Sector/Sector Block Addresses for Table 7. Bottom Boot Sector/Sector Block Addresses for

PRELIMINARY (May, 2005, Version 0.0) 14 AMIC Technology, Corp. The hardware sector protec tion feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. Sector protection and unprotection can be implemented via two methods. The primary method requires V ID on the RESET pin only, and can be implemented either in-system or via programming equipment. Figure 2 shows the algorithms and Figure 23 shows the timing diagram. This method uses standard microprocessor bus cycle timing. For sector unprotect, all unprotected sector s must first be protected prior to the first sector unprotect write cycle. The sector unprotect algorith m unprotects all sectors in parallel. All previously protect ed sectors must be individually re-protected. To change data in protected sectors efficiently, the temporary sector unprotect function is available. See “Temporary Sector/Sector Block Unprotect”. The alternate method for protec tion and unprotection is by software sector /sector block protect unprotect command. See Figure 2 for Command Flow. The device is shipped with all sectors unprotected. It is possible to determine whether a sector is protected or unprotected. See the Autoselect Mode section for details. Write Protect ( WP ) The Write Protect function provides a hardware method of protecting certain boot sectors without using V ID. This function is one of two provided by the WP /ACC pin. If the system asserts V IL on the WP /ACC pin, the device disables program and erase func tions in the two “outermost”

8 Kbyte boot sectors independent ly of whether those sectors

were protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. The two outermost 8 Kbyte boot sectors are the two sectors containing the lowest addres ses in a bottom-boot-configured device, or the two sectors co ntaining the highest addresses in a top-boot-configured device. If the system asserts V IH on the WP /ACC pin, the device reverts to whether the two ou termost 8 Kbyte boot sectors were last set to be protected or unprotected. That is, sector protection or unprotection fo r these two sectors depends on whether they were last protec ted or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. Note that the WP /ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Temporary Sector/Sector Block Unprotect (Note: For the following discussion, the term “sector” applies to both sectors and sector blocks. A sector block consists of two or more adjacent sector s that are protected or unprotected at the same time (see Tables 6 and 7). This feature allows temporar y unprotection of previously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET pin to VID (8.5V-12.5V). During this m ode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once VID is removed from the RESET pin, all the previously protected sectors are protected again. Figure 1 shows the algorithm, and Figure 22 shows the timing diagrams, for this feature.

PRELIMINARY (May, 2005, Version 0.0) 16 AMIC Technology, Corp. START PLSCNT=1 RESET=VID Wait 1 us First Write Cycle=60h? Set up sector address Sector Protect: Write 60h to sector address with A6=0, A1=1, A0=0 Wait 150 us Verify Sector Protect: Write 40h to sector address with A6=0, A1=1, A0=0 Read from sector address with A6=0, A1=1, A0=0 Data=01h? Protect another sector? Remove VID from RESET Write reset command Sector Protect complete Sector Protect Algorithm Temporary Sector Unprotect Mode Increment PLSCNT PLSCNT =25? Device failed No No No Yes Reset PLSCNT=1 Yes Yes No Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address START PLSCNT=1 Wait 1 us First Write Cycle=60h? No Temporary Sector Unprotect Mode Yes No All sectors protected? Set up first sector address Sector Unprotect: Write 60h to sector address with A6=1, A1=1, A0=0 Wait 15 ms Verify Sector Unprotect : Write 40h to sector address with A6=1, A1=1, A0=0 Read from sector address with A6=1, A1=1, A0=0 Data=00h? Last sector verified? Remove VID from RESET Write reset Command Sector Unprotect complete Yes Yes Set up next sector address No Yes Yes Sector Unprotect Algorithm Increment PLSCNT PLSCNT= 1000? Device failed Yes No No Figure 2-1. High Voltage Sector/Sector Block Protection and Unprotection Algorithms Note: The term “sector” in the figure applies to both sectors and sector blocks * No other command is allowed during this process ** Read access time is 200ns-300ns RESET=VID

PRELIMINARY (May, 2005, Version 0.0) 17 AMIC Technology, Corp. START PLSCNT=1 555/AA + 2AA/55 + Wait 1 us First Write Cycle=60h? Set up sector address Sector Protect: Write 60h to sector address with A6=0, A1=1, A0=0 Wait 150 us Verify Sector Protect: Write 40h to sector address with A6=0, A1=1, A0=0 Read from sector address with A6=0, A1=1, A0=0 Data=01h? Protect another sector? Write reset command Sector Protect complete Sector Protect Algorithm Temporary Sector Unprotect Mode Increment PLSCNT PLSCNT =25? Device failed No No No Yes Reset PLSCNT=1 Yes Yes No Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address START PLSCNT=1 Wait 1 us First Write Cycle=60h? No Temporary Sector Unprotect Mode Yes No All sectors protected? Set up first sector address Sector Unprotect: Write 60h to sector address with A6=1, A1=1, A0=0 Wait 15 ms Verify Sector Unprotect : Write 40h to sector address with A6=1, A1=1, A0=0 Read from sector address with A6=1, A1=1, A0=0 Data=00h? Last sector verified? Write reset Command Sector Unprotect complete Yes Yes Set up next sector address No Yes Yes Sector Unprotect Algorithm Increment PLSCNT PLSCNT= 1000? Device failed Yes No No Figure 2-2. Software Sector/Sector Block Protection and Unprotection Algorithms Note: The term “sector” in the figure applies to both sectors and sector blocks * No other command is allowed during this process ** Read access time is 200ns-300ns 555/AA + 2AA/55 +

PRELIMINARY (May, 2005, Version 0.0) 18 AMIC Technology, Corp. inadvertent writes (refer to Table 12 for command definitions). when VCC is greater than VLKO. do not initiate a write cycle. WE must be a logical zero while OE is a logical one. device does not accept commands on the rising edge of WE . interfaces for long-term compatibility. reset command to return the device to the autoselect mode. Table 8. CFI Query Identification String

PRELIMINARY (May, 2005, Version 0.0) 19 AMIC Technology, Corp. Table 9. System Interface String

PRELIMINARY (May, 2005, Version 0.0) 20 AMIC Technology, Corp. Table 11. Primary Vendor-Specific Extended Query

PRELIMINARY (May, 2005, Version 0.0) 21 AMIC Technology, Corp. COMMAND DEFINITIONS Writing specific address and data commands or sequences into the command register initiates device operations. Table 12 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. A reset command is then required to return the device to reading array data. All addresses are latched on the falling edge of WE or CE , whichever happens later. All data is latched on the rising edge of WE or CE , whichever happens first. Refer to the AC Characteristics section for timing diagrams. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the corresponding bank enters the erase-suspend-read mode, after which the system can read data from any non-erase- suspended sector within the same bank. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See the Erase Suspend/Erase Resume Commands section for more information. The system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if I/O 5 goes high during an active program or erase operation, or if the bank is in the autoselect mode. See the next section, Reset Command, for more information. See also Requirements for Reading Array Data in the Device Bus Operations section for more information. The Read-Only Operations table provides the read parameters, and Figure 11 shows the timing diagram. Reset Command Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the bank to which the system was writing to reading array data. Once er asure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the bank to which the system was writing to reading array data. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data. If a bank entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. If I/O 5 goes high during a program or erase operation, writing the reset command returns the banks to reading array data (or erase-suspend-read mode if that bank was in Erase Suspend). Autoselect Command Sequence The autoselect command sequenc e allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. Table 12 shows the address and data requirement s. This method is an alternative to that shown in Table 5, which is intended for PROM programmers and requires V ID on address pin A9. The autoselect command sequence may be written to an address wit h in a bank that is either in t he read or erase- suspend-read mode. The autoselect command may not be written while the device is actively programming or erasing in the other bank. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the bank address and the autoselect command. T he bank then enter s the autoselec t mode. The system may read at any address within the same bank any number of times without initiating another autoselect command sequence: „ A read cycle at address (BA)XX00h (where BA is the bank address) returns the manufacturer code. „ A read cycle at address (BA)XX01h in word mode (or (BA)XX02h in byte mode) returns the device code. „ A read cycle to an address containing a sector address (SA) within the same bank, and the address 02h on A7-A0 in word mode (or the address 04h on A6-A-1 in byte mode) returns 01h if the sector is protected, or 00h if it is unprotected. (Refer to Tabl es 3-4 for valid sector addresses). The system must write the reset command to return to reading array data (or erase-suspend-read mode if the bank was previously in Erase Suspend). Byte/Word Program Command Sequence The system may program the device by word or byte, depending on the state of the BYTE pin. Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table 12 shows the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, that bank then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using I/O 7, I/O6, or RY/ BY. Refer to the Write Operation Status section for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the progr am operation. The program command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from “0” back to a “1.” Attempting to do so may cause that bank to set I/O 5 = 1, or cause the I/O7 and I/O6 status bits to indicate the operation was successful. However, a succeeding read will show that the data is still “0.” Only erase operations can convert a “0” to a “1.”

PRELIMINARY (May, 2005, Version 0.0) 24 AMIC Technology, Corp.

  1. See Table 14 for erase command sequence.

Figure 4. Erase Operation

PRELIMINARY (May, 2005, Version 0.0) 25 AMIC Technology, Corp. Table 12. A29DL32x Command Definitions

555 AAA AAA

55 SA 30

RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data latches on the rising edge of WE or CE pulse, whichever happens first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A20 - A12 select a unique sector. BA = Address of the bank that is being switched to autoselect mode, is in bypass mode, or is being erased.

  1. See Table 1 for description of bus operations.
  2. All values are in hexadecimal.
  3. Except for the read cycle and the four th cycle of the autoselect command sequence, all bus cycles are write cycles.

15-I/O8 are don’t care in command sequences. Except for RD and PD.

  1. Unless otherwise noted, address bits A20-A11 are don’t cares.
  2. No unlock or command cycles required when bank is reading array data.
  3. The Reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in Erase

5 goes high (while the bank is providing status information).

  1. The fourth cycle of the autoselect co mmand sequence is a read cycle. The system must provide the bank address to obtain

section for more information.

  1. The data is 00h for an unprotect ed sector/sector block and 01h for a protected sector/sector block.
  2. The Unlock Bypass command is required prior to the Unlock Bypass Program Command.
  3. The Unlock Bypass Reset command is required to return to reading array data when the bank is in the unlock bypass mode.
  4. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode.

The Erase Suspend command is valid only during a sector erase operation, and require the bank address.

  1. The Erase Resume command is valid only during the Erase.
  2. Command is valid when device is ready to read array data or when device is in autoselect mode.
  3. Once a reset command is applied, software temporary unprotec t is exit to return to read array data. But under erase

deactivate the software temporary unprotect command is useful only after the erase command is complete.

PRELIMINARY (May, 2005, Version 0.0) 26 AMIC Technology, Corp. program or erase operation: I/O 2, I/O 3, I/O 5, I/O 6, and I/O 7. program or erase command sequence. on I/O 7 the complement of the datum programmed to I/O 7. complete, the device outputs the datum programmed to I/O 7. erasure to read valid status information on I/O7. sectors, and ignores the selected sectors that are protected. protected sector, the status may not be valid.

  1. VA = Valid address for programming. During a sector

address is any non-protected sector address. I/O7 may change simultaneously with I/O5. Figure 5. Data Polling Algorithm

PRELIMINARY (May, 2005, Version 0.0) 28 AMIC Technology, Corp. I/O2: Toggle Bit II The "Toggle Bit II" on I/O 2, when used with I/O 6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE pulse in the command sequence. I/O2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE or CE to control the read cycles.) But I/O 2 cannot distinguish whether the sect or is actively erasing or is erase-suspended. I/O6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required fo r sector and mode information. Refer to Table 8 to compare outputs for I/O2 and I/O6. Figure 6 shows the toggle bit algor ithm in flowchart form, and the section " I/O 2: Toggle Bit II" explains the algorithm. See also the " I/O 6: Toggle Bit I" subsection. Figure 20 shows the toggle bit timing diagram. Figure 21 shows the differences between I/O2 and I/O6 in graphical form. Reading Toggle Bits I/O6, I/O2 Refer to Figure 6 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read I/O7-I/O0 at least twice in a row to determine whether a toggle bit is toggling. Typically, a system would note and store the value of the toggle bit after the first read. After the second read, the system would compar e the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or eras e operation. The system can read array data on I/O7-I/O0 on the following read cycle. However, if after the initia l two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of I/O 5 is high (see the section on I/O 5). If it is, the system should then determine again whether the toggle bit is togg ling, since the toggle bit may have stopped toggling just as I/O 5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and I/O 5 has not gone high. The system may continue to monitor the toggle bit and I/O 5 through successive read cycles, determining the status as described in the previous paragr aph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 6). I/O5: Exceeded Timing Limits I/O5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions I/O5 produces a "1." This is a failure condition that indicates the program or erase cycle was not successfully completed. The device may output a “1” on I/O 5 if the system tries to program a “1” to a location that was previously programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the device halts the operation, and when the timing limit has been exceeded, I/O 5 produces a “1.” . Under both these conditions, the system must write the reset command to return to reading array data (or to the erase- suspend-read mode if a bank was previously in the erase- suspend-program mode). I/O3: Sector Erase Timer After writing a sector erase command sequence, the system may read I/O 3 to determine whether or not an erase operation has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entir e time-out also applies after each additional sector erase command. When the time-out is complete, I/O 3 switches from "0" to "1." The system may ignore I/O 3 if the system can guar antee that the time between additional sector erase commands will always be less than 50 µs. See also the "Sector Erase Command Sequence" section. After the sector erase command sequence is written, the system should read the status on I/O 7 ( Data Polling) or I/O6 (Toggle Bit 1) to ensure the device has accepted the command sequence, and then read I/O 3. If I/O 3 is "1", the internally controlled erase cycle has begun; all further commands (Except Erase Suspend) are ignored until the erase operation is complete. If I/O 3 is "0", the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of I/O 3 prior to and following each subsequent sector erase command. If I/O 3 is high on the second status check, the last command might not have been accepted. Table 13 shows the status of I/O 3 relative to the other status bits.

PRELIMINARY (May, 2005, Version 0.0) 29 AMIC Technology, Corp. Table 13. Write Operation Status

1 No toggle 0 N/A Toggle 1

  1. I/O5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

Refer to the section on I/O5 for more information.

  1. I/O7 and I/O2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
  2. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm

is in progress. The device outputs array data if the system addresses a non-busy bank.

PRELIMINARY (May, 2005, Version 0.0) 31 AMIC Technology, Corp. DC CHARACTERISTICS CMOS Compatible Parameter Symbol Parameter Description Test Description Min. Typ. Max. Unit ILI Input Load Current VIN = VSS to VCC. VCC = VCC Max ±1.0 µA ILIT A9 Input Load Current VCC = V CC Max, A9 =12.5V 35 µA ILO Output Leakage Current VOUT = VSS to VCC. VCC = VCC Max ±1.0 µA

5 MHz 10 16 CE = VIL, OE = VIH

5 MHz 10 16

ICC1 VCC Active Read Current (Notes 1, 2) CE = VIL, OE = VIH Word Mode 1 MHz 2 4 mA ICC2 VCC Active Write Current (Notes 2, 3) CE = VIL, OE =VIH 20 30 mA ICC3 VCC Standby Current (Note 2) CE = VIH, RESET= VCC ± 0.3V 0.2 5 µA ICC4 VCC Reset Current (Note 2) RESET= VSS ± 0.3V 0.2 5 µA ICC5 Automatic Sleep Mode (Note 2, 4) VIH = VCC ± 0.3V; VIL = VSS ± 0.3V 0.2 5 µA Byte 21 45 ICC6 VCC Active Read-While-Program Current (Notes 1, 2) CE = VIL, OE = VIH Word 21 45 mA Byte 21 45 ICC7 VCC Active Read-While-Erase Current (Notes 1, 2) CE = VIL, OE = VIH Word 21 45 mA ICC8 VCC Active Program-While-Erase-Suspended Current (Notes 2, 5) CE = VIL, OE = VIH 17 35 mA ACC pin 5 10 IACC ACC Accelerated Program Current, Word or Byte CE = VIL, OE = VIH VCC pin 15 30 mA VIL Input Low Level -0.5 0.8 V VIH Input High Level 0.7 x VCC VCC + 0.3 V VHH Voltage for WP /ACC Sector Protect/Unprotect and Program Acceleration VCC = 3.0 V ± 10% 8.5 9.5 V VID Voltage for Autoselect and Temporary Unprotect Sector VCC = 3.0 V ± 10% 8.5 12.5 V VOL Output Low Voltage IOL = 4.0mA, VCC = VCC Min 0.45 V VOH1 IOH = -2.0 mA, VCC = VCC Min 0.85 x VCC V VOH2 Output High Voltage IOH = -100 µA, VCC = VCC Min VCC - 0.4 V VLKO Low VCC Lock-Out Voltage (Note 5) 2.3 2.5 V Notes: 1. The ICC current listed is typically less than 2 mA/MHz, withOE at VIH. 2. Maximum ICC specifications are tested with VCC = VCC max. 3. ICC active while Embedded Algorithm (program or erase) is in progress. 4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30ns. Typical sleep mode current is 200nA. 5. Not 100% tested.

PRELIMINARY (May, 2005, Version 0.0) 33 AMIC Technology, Corp.

  1. See Figure 9 and Table 14 for test specifications.
  2. Measurements performed by placing a 50-ohm termination on the data pin with a bias of VCC/2. The time from OE high to

the data bus driven to VCC/2 is taken as tDF. Figure 11. Read Operation Timings

PRELIMINARY (May, 2005, Version 0.0) 34 AMIC Technology, Corp. Figure 12. RESET Timings

PRELIMINARY (May, 2005, Version 0.0) 36 AMIC Technology, Corp. AC CHARACTERISTICS Erase and Program Operations Parameter Speed JEDEC Std

Description

-70 -80 -90 -120 Unit tAVAV tWC Write Cycle Time (Note 1) Min. 70 80 90 120 ns tAVWL tAS Address Setup Time Min. 0 ns tASO Address Setup Time to OE low during toggle bit polling 15 15 15 15 ns tWLAX tAH Address Hold Time Min. 45 45 45 50 ns tAHT Address Hold Time From CE or OE high during toggle bit polling 0 ns tDVWH tDS Data Setup Time Min. 35 35 45 50 ns tWHDX tDH Data Hold Time Min. 0 ns tOEPH Output Enable High during toggle bit polling Min. 20 20 20 20 ns tGHWL tGHWL Read Recover Time Before Write (OE high to WE low) Min. 0 ns tELWL t CS CE Setup Time Min. 0 ns tWHEH tCH CE Hold Time Min. 0 ns tWLWH tWP Write Pulse Width Min. 30 30 35 50 ns tWHDL tWPH Write Pulse Width High Min. 30 30 30 30 ns tSR/W Latency Between Read and Write Operations Min. 0 Byte Typ. 5 tWHWH1 t WHWH1 Byte Programming Operation (Note 2) Word Typ. 7 µs tWHWH1 t WHWH1 Accelerated Programming Operation, Word or Byte (Note 2) Typ. 4 sec tWHWH2 t WHWH2 Sector Erase Operatio n (Note 2) Typ. 0.7 sec tvcs VCC Set Up Time (Note 1) Min. 50 µs tRB Recovery Time from RY/BY Min 0 ns tBUSY Program/Erase Valid to RY/BY Delay Min 90 ns Notes: 1. Not 100% tested. 2. See the "Erase and Programming Performance" section for more information.

PRELIMINARY (May, 2005, Version 0.0) 38 AMIC Technology, Corp.

  1. SA = Sector Address (for Sector Erase), VA = Valid Address for reading status data (see "Write Operaion Ststus").
  2. Illustration shows device in word mode.

Figure 17. Chip/Sector Erase Operation Timings

PRELIMINARY (May, 2005, Version 0.0) 41 AMIC Technology, Corp. Figure 22. Temporary Sector/Sector Block Unprotect Timing Diagram

PRELIMINARY (May, 2005, Version 0.0) 42 AMIC Technology, Corp. Figure 23. Sector/Sector Block Protect and Unprotect Timing Diagram

PRELIMINARY (May, 2005, Version 0.0) 43 AMIC Technology, Corp. AC CHARACTERISTICS Alternate CE Controlled Erase and Program Operations Parameter Speed JEDEC Std -70 -80 -90 -120 Unit tAVAV t WC Write Cycle Time (Note 1) Min. 70 80 90 120 ns tAVEL t AS Address Setup Time Min. 0 ns tELAX t AH Address Hold Time Min. 45 45 45 50 ns tDVEH t DS Data Setup Time Min. 35 35 45 50 ns tEHDX t DH Data Hold Time Min. 0 ns tGHEL t GHEL Read Recover Time Before Write (OE High to WE Low) Min. 0 ns tWLEL t WS WE Setup Time Min. 0 ns tEHWH t WH WE Hold Time Min. 0 ns tELEH t CP CE Pulse Width Min. 30 30 45 50 ns tEHEL t CPH CE Pulse Width High Min. 30 30 30 30 ns Byte Typ. 5 tWHWH1 t WHWH1 Programming Operation (Note 2) Word Typ. 7 µs tWHWH1 t WHWH1 Accelerated Programming Operation, Word or Byte (Note 2) Typ. 4 µs tWHWH2 t WHWH2 Sector Erase Operation (Note 2) Typ. 0.7 sec Notes: 1. Not 100% tested. 2. See the "Erase and Programming Perfo rmance" section for more information.

PRELIMINARY (May, 2005, Version 0.0) 44 AMIC Technology, Corp. Figure 24. Alternate CE Controlled Write (Erase/Program) Operation Timings

  1. Figure indicates last two bus cycl es of a program or erase operation.
  2. PA = program address, SA = sect or address, PD = program data.
  3. 7I/O is the complement of the data written to the device. DOUT is the data written to the device.
  4. Waveforms are for the word mode.

PRELIMINARY (May, 2005, Version 0.0) 45 AMIC Technology, Corp. ERASE AND PROGRAMMING PERFORMANCE Parameter Typ. (Note 1) Max. (Note 2) Unit Comments Sector Erase Time 0.7 15 sec Chip Erase Time 27 sec Excludes 00h programming prior to erasure (Note 4) Byte Programming Time 5 150 µs Word Programming Time 7 210 µs Accelerated Word/Byte Programming Time 4 120 µs Byte Mode 9 27 sec Chip Programming Time (Note 3) Word Mode 6 18 sec Excludes system-level overhead (Note 5) Notes: 1. Typical program and erase times assume the following conditions: 25°C, 3.0V VCC, 10,000 cycles. Additionally, programming typically assumes checkerboard pattern. 2. Under worst case conditions of 90°C, VCC = 2.7V, 100,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum byte program time listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 12 for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 10,000 cycles. LATCH-UP CHARACTERISTICS Description Min. Max. Input Voltage with respect to VSS on all I/O pins -1.0V VCC+1.0V VCC Current -100 mA +100 mA Input voltage with respect to VSS on all pins except I/O pins (including A9, OE and RESET) -1.0V 12.5V Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at time. PACKAGE AND PIN CAPACITANCE Parameter Symbol Parameter Description Test Setup Typ. Max. Unit TSOP 6 7.5 pF CIN Input Capacitance VIN=0 TF BGA 4.2 5 pF TSOP 8.5 12 pF COUT Output Capacitance VOUT=0 TF BGA 5.4 6.5 pF TSOP 7.5 9 pF CIN2 Control Pin Capacitance VIN=0 TF BGA 3.9 4.7 pF Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25°C, f = 1.0MHz DATA RETENTION Parameter Test Conditions Min Unit 150°C 10 Years Minimum Pattern Data Retention Time 125°C 20 Years

PRELIMINARY (May, 2005, Version 0.0) 46 AMIC Technology, Corp.

Ordering Information

Part No. Access Time (ns) Active Read Current Typ. (mA) Program/Erase Current Typ. (mA) Standby Current Typ. (µA) Package A29DL322TV-70 48 pin TSOP A29DL322TG-70 70 10 20 0.2 48 ball TFBGA A29DL322TV-80 48 pin TSOP A29DL322TG-80 80 10 20 0.2 48 ball TFBGA A29DL322TV-90 48 pin TSOP A29DL322TG-90 90 10 20 0.2 48 ball TFBGA A29DL322TV-120 48 pin TSOP A29DL322TG-120 120 10 20 0.2 48 ball TFBGA A29DL323TV-70 48 pin TSOP A29DL323TG-70 70 10 20 0.2 48 ball TFBGA A29DL323TV-80 48 pin TSOP A29DL323TG-80 80 10 20 0.2 48 ball TFBGA A29DL323TV-90 48 pin TSOP A29DL323TG-90 90 10 20 0.2 48 ball TFBGA A29DL323TV-120 48 pin TSOP A29DL323TG-120 120 10 20 0.2 48 ball TFBGA A29DL324TV-70 48 pin TSOP A29DL324TG-70 70 10 20 0.2 48 ball TFBGA A29DL324TV-80 48 pin TSOP A29DL324TG-80 80 10 20 0.2 48 ball TFBGA A29DL324TV-90 48 pin TSOP A29DL324TG-90 90 10 20 0.2 48 ball TFBGA A29DL324TV-120 48 pin TSOP A29DL324TG-120 120 10 20 0.2 48 ball TFBGA

PRELIMINARY (May, 2005, Version 0.0) 47 AMIC Technology, Corp. Ordering Information (continued) Bottom Boot Sector Flash Part No. Access Time (ns) Active Read Current Typ. (mA) Program/Erase Current Typ. (mA) Standby Current Typ. (µA) Package A29DL322UV-70 48 pin TSOP A29DL322UG-70 70 10 20 0.2 48 ball TFBGA A29DL322UV-80 48 pin TSOP A29DL322UG-80 80 10 20 0.2 48 ball TFBGA A29DL322UV-90 48 pin TSOP A29DL322UG-90 90 10 20 0.2 48 ball TFBGA A29DL322UV-120 48 pin TSOP A29DL322UG-120 120 10 20 0.2 48 ball TFBGA A29DL323UV-70 48 pin TSOP A29DL323UG-70 70 10 20 0.2 48 ball TFBGA A29DL323UV-80 48 pin TSOP A29DL323UG-80 80 10 20 0.2 48 ball TFBGA A29DL323UV-90 48 pin TSOP A29DL323UG-90 90 10 20 0.2 48 ball TFBGA A29DL323UV-120 48 pin TSOP A29DL323UG-120 120 10 20 0.2 48 ball TFBGA A29DL324UV-70 48 pin TSOP A29DL324UG-70 70 10 20 0.2 48 ball TFBGA A29DL324UV-80 48 pin TSOP A29DL324UG-80 80 10 20 0.2 48 ball TFBGA A29DL324UV-90 48 pin TSOP A29DL324UG-90 90 10 20 0.2 48 ball TFBGA A29DL324UV-120 48 pin TSOP A29DL324UG-120 120 10 20 0.2 48 ball TFBGA

PRELIMINARY (May, 2005, Version 0.0) 48 AMIC Technology, Corp.

Package Information

TSOP 48L (Type I) Outline Dimensions unit: inches/mm E c D L θ Detail "A" 0.25 24 25 D y eS A1 A2 A Detail "A" b Dimensions in inches Dimensions in mm Symbol Min Nom Max Min Nom Max A1 0.002 - 0.006 0.05 - 0.15 c 0.004 - 0.008 0.12 - 0.20 E - 0.472 0.476 - 12.00 12.10 e 0.020 BASIC 0.50 BASIC S 0.011 Typ. 0.28 Typ. θ 0° - 8° 0° - 8° Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension S includes end flash.

PRELIMINARY (May, 2005, Version 0.0) 49 AMIC Technology, Corp. 48LD CSP (6 x 8 mm) Outline Dimensions unit: mm (48TFBGA) H G F E D C B A TOP VIEW SIDE VIEW C SEATING PLANE 654321 BOTTOM VIEW Ball*A1 CORNER H G F E D C B A E e e D b 0.10 C A 123456 Dimensions in mm Symbol Min. Nom. Max. A - - 1.20 A1 0.20 0.25 0.30 b 0.30 - 0.40 D 5.90 6.00 6.10 D1 4.00 BSC e - 0.80 - E 7.90 8.00 8.10 E1 5.60 BSC