A29DL323 AMICC | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 46
Technical content
Features
n Two bank organization enabling simultaneous execution of erase / program and read n Bank organization: 2 banks (8 Mbits + 24 Mbits) n Memory organization: - 4,194,304 words x 8 bits (BYTE mode) - 2,097,152 words x 16 bits (WORD mode) n Sector organization: 71 sectors (8 Kbytes / 4 Kwords × 8 sectors, 64 Kbytes /
32 Kwords × 63 sectors)
n 2 types of sector organization - T type: Boot sector allocated to the highest address (sector) - B type: Boot sector allocated to the lowest address (sector) n 3-state output n Automatic program - Program suspend / resume n Unlock bypass program n Automatic erase - Chip erase - Sector erase (sectors can be combined freely) n Erase suspend / resume n Program / Erase completion detection - Detection through data polling and toggle bits - Detection through RY/BY pin n Sector group protection - Any sector group can be protected - Any protected sector group can be temporary unprotected n Sectors can be used for boot application n Hardware reset and standby using RESET pin n Automatic sleep mode n Boot block sector protect by WP (ACC) pin n Conforms to common flash memory interface (CFI) n Extra One Time Protect Sector provided Part No. Access time (Max.) Operating supply voltage Power supply current (Active mode) (Max.) Standby current (Max.) A29DL323 90ns 2.7V~ 3.6V 16mA 30mA 5A n Operating ambient temperature: -40 to 85°C n Program / erase time - Program: 9.0 µs / byte (TYP.) 11.0 µs / word (TYP.) - Sector erase: 0.7 s (TYP.) n Number of program / erase: 1,000,000 times (MIN.) n Package options - 48-pin TSOP (I) or 63-ball TFBGA General Description The A29DL323 is a flash memory organized of 33,554,432 bits and 71 sectors. Sectors of this memory can be erased at a low voltage (2.7 to 3.6 V) supplied from a single power source, or the contents of the entire chip can be erased. Two modes of memory organization, BYTE mode (4,194,304 words × 8 bits) and WORD mode (2,097,152 words × 16 bits), are selectable so that the memory can be programmed in byte or word units. The A29DL323 can be read while its contents are being erased or programmed. The memory cell is divided into two banks. While sectors in one bank are being erased or programmed, data can be read from the other bank thanks to the simultaneous execution architecture. The banks are 8 Mbits and 24 Mbits. This flash memory comes in two types. The T type has a boot sector located at the highest address (sector) and the B type has a boot sector at the lowest address (sector). Because the A29DL323 enables the boot sector to be erased, it is ideal for storing a boot program. In additio n, program code that controls the flash memory can be also stored, and the program code can be programmed or erased without the need to load it into RAM. Eight small sectors for storing parameters are provided, each of which can be erased in 8 Kbytes units. Once a program or erase command sequence has been executed, an automatic program or automatic erase function internally executes program or erase and verification automatically. Because the A29DL323 can be electrically erased or programmed by writing an instruction, data can be reprogrammed on -board after the flash memory has been installed in a system, making it suitable for a wide range of applications.
PRELIMINARY (May, 2002, Version 0.0) 2 AMIC Technology, Inc. Pin Configurations n TSOP (I) A29DL323V A14 A13 A12 A11 A10 A20 WE RESET NC WP (ACC) RY/BY A18
33 I/O
I/O 15 (A-1) GND BYTE A16A15 A19 24 25
32 I/O 9
n TFBGA Top View Bottom View A B C D E F G H J K L M A BC DEFGHJKLM Top View A B C D E F G H J K L M
1 NC NC NC NC
2 NC NC A13 A12 A14 A15 A16 BYTE I/O15(A-1) GND NC NC
3 A9 A8 A10 A11 I/O7 I/O14 I/O13 I/O6
4 WE RESET NC A19 I/O5 I/O12 VCC I/O4
5 RY/BY WP (ACC) A18 A20 I/O2 I/O10 I/O11 I/O3
6 A7 A17 A6 A5 I/O0 I/O8 I/O9 I/O1
7 NC A3 A4 A2 A1 A0 CE OE GND NC NC
8 NC NC NC NC
PRELIMINARY (May, 2002, Version 0.0) 3 AMIC Technology, Inc. Block Diagram Address Buffers Bank / Sector Decoder State Control (Command Register) Address LatchAddress Latch X-Decoder Y-Decoder Cell Matrix (Bank 1) Y-Gating X-Decoder Y-Decoder Cell Matrix (Bank 2) Y-Gating SA / WC Data Latch SA / WC Input / Output Buffers I/O0 - I/O15 (A-1)WP(ACC) A0-A20 VCC GND RY/BY Bank 1 Address RESET WE BYTE CE OE Bank 2 Address Program / Erase Voltage Generator Pin Descriptions Pin No. Description A0 – A20 Address Inputs I/O0 - I/O14 Data Inputs/Outputs I/O15 Data Input/Output, Word Mode I/O15 (A-1) A-1 LSB Address Input, Byte Mode CE Chip Enable WE Write Enable OE Output Enable RESET Hardware Reset Input BYTE Mode Select RY/BY Ready/BUSY- Output WP (ACC) Write Protect (Accelerated) Input GND Ground VCC Power Supply NC Note No Connection Note: Some signals can be applied because this pin is not connected to the inside of the chip.
PRELIMINARY (May, 2002, Version 0.0) 4 AMIC Technology, Inc. Input / Output Pin Function Pin Name Input / Output Function A0 to A20 Input Address input pins. A0 to A20 are used differently in the BYTE mode and the WORD mode. BYTE MODE A0 to A20 are used as the upper 21 bits of total 22 bits of address input pin. (The least significant bit (A-1) is combined to I/O15.) WORD MODE A0 to A20 are used as 21 bits address input pin. I/O0 to I/O14 Input / Output Data input / output pins. I/O0 to I/O14 are used differently in the BYTE mode and the WORD mode. BYTE MODE I/O0 to I/O7 are used as the 8 bits data input / output pins. I/O8 to I/O14 are Hi-Z. WORD MODE I/O0 to I/O14 are used as the lower 15 bits of total 16 bits of data input / output pins. (The most significant bit (I/O15) is combined to A -1.) I/O15, A-1 Input / Output I/O15, A1 are used differently in the BYTE mode and the WORD mode . BYTE MODE The least significant address input pin (A-1) WORD MODE The most significant data input / output pin (I/O 15) CE Input This pin inputs the signal that activates the chip. When high level, the chip enters the standby mode. OE Input This pin inputs the read operation control signal. When high level, output is Hi -Z. WE Input This pin inputs the write operation control signal. When low level, command input is accepted. BYTE Input The pin for switching BYTE mode and WORD mode. High level : WORD MODE (2M words x 16 bits) Low level : BYTE MODE (4M words x 8 bits) RESET Input This pin inputs hardware reset. When low level, hardware reset is performed. If 11.5 to 12.5 V is applied to RESET, the chip enters the temporary sector group unprotect mode. RY/BY Output This pin indicates whether automatic program / erase is currently being executed. It uses open drain connection. Low level indicates the busy state during which the device is performing automatic program erase. High level indicates the device is in the ready state and will accept the next operation. In this case, the device is either in the erase suspend mod e or the standby mode. WP (ACC) Input This pin selects the boot block sector protect mode or accelerated mode. Low level: The boot block (2 sectors) is protected. High level: The boot block is unprotected. VACC level: Accelerated mode is selected. VCC - Supply Voltage GND - Ground NC - No Connection
PRELIMINARY (May, 2002, Version 0.0) 5 AMIC Technology, Inc.
- VCC + 0.5V (Max.) (Pulse width ≤ 20ns)
Ratings" may cause permanent damage to this device. periods may affect device reliability. RESET until VCC ≥ VCC (min.). Table 1. A29DL323 Bus Operations Note: When OE = VIL, VIL can be applied to WE . When OE = VIH, a write operation is started.
- If an address is held longer than the minimum read cycle time (t RC), the automatic sleep mode is set.
- If WP (ACC)=VIL, sector 0,1,140, and 141 remain protected. If WP (ACC)=VIH, protection on sectors 0,1,140, and 141
Protection and Unprotection”. If WP (ACC)=VHH, all sectors will be unprotected.
PRELIMINARY (May, 2002, Version 0.0) 6 AMIC Technology, Inc. Read Operation The read operation is controlled by the OE and /OE. The /CE is used to select a device, and t he OE controls data output. The following three access times are used depending on the condition. - Address access time (t ACC): Time until valid data is output after an address has been determined (however, after CE ). - CE access time (t CE): Time until valid data is output after CE has been determined (however, after address). - OE access time (t OE): Time until valid data is output after OE has been determined (however, OE must be input after t ACC-tOE, t CE-tOE after address and CE have been determined). On power -up, the device is automatically set in the read mode. To read the device without changin g address immediately after power application, either execute hardware reset or briefly lower CE to VIL from VIH. For the timing waveform, refer to Timing Waveform for Read Cycle (1). Write Operation The operation of the device is con trolled by writing commands to the registers. The command register is a function that latches the address and data necessary for executing an instruction and does not occupy the memory area. If an illegal address or data is written or if an address or data is written in the wrong sequence, the device is reset to the read mode. Standby Mode The standby mode is set when V IH is input to the CE . The current consumption in the standby mode can be lowered to 5 µA or less in two ways. One is t o use CE and RESET. Input VCC ± 0.3 V to CE and RESET . However, while automatic programming or erasing is being executed, the operating supply current (ICC2) does not decrease t o 5µA or lower even if CE = VIH. If a read operation is executed in the standby mode, data is output at CE access time. The other is to input GND ± 0.3 V to the RESET. At this time, the level of CE is V IH or V IL. In this case, t RH is required for the device to return to the read mode from the standby mode. For the timing waveform, refer to Timing Waveform for Read Cycle (2). Hardware Reset Pin The device is reset to the read mode if V IL is input to the RESET for the duration of t RP and V IH for the duration of tRH. While V IL is being input to the RESET, all commands are ignored, and the output pins go into a Hi -Z state. If the voltage on RESET is kept to GND ± 0.2 V at this time, the current consumption can be lowered to 5 µA or less. If V IH is input to the RESET, tREADY is required until data is output. For the timing waveform, refer to Timing Waveform for Read Cycle (2). Output Disable Mode Output from the device is disabled (Hi -Z state) if VIH is input to the OE . Sector Group Protection Protect the sector group by using a command. OE or WE control is no need. Temporary Sector Group Unprotect Protection of a sector group can be temporarily canceled. When V ID is input to RESET, the temporary sector group unprotect mode is set. If a protected sector is selected in this mode, it can be programmed or erased. If the mode is canceled, the sector group is protected again. For the timing waveform, refer to Timing Waveform for Temporary Sector Group Unprotect. Product ID Read the product ID code by using a command. Automatic Sleep Mode The automatic sleep mode is used to reduce the power consumption substantially during a read operation. If an address is held longer than the minimum read cycle time (t RC), the sleep mode (low power consumption mode) is automatically set. In this mode, the output data is latched and continuously output. In the automatic sleep mode, CE , WE , and OE do not have to be controlled. At this time, the current consumption decreases to 5 µA or less. Du ring dual operation, however, the current consumption is power supply current (ICC6, ICC7). If the address is changed, the automatic sleep mode is canceled automatically, the device returns to the read mode, and the data of the newly input address is output.
PRELIMINARY (May, 2002, Version 0.0) 7 AMIC Technology, Inc. and the programming time can be shortened to about 60%. programming or detection of completion of programming. be executed at the same time in the same bank. Table 2. Dual Operation
1 Read mode Read mode
2 Read mode Product ID
3 Read mode Program (Note 1)
4 Read mode Erase (Note 2)
5 Product ID Read mode
6 Program (Note 1) Read mode
7 Erase (Note 2) Read mode
being programmed to at this time can only be read.
- The erase operation is suspended by the erase suspend command. The sector not erased at
this time can be read or programmed.
PRELIMINARY (May, 2002, Version 0.0) 8 AMIC Technology, Inc. Table 3. A29DL323 Top Boot Block Sector Address Table
PRELIMINARY (May, 2002, Version 0.0) 9 AMIC Technology, Inc. Table 3. A29DL323 Top Boot Block Sector Address Table (continued)
PRELIMINARY (May, 2002, Version 0.0) 10 AMIC Technology, Inc. Table 4. A29DL323 Bottom Boot Block Sector Address Table
PRELIMINARY (May, 2002, Version 0.0) 11 AMIC Technology, Inc. Table 4. A29DL323 Bottom Boot Block Sector Address Table (continued)
PRELIMINARY (May, 2002, Version 0.0) 12 AMIC Technology, Inc. Table 5. A29DL323 Top Boot Sector Group Address Table
PRELIMINARY (May, 2002, Version 0.0) 13 AMIC Technology, Inc. Table 6. A29DL323 Bottom Boot Sector Group Address Table
PRELIMINARY (May, 2002, Version 0.0) 14 AMIC Technology, Inc. Table 7. A29DL323 Product ID Code (Manufacture Code / Device Code)
- If 01H is output, the sector group is protected. If 00H is output, the sector group is unprotected.
PRELIMINARY (May, 2002, Version 0.0) 15 AMIC Technology, Inc. Sector Group Protection This command performs sector group protection. By applying V ID to RESET and writing 60H to any address, the device enters the sector group protection mode. Sector group protection is started by inputting the sector group address of the sector group to be protected to A12 to A20, inputting (A6, A1, A0) = (V IL, VIH, VIL), and writing 60H. After a timeout of 250 µs, sector group p rotection is completed. Next, with the sector group address input to A12 to A20, the device enters the sector group protection verify mode by inputting (A6, A1, A0) = (VIL, VIH, VIL), and writing 40H. When read is performed in this state, the sector group protection verify result is output to I/O0. If "1" is output to I/O0, the verified sector group is protected. If "1" was not output to I/O0, sector group protection failed, so perform sector group protection again. For the timing waveform and flow chart , refer to Timing Waveform for Sector Group Protection and Figure 1. Sector Group Unprotect This command performs sector group unprotect. Sector group unprotect is performed for all sector group. Unprotect cannot be performed for specific sector group. Moreover, all sector groups must be protected priors to unprotect. The device enters the sector group unprotect mode by applying VID to RESET and writing 60H to any address. If unprotected sector group exist, first perform sector group protection for these sector groups. To protect a sector group, input the sector group address of the sector group to be protected to the sector group address input pin, input (A6, A1, A0) = (VIL, VIH, VIL), and write 60H (refer to Sector Group Protection). Sector group unprotect is started by inputting (A6, A1, A0) = (VIH, VIH, VIL), and writing 60H to any address. Following a timeout of 15 ms, sector group unprotect is completed. Unprotect verification must be performed for each sector group. The device ente rs the sector group unprotect verification mode by inputting the sector group address to input pin of sector group address and writing 40H, with input (A6, A1, A0) = (VIH, VIH, VIL). If reading is performed in this state, the sector group unprotect verific ation result is output to I/O 0. If the verified sector group is unprotected, "0" is output to I/O 0. If "0" is not output to I/O 0, this means that unprotect failed, so perform sector group unprotect again. For the flow chart, refer to Figure 2. Sector Gro up Unprotect Flow Chart. Query The dual operation flash memory conforms to CFI (Common Flash memory Interface). CFI enables information about a device such as the device specifications, memory density, and supply voltage to be read. Therefore, the softwa re of the host system can support the software algorithm of a specific vendor used by a device by using the CFI. For details, refer to the CFI specifications. By writing the Query command (98H) and giving an address, the device information corresponding t o that address can be read. If the device information is read in the WORD mode (16 bits), the upper bytes of data (I/O15 to I/O8) are "0". To end the Query mode, writes the read / reset command. Extra One Time Protect Sector Entry The dual operation flas h memory has a sector area that has One Time Protect function. This area does not allow code that has been written to the area to be changed. This area can be programmed or erased until it is protected. Once it has been protected, however, protection can n ever be canceled. Therefore, care must be exercised when using this area. The Extra One Time Protect Sector area has a density of 64 Kbytes and exits at the same addresses as the 8 Kbytes sector. These addresses are 3F0000H to 3FFFFFH for top boot in the BYTE mode (1F8000H to 1FFFFFH in the WORD mode), and 000000H to 00FFFFH for bottom boot in the BYTE mode (000000H to 007FFFH in the WORD mode). Because boot block areas (8 Kbytes x 8 sectors) usually appear in the areas of these addresses, the Extra One Tim e Protect Sector entry command sequence must be written to enter them as the Extra One Time Protect Sector area. The status in which the Extra One Time Protect Sector area appears is the Extra One Time Protect Sector mode. In the Extra One Time Protect Sec tor mode, the other sectors, except the boot block area, can be read. In addition, the Extra One Time Protect Sector area can be read, programmed, or erased in this mode. To exit from the Extra One Time Protect Sector mode, the Extra One Time Protect Sector Reset command sequence must be written. Extra One Time Protect Sector Program To program data to the Extra One Time Protect Sector area, write the Extra One Time Protect Sector Program command sequence in the Extra One Time Protect Sector mode. This command is no different from the conventional program command except that it must be written in the Extra One Time Protect Sector mode. Therefore, completion of execution of this command is detected in the same manner as the conventional detection method of using I/O 7 data polling, I/O6 toggle bit, and RY/ BY. Care must be exercised in selecting a program destination address. If a program destination address other than the one in the Extra One Time Protect Sector area is selected, the data of that address is changed.
PRELIMINARY (May, 2002, Version 0.0) 16 AMIC Technology, Inc. Extra One Time Protect Sector Erase To erase the Extra One Time Protect Sector area, write the Extra One Time Protect Sector erase command sequence in the Extra One Time Protect Sector mode. This command is the same as the con ventional sector erase command except that it must be written in the Extra One Time Protect Sector mode. Therefore, completion of execution of this command is detected in the same manner as the conventional detection method of using I/O 7 data polling, I/O 6 toggle bit, and RY/ BY . Care must be exercised in selecting a sector address to erase. If a sector address other than the one in the Extra One Time Protect Sector area is selected, the data of that sector is changed. Extra One Time Protect Sector Protection The following write operations are used to protect the Extra One Time Protect area during the Extra One Time Protect Sector mode. Write the sector group protection setup command (60H) in the Extra One Time Protect Sector mode. . Set (A6, A1, A0) = (V IL, VIH, VIL), and set the sector address that selects the Extra One Time Protect Sector. . Write the sector group protection command (60H). Because the sequence is the same as the conventional command sequence to protect a sector group except that the Extra One Time Protect Sector mode must be set and that VID is not input to the RESET , the same command sequence can be used. For details of how to protect a sector group, refer to Sector Group Protection. If an address o ther than the one of the Extra One Time Protect Sector area is specified as a sector address, the other sectors are affected. Once the sector has been protected, protection can never be canceled. Exercise utmost care when protecting a sector. Hardware Data Protection This device requires two unlock cycles for program / erase command sequence to prevent illegal program / erase. Moreover, a hardware data protect function is provided as follows. Low VCC Write Inhibit To prevent an illegal write cycle during VCC transition, the command register and program / erase circuit is disabled and all write cycles are ignored while VCC is V LKO or lower. Write commands are ignored until VCC becomes equal to or greater than VLKO. Logical Inhibit The write cycle is inhibi ted under any of the following conditions : OE = V IL, CE = V IH, or WE = V IH. To start a write cycle, CE = VIL and WE = VIL must be set while /OE = VIH. Power-Up Write Inhibit Even if WE = CE = V IL and OE = V IH are satisfied at power-up, no commands are accepted at the rising edge of WE . The device is automatically reset to the read mode at power ON. Write Pulse "Glitch" Protection Because OE , CE , and /WE reject a noise pulse of 5 ns (typical) or less as an invalid pulse, a write operation is not started. Sector Group Protection The dual operation flash memory can be protected by the user in sector group units. For details, refer to Sector Group Protection.
PRELIMINARY (May, 2002, Version 0.0) 17 AMIC Technology, Inc. Figure 1. Sector Group Protection Flow Chart
PRELIMINARY (May, 2002, Version 0.0) 18 AMIC Technology, Inc. Figure 2. Sector Group Unprotect Flow Chart
PRELIMINARY (May, 2002, Version 0.0) 19 AMIC Technology, Inc. CFI Code List Address A6 to A0 Data I/O15 to I/O0 Description 10H 11H 12H 0051H 0052H 0059H "QRY" (ASCII code) 13H 14H 0002H 0000H Main command set 2 : AMD/FJ standard type 15H 16H 0040H 0000H Start address of PRIMARY table 17H 18H 0000H 0000H Auxiliary command set 00H : Not supported 19H 1AH 0000H 0000H Start address of auxiliary algorithm table 1BH 0027H Minimum VCC voltage (program / erase) I/O7 to I/O4 : 1 V/bit I/O3 to I/O0 : 100 mV/bit 1CH 0036H Maximum VCC voltage (program / erase) I/O7 to I/O4 : 1 V/bit I/O3 to I/O0 : 100 mV/bit 1DH 0000H Minimum VPP voltage 1EH 0000H Maximum VPP voltage 1FH 0004H Typical word program time (2N µs) 20H 0000H Typical buffer program time (2N µs) 21H 000AH Typical sector erase time (2N ms) 22H 0000H Typical chip erase time (2N ms) 23H 0005H Maximum word program time (typical time × 2N) 24H 0000H Maximum buffer program time (typical time × 2N) 25H 0004H Maximum sector erasing time (typical time × 2N) 26H 0000H Maximum chip erasing time (typical time × 2N) 27H 0016H Capacity (2N Bytes) 28H 29H 0002H 0000H I/O information 2 : ×8/×16-bit organization 2AH 2BH 0000H 0000H Maximum number of bytes when two banks are programmed (2N) 2CH 0002H Type of erase block 2DH 2EH 2FH 30H 0007H 0000H 0020H 0000H Information about erase block 1 Bit0 to 15 : y = number of sectors Bit16 to 31 : z = size (Z × 256 Bytes) 31H 32H 33H 34H 003EH 0000H 0000H 0001H Information about erase block 2 bit0 to 15 : y = number of sectors bit16 to 31 : z = size (z × 256 Bytes) 40H 41H 42H 0050H 0052H 0049H "PRI" (ASCII code)
PRELIMINARY (May, 2002, Version 0.0) 20 AMIC Technology, Inc. CFI Code List (continued) Address A6 to A0 Data I/O15 to I/O0 Description 43H 0031H Main version (ASCII code) 44H 0032H Minor version (ASCII code) 45H 0000H Address during command input 00H : Necessary 01H : Unnecessary 46H 0002H Temporary erase suspend function 00H : Not supported 01H : Read only 02H : Read / Program 47H 0001H Sector group protection 00H : Not supported 01H : Supported 48H 0001H Temporary sector group protection 00H : Not supported 01H : Supported 49H 0004H Sector group protection algorithm 4AH 00XXH Number of sectors of bank 2 00H : Not supported 30H : A29DL323 4BH 0000H Burst mode 00H : Not supported 4CH 0000H Page mode 00H : Not supported 4DH 0085H Minimum VACC voltage I/O7 to I/O4 : 1 V/bit I/O3 to I/O0 : 100 mV/bit 4EH 0095H Maximum VACC voltage I/O7 to I/O4 : 1 V/bit I/O3 to I/O0 : 100 mV/bit 4FH 00XXH Boot organization 02H : Bottom boot (A29DL323UX-XX) 03H : Top boot (A29DL323TX-XX) 50H 0001H Temporary program suspend function 00H : Not supported 01H : Supported
PRELIMINARY (May, 2002, Version 0.0) 21 AMIC Technology, Inc. All operations are executed by writing a command. instruction and does not occupy the memory area. Table 8. shows the commands and command sequences. This command resets the device to the read mode. command register are changed. using the read cycle of a standard microprocessor. command register are changed. inputting a high voltage to the address pin. of the memory cell is output. is protected (for details refer to Sector Group Protection). This command is used to program data. polling, but actually the data is "0" as before. control from external is not required. the program command following completion of reset. Waveform for Write Cycle ( CE Controlled) and Figure 3. Figure 3. Program Flow Chart
PRELIMINARY (May, 2002, Version 0.0) 22 AMIC Technology, Inc. This command is used to suspend automatic programming. pins.) refer to I/O7 (Data polling) and I/O6 (Toggle Bit). command (30H) while the operation is suspended. This command is used to erase the entire chip. before erase and control from external are not required. command again after reset is completed. and “RY/BY (Ready / Busy )”. Waveform for Sector / Chip Erase and Figure 4. This command is used to erase data in sector units. has elapsed, the device automatically starts erasing. after the last erase command has been written. protected is erased and the protected sector is ignored. reset is executed. In this case, sector erase is not guaranteed. bank (i.e., dual operation) cannot be executed. Waveform for Sector / Chip Erase and Figure 4. Figure 4. Sector / Chip Erase Flow Chart
PRELIMINARY (May, 2002, Version 0.0) 23 AMIC Technology, Inc. sectors for which erase is being performed. automatic erase is suspended. erase is not being performed can be read and programmed. mode, it is possible to perform program without unlock cycles. bypass program and unlock bypass reset are ignored. For the flowchart, refer to Figure 5. This command sets the device to the unlock bypass mode. This command is used to quit the unlock bypass mode. Figure 5. Unlock Bypass Flow Chart (WORD Mode) mode, address to be input is different from the WORD mode.
PRELIMINARY (May, 2002, Version 0.0) 24 AMIC Technology, Inc. Table 8. A29DL323 Command Sequence
4 XXXH 60H EOTPSA 60H EOTPSA 40H EOTPSA SD - - - -
- Both these read / reset commands reset the device to the read mode.
- Programming is suspended if B0H is input to the bank address being programmed to in a program operation.
- Programming is resumed if 30H is input to the bank address being suspended to in a program -suspend operation.
- Erasure is suspended if B0H is input to the bank address being erased in a sector erase operation.
- Erasure is resumed if 30H is input to the bank address being suspended in a sector -erase-suspend operation.
- Valid only in the unlock bypass mode.
- Valid only when RESET = VID (except in the Extra One Time Protect Sector mode).
- The command sequence that protects a sector group is excluded.
PRELIMINARY (May, 2002, Version 0.0) 25 AMIC Technology, Inc. 9. Only A0 to A6 are valid as an address. 10. Valid only in the Extra One Time Protect Sector mode. 11. This command can be used even if this data is F0H. Remarks: 1. Specify address 555H or 2AAH (A10 to A0) in the WORD mode, and AAAH or 555H (A10 to A0, A -1) in the BYTE mode. 2. RA : Read address RD : Read data IA : Address input xx00H (to read the manufacturer code) xx02H (to read the device code in the BYTE mode) xx01H (to read the device code in the WORD mode) ID : Code output. Refer to the Product ID code (Manufacturer code / Device code). PA : Program address PD : Program data FSA: Erase sector address. The sector to be erased is selected by the comb ination of this address. Refer to the Sector Organization / Sector Address Table. BA : Bank address. Refer to the Sector Organization / Sector Address Table. SPA : Sector group address to be protected. Set sector group address (SGA) and (A6, A1, A0) = ( VIL, VIH, VIL). SUA : Unprotect sector group address. Set sector group address (SGA) and (A6, A1, A0) = (V IH, VIH, VIL). EOTPSA : Extra One Time Protect Sector area addresses. These addresses are 3F0000H to 3FFFFFH (BYTE mode) / 1F8000H to 1FFFFFH (WORD mode) for top boot, and 000000H to 00FFFFH (BYTE mode) / 000000H to 007FFFH (WORD mode) for bottom boot. SD : Data for verifying whether sector groups read from the address specified by SPA, SUA, and EOTPSA are protected or unprotected. 3. The sector group address is don't care except when a program / erase address or read address are selected. 4. × of address bit indicates VIH or VIL.
PRELIMINARY (May, 2002, Version 0.0) 26 AMIC Technology, Inc. CE or change the address before reading the data. data may not be output correctly. program / erase command sequence. programmed data, not the complement, is output. erasure is suspended is read. protected, data polling is valid for approximately 400 µs. OE is maintained at low level. Waveform for Data Polling and Figure 6. status of automatic program / erase is in progress. program / erase command sequence. read control is performed with the OE or CE . device is reset to the read mode. and then the device is reset to the read mode. II) is used. See section “I/O2 (Toggle Bit II)”. Figure 6. Data Polling Flow Chart
PRELIMINARY (May, 2002, Version 0.0) 27 AMIC Technology, Inc. particular sector by using I/O2. address in a sector other than an erased sector. progress or erase suspend cannot be determined with I/O 2. section “I/O6 (Toggle Bit)”. I/O5 when the timing limit is exceeded. When this happens, execute com mand reset. erase command sequence before automatic erase starts. period, "1" is output to I/O3. erase suspend) are ignored until erase is completed. that addition may not be accepted. status of automatic program / erase is in progress. the read mode (including erase suspend) or standby mode. Figure 7. Toggle Bit Flow Chart
PRELIMINARY (May, 2002, Version 0.0) 28 AMIC Technology, Inc. Table 9. Hardware Sequence Flags
- To read I/O7 or I/O2, a valid address must be input.
- To read I/O6, any address can be used.
- For I/O5, “1” is output if the automatic program / erase time exceeds the prescribed number of internal pulses.
PRELIMINARY (May, 2002, Version 0.0) 29 AMIC Technology, Inc.
Electrical Characteristics
Before turning on power, input GND ± 0.2 V to the RESET pin until VCC VCC (MIN.). DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) Parameter Symbol Test Description Min. Typ. Max. Unit High level input voltage VIH 2.4 VCC+0.3 V Low level input voltage VIL -0.3 +0.5 V High level output voltage VOH IOH = -500 µA, VCC = VCC (min.) 2.4 V Low level output voltage VOL IOL = +1.0 mA, VCC = VCC (min.) 0.4 V Input leakage current ILI -1.0 +1.0 µA Output leakage current ILO -1.0 +1.0 µA tCYCLE = 5 MHz 10 16 BYTE mode tCYCLE = 1 MHz 2 4 tCYCLE = 5 MHz 10 16 Read WORD mode ICC1 VCC = VCC (max.), CE = VIL, OE = VIH tCYCLE = 1 MHz 2 4 mA Program, Erase ICC2 VCC = VCC (max.), CE = VIL, OE = VIH 15 30 mA Standby ICC3 VCC = VCC (max.), CE = RESET = WP (ACC) = VCC ± 0.3 V, OE = VIL 0.2 5 µA Standby / Reset ICC4 VCC = VCC (max.), RESET = GND ± 0.2 V 0.2 5 µA Automatic sleep mode ICC5 VIH = VCC ± 0.2 V, VIL = GND ± 0.2 V 0.2 5 µA Read during programming ICC6 VIH = VCC ± 0.2 V, VIL = GND ± 0.2 V 21 45 mA Read during erasing ICC7 VIH = VCC ± 0.2 V, VIL = GND ± 0.2 V 21 45 mA Programming during suspend ICC8 CE = VIL, OE = VIH, Automatic programming during suspend 17 35 mA WP (ACC) pin 5 10 Power Supply Current Accelerated programming IACC VCC 15 30 mA RESET high level input voltage VID High Voltage is applied 11.5 12.5 V Accelerated programming voltage VACC High Voltage is applied 8.5 9.5 V Low VCC lock-out voltage (Note) VLKO VIH = VCC ± 0.3V; VIL = VSS ± 0.3V 1.7 V Notes: 1. When VCC is equal to or lower than VLKO, the device ignores all write cycles. Remark: These DC characteristics are in common regardless of product classification.
PRELIMINARY (May, 2002, Version 0.0) 30 AMIC Technology, Inc. AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) AC Test Conditions Input Waveform (Rise and Fall Time 5 ns) 3.0V 1.5V 1.5VTest points Output Waveform 1.5V 1.5VTest points Output Load
1 TTL + 30pF
Parameter Symbol Test Condition Min. Typ. Max. Unit Notes Read cycle time tRC 85 ns Address access time tACC CE = OE = VIL 85 ns CE access time tCE OE = VIL 85 ns OE access time tOE CE = VIL 40 ns Output disable time tDF OE = VIL or CE = VIL 30 ns Output hold time tOH 0 ns RESET pulse width tRP 500 ns RESET hold time before read tRH 50 ns RESET low to read mode tREADY 20 µs CE low to /BYTE low, high tELFL/tELFH 5 ns BYTE low output disable time tFLQZ 30 ns BYTE high access time tFHQV 85 ns Remark: tDF is the time from inactivation of CE or OE to Hi-Z state output.
PRELIMINARY (May, 2002, Version 0.0) 31 AMIC Technology, Inc. AC Characteristics Write Cycle (Program / Erase) Parameter Symbol Min. Typ. Max. Unit Notes Write cycle time tWC 85 ns Address setup time ( WE to address) tAC 0 ns Address setup time ( CE to address) tAS 0 ns Address hold time ( WE to address) tAH 45 ns Address hold time ( CE to address) tAH 45 ns Input data setup time tDS 35 ns Input data hold time tDH 0 ns Read 0 OE hold time Toggle bit, Data polling tOEH ns Read recovery time before write ( OE to CE ) tGHEL 0 ns Read recovery time before write ( OE to WE ) tGHWL 0 ns WE setup time ( CE to WE ) tWS 0 ns CE setup time ( WE to CE ) tCS 0 ns WE hold time ( CE to WE ) tWH 0 ns CE hold time ( WE to CE ) tCH 0 ns Write pulse width tWP 35 ns CE pulse width tCP 35 ns Write pulse width high tWPH 30 ns CE pulse width high tCPH 30 ns Byte programming operation time tBPG 9 200 µs Word programming operation time tWPG 11 200 µs Sector erase operation time tSER 0.7 5 s 1 VCC set time tVCS 50 µs RY/BY recovery time tRB 0 ns RESET pulse width tRP 500 ns RESET high-voltage (VID) hold time from high of RY/ BY when sector group is temporarily unprotect tRRB 20 µs RESET hold time tRH 50 ns From completion of automatic program / erase to data output time tEOE 85 ns RY/BY delay time from valid program or erase operation tBUSY 90 ns Address setup time to OE low in toggle bit tASO 15 ns Address hold time to CE or OE high in toggle bit tAHT 0 ns
PRELIMINARY (May, 2002, Version 0.0) 32 AMIC Technology, Inc. Write Cycle (Program / Erase) (continued) Parameter Symbol Min. Typ. Max. Unit Notes CE pulse width high for toggle bit tCEPH 20 ns OE pulse width high for toggle bit tOEPH 20 ns Voltage transition time tVLHT 4 µs 2 Rise time to VID (RESET) tVIDR 500 ns 3 Rise time to VACC ( WE (ACC)) tVACCR 500 ns 2 Erase timeout time tTOW 50 µs 4 Erase suspend transition time tSPD 20 µs 4 Notes: 1. The preprogramming time prior to the erase operation is not included. 2. Sector group protection and accelerated mode only. 3. Sector group protection only. 4. Table only. Write operation (Erase / Program) Performance Parameter Description Min. Typ. Max. Unit Sector erase time Excludes programming time prior to erasure 0.7 5 s Chip erase time Excludes programming time prior to erasure 50 s Byte programming time Excludes system-level overhead 9 200 µs Word programming time Excludes system-level overhead 11 200 µs BYTE mode 40 Chip programming time Excludes system-level overhead WORD mode 25 s Accelerated programming time Excludes system-level overhead 7 150 µs Erase / Program cycle 1,000,000 cycle
PRELIMINARY (May, 2002, Version 0.0) 33 AMIC Technology, Inc. Timing Waveform for Read Cycle (1) Addresses (Input) Addresses Stable CE (Input) OE (Input) WE (Input) Data Out High-ZI/O (Output) tRC tOEH tOE tCE High-Z tOH tDF tACC Timing Waveform for Read Cycle (2) Addresses (Input) Addresses Stable CE (Input) OE (Input) Data Out High-ZI/O (Output) tRC tRP High-Z tOH tACCtRH tREADY tCE
PRELIMINARY (May, 2002, Version 0.0) 34 AMIC Technology, Inc. Timing Waveform for Sector Group Protection VID VIH RESET (Input) Address (Input) VCC tVCS tVIDR SGAx SGAx SGAy tOE tWP TIMEOUT tWC tVLHT tWC (Input) (Input) (Input) CE (Input) OE (Input) WE (Input) I/O (Input / Outpu) 60H 60H 40H 01H (Note) 60H Note: The sector group protection verification result is output 01H: The sector group is protected. 00H: The sector group is not protected
PRELIMINARY (May, 2002, Version 0.0) 35 AMIC Technology, Inc. Timing Waveform for Temporary Sector Group Unprotect Program or Erase Command Sequence ~~~~ tRRB WE (Input) CE (Input) RY/BY (Output) VID VIH RESET (Input) VCC tVCS tVIDR tVLHT tVLHTtVLHT Period during which protection is canceled Timing Waveform for Accelerated Mode Program or Erase Command Sequence ~~~~ tRRB CE (Input) WE (Input) RY/BY (Output) VID VIH RESET (Input) VCC tVCS tVACCR tVLHT tVLHTtVLHT Accelerated mode period
PRELIMINARY (May, 2002, Version 0.0) 36 AMIC Technology, Inc. Timing Waveform for Dual Operation Address (Input) BA1 Input BA2 BA1 BA2 BA1 BA2 Output InputOutput StatusOutput tRC tWC tRC tWC tRC tWC tAS tAH tACC tCEPH tAHT tAS tDF tDF tCE tOEtOEHtWP tGHWL tDHtDS CE (Input) OE (Input) WE (Input) I/O (Input / Outpu) Timing Waveform for Write Cycle ( WE Controlled) Addresses (Input) CE (Input) OE (Input) WE (Input) I/O (Input / Output) 555H PA DOUTI/O7 Data Polling Note : 1. This timing waveform shows the last two write cycles among the program command sequence's four write cycles, and data polling. 2. This timing waveform shows the WORD mode's case. In the BYTE mode, address to be input is different from the WORD mode. See Table 8. Command Sequence. 3. PA : Program address PD : Program data I/O 7 : The output of the complement of the data written to the device. DOUT : The output of the data written to the device. tBPG or tWPG tAStWC tWP tCS tWPH tDH PA 3rd and 4th write cycle tAH tRC PDA0H DOUT tCE tOE tOH tGHWL tCH tDS
PRELIMINARY (May, 2002, Version 0.0) 37 AMIC Technology, Inc. Timing Waveform for Write Cycle ( CE Controlled) Addresses (Input) CE (Input) OE (Input) WE (Input) I/O (Input / Output) 555H PA DOUTI/O7 Data Polling Note : 1. This timing waveform shows the last two write cycles among the program command sequence's four write cycles, and data polling. 2. This timing waveform shows the WORD mode's case. In the BYTE mode, address to be input is different from the WORD mode. See Table 8. Command Sequence. 3. PA : Program address PD : Program data I/O 7 : The output of the complement of the data written to the device. DOUT : The output of the data written to the device. tBPG or tWPG tAStWC tWH PA 3rd and 4th write cycle tAH tRC PDA0H DOUT tCE tOE tOH tGHWL tDS tCP tCPH tWS tDH
PRELIMINARY (May, 2002, Version 0.0) 38 AMIC Technology, Inc. Timing Waveform for Sector / Chip Erase Address (Input) 555H 55H 2AAH 555H 555H 2AAH FSA (Note) AAH AAH80H 55H tRC tWC CE (Input) I/O (Input / Outpu) 30H tAH tCHtCS tGHWL tWP tWPH tVCS tDHtDS (10H for chip erase) OE (Input) WE (Input) VCC Note : 1. FSA is the sector address to be erased. In the case of chip erase, input 555H (WORD mode), AAAH (BYTE mode). 2. This timing chart shows the WORD mode's case. In the BYTE mode, address to be input is different from the WORD mode. See Table 8. Command Sequence.
PRELIMINARY (May, 2002, Version 0.0) 39 AMIC Technology, Inc. Timing Waveform for Data Polling I/O7 Status Data tDF Valid Data DOUT (Note) tOE tCE tOEH tCH tBUSY tBPG, tWPG, tSER tEOE Hi-Z Hi-Z CE (Input) OE (Input) WE (Input) I/O0-I/O6 (Output) RY/BY(Output) I/O7 (Output) Note : 1. I/O7 = DOUT : True value of program data (indicates completion of automatic program / erase)
PRELIMINARY (May, 2002, Version 0.0) 40 AMIC Technology, Inc. Timing Waveform for Toggle Bit VA ToggleToggle Toggle Stop Toggle (note) Valid Data OutInput Data tBUSY tOEtDH tOEH tOEPH tASO tAHT tAS tAHT tCEPH tCE tOEH Addresses (Input) CE (Input) WE (Input) OE (Input) I/O6, I/O2 (Input / Output) RYBY (Output) Note : 1. I/O6 stops the toggle (indicates automatic program / erase completion). Timing Waveforms for I/O2 vs. I/O6 Input of Automatic Erase Command Erase Suspended Erase Suspended Input of Program Command Erase Resumed WE (Input) I/O6 (Output) I/O2 (Output) Erasure Erase Suspend Read Erase Suspend Read Erasure Completion of Erasure Toggle I/O2 and I/O6 (CE or OE is used for toggle) Erase Suspend Input of Program Command ~~~~
PRELIMINARY (May, 2002, Version 0.0) 41 AMIC Technology, Inc. Timing Waveform for RY/ BY (Read / Busy) tBUSY Rising Edge of the Last Write Pulse Automatic Program or Erase CE (Input) WE (Input) RY/BY (Output) Timing Waveform for RESET / RY / BY tRPD tRB WE (Input) RESET (Input) RY/BY (Output) tRP Timing Waveform for BYTE Input Determined Failing Edge of Last Write Pulse tAH tAS OE, WE (Input) BYTE (Input)
PRELIMINARY (May, 2002, Version 0.0) 42 AMIC Technology, Inc. Timing Waveform for BYTE Mode Switching Data Output I/O0 to I/O14 Data Output I/O0 to I/O7 tELFL Hi-Z CE (Input) BYTE (Input) I/O15 (Output), A-1(Input) I/O0 to I/O14 (Output) Data Output I/O15 Address Input A-1 Hi-Z Hi-Z tACC tFLQZ Timing Waveform for WORD Mode Switching Data Output I/O0 to I/O 7 tELFH Hi-Z CE (Input) BYTE (Input) I/O15 (Output), A-1(Input) I/O0 to I/O14 (Output) Hi-Z tFHQV Data Output I/O0 to I/O14 Data Output I/O15 Address Input A-1 Hi-Z tCE
PRELIMINARY (May, 2002, Version 0.0) 43 AMIC Technology, Inc. Latch-up Characteristics Description Min. Max. Input Voltage with respect to VSS on all I/O pins -1.0V VCC+1.0V VCC Current -100 mA +100 mA Input voltage with respect to VSS on all pins except I/O pins (including A9, OE and RESET) -1.0V 12.5V Includes all pins except VCC. Test conditions: VCC = 5.0V, one pin at time. Capacitance (TA = 25°°C, f = 1MHz) Parameter Symbol Parameter Description Test Setup Typ. Max. Unit CIN Input Capacitance VIN=0 6 7.5 pF COUT Output Capacitance VOUT=0 8.5 12 pF Notes: 1. VIN : Input voltage, VOUT : Output voltage 2. These parameters are not 100% tested. Data Retention Parameter Test Conditions Min Unit 150°C 10 Years Minimum Pattern Data Retention Time 125°C 20 Years
PRELIMINARY (May, 2002, Version 0.0) 44 AMIC Technology, Inc.
Ordering Information
Part No. Access Time (ns) Operating Supply Voltage (V) Boot Sector Package A29DL323TV-90 Top Address (Sector) (T type) 48Pin TSOP A29DL323UV-90 Bottom Address (Sector) (B type) 48Pin TSOP A29DL323TG-90 Top Address (Sector) (T type) 63-ball TFBGA A29DL323UG-90 90 2.7 to 3.6 Bottom Address (Sector) (B type) 63-ball TFBGA
PRELIMINARY (May, 2002, Version 0.0) 45 AMIC Technology, Inc.
Package Information
TSOP 48L (Type I) Outline Dimensions unit: inches/mm E c D L θ Detail "A" 0.25 24 25 D y eS A1 A2 A Detail "A" b Dimensions in inches Dimensions in mm Symbol Min Nom Max Min Nom Max A1 0.002 - 0.006 0.05 - 0.15 c 0.004 - 0.008 0.12 - 0.20 E - 0.472 0.476 - 12.00 12.10 e 0.020 BASIC 0.50 BASIC S 0.011 Typ. 0.28 Typ. θ 0° - 8° 0° - 8° Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension S includes end flash.
PRELIMINARY (May, 2002, Version 0.0) 46 AMIC Technology, Inc.
63 BALLS TFBGA (7 x 11mm) Outline Dimensions unit: mm
0.0511.00 ± 8 7 6 5 4 3 2 1 A B C D E F G H J K L M 5.6 0.7 8.8 0.8 1.17.00 0.05± Ball#A1 CORNER A0.10 C M 0.05 M B C 0.35 A B Ball*A1 CORNER TOP VIEW BOTTOM VIEW SIDE VIEW CSEATING PLANE // 0.1 C 1.2 MAX. 0.050.25 ± 0.08 C