A29512

A29512 AMICC | Alldatasheet

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64K X 8 Bit CMOS 5.0 Volt-only, Preliminary Uniform Sector Flash Memory PRELIMINARY (November, 2001, Version 0.0) AMIC Technology, Inc. Document Title 64K X 8 Bit CMOS 5.0 Volt-only, Uniform Sector Flash Memory

Revision History

Rev. No. History Issue Date Remark

0.0 Initial issue November 30, 2001 Preliminary

64K X 8 Bit CMOS 5.0 Volt-only, Preliminary Uniform Sector Flash Memory PRELIMINARY (November, 2001, Version 0.0) 1 AMIC Technology, Inc.

Features

n 5.0V ± 10% for read and write operations n Access times: - 55/70/90 (max.) n Current: - 20 mA typical active read current - 30 mA typical program/erase current - 1 µA typical CMOS standby n Flexible sector architecture - 32 Kbyte X 2 sectors - Any combination of sectors can be erased - Supports full chip erase - Sector protection: A hard ware method of protecting sectors to prevent any inadvertent program or erase operations within that sector n Embedded Erase Algorithms - Embedded Erase algorithm will automatically erase the entire chip or any combination of designated sectors and verify the erased sectors - Embedded Program algorithm automatically writes and verifies bytes at specified addresses n Typical 100,000 program/erase cycles per sector n 20-year data retention at 125°C - Reliable operation for the life of the system n Compatible with JEDEC-standards - Pinout and software compatible with single -power- supply Flash memory standard - Superior inadvertent write protection n Data Polling and toggle bits - Provides a software method of detecting completion of program or erase operations n Erase Suspend/Erase Resume - Suspends a sector erase operation to read data from, or program data to, a non -erasing sector, then resumes the erase operation n Package options - 32-pin P-DIP, PLCC, or TSOP(Forward type) General Description The A29512 is a 5.0 volt -only Flash memory organized as 65,535 bytes of 8 bits each. The 64 Kbytes of data are further divided into four sectors for flexible sector erase capability. The 8 bits of data appear on I/O 0 - I/O7 while the addresses are input on A0 to A15. The A29512 is offered in 32 -pin PLCC, TSOP, and PDIP packages. This device is designed to be programmed in -system with the standard system 5.0 volt VCC supply. Additional 12.0 volt VPP is not required for in-system write or erase operations. Howeve r, the A29512 can also be programmed in standard EPROM programmers. The A29512 has the first toggle bit, I/O 6, which indicates whether an Embedded Program or Erase is in progress, or it is in the Erase Suspend. Besides the I/O 6 toggle bit, the A29512 has a second toggle bit, I/O 2, to indicate whether the addressed sector is being selected for erase. The A29512 also offers the ability to program in the Erase Suspend mode. The standard A29512 offers access times of 55, 70 and 90 ns allowing high -speed microp rocessors to operate without wait states. To eliminate bus contention the device has separate chip enable ( CE ), write enable ( WE ) and output enable ( OE ) controls. The device requires only a single 5.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The A29512 is entirely software command set compatible with the JEDEC single -power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state -machine that controls the erase and programming circuitry. Write cycles also internally latch addresse s and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by writing the proper program command sequence. This initiates the Embedded Progr am algorithm - an internal algorithm that automatically times the program pulse widths and verifies proper program margin. Device erasure occurs by executing the proper erase command sequence. This initiates the Embedded Erase algorithm - an internal algo rithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper erase margin.

PRELIMINARY (November, 2001, Version 0.0) 2 AMIC Technology, Inc. The host system can detect whethe r a program or erase operation is complete by reading the I/O 7 ( Data Polling) and I/O6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The A29512 is fully erased when shipped from the factory. The hardware sector protection feature disables operations for both pro gram and erase in any combination of the Pin Configurations sectors of memory. This can be achieved via programming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any other sector that is not selected for erasure. True background erase can thus be achieved. Power consumption is greatly reduced when the device is placed in the standby mode. n DIP n PLCC NC NC A15 A12 I/O0 I/O1 I/O2 I/O3VSS I/O4 I/O5 I/O6 I/O7 CE A10 OE A13 WE NC A14 VCC A11 A29512 16 17 I/O0 21 CE I/O7 A10 A29512L OE A11 A13 A14 I/O1 I/O2 VSS I/O3 I/O4 I/O5 I/O6 A12 A15 NC NC VCC WE NC n TSOP (Forward type) A29512V A13 A14 NC WE VCC NC A15 A12 17 A3 I/O I/O1 I/O2 VSS I/O3 I/O4 I/O5 I/O6 I/O7 CE A10 OEA11 NC

PRELIMINARY (November, 2001, Version 0.0) 3 AMIC Technology, Inc. Block Diagram Pin Descriptions Pin No. Description A0 - A15 Address Inputs I/O0 - I/O7 Data Inputs/Outputs CE Chip Enable WE Write Enable OE Output Enable VSS Ground VCC Power Supply State Control Command Register Address Latch X-decoder Y-Decoder Chip Enable Output Enable Logic Cell Matrix Y-Gating VCC Detector PGM Voltage Generator Data Latch Input/Output BuffersErase Voltage Generator VCC VSS WE CE OE A0-A15 I/O0 - I/O7 Timer STB STB

PRELIMINARY (November, 2001, Version 0.0) 4 AMIC Technology, Inc.

1. Minimum DC voltage on input or I/O pins is -0.5V.
2. Minimum DC input voltage on A9 pins is -0.5V. During

to 13.5V for periods up to 20ns.

1. No more than one output is shorted at a time. Duration

Ratings" may cause permanent damage to this device. periods may affect device reliability. functionally of the device is guaranteed. Table 1. A29512 Device Bus Operations

PRELIMINARY (November, 2001, Version 0.0) 5 AMIC Technology, Inc. Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE and OE pins to V IL. CE is the power control and selects the device. OE is the output control and gates array data to the output pins. WE should remain at V IH all the time during read operation. The internal state machine is set for reading array data upon device power -up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device ad dress inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See "Reading Array Data" for more information. Refer to the AC Read Operations table for timing specifi cations and to the Read Operations Timings diagram for the timing waveforms, lCC1 in the DC Characteristics table represents the active current specification for reading array data. Writing Commands/Command Sequences To write a command or command sequenc e (which includes programming data to the device and erasing sectors of memory), the system must drive WE and CE to VIL, and OE to V IH. An erase operation can erase one sector, multiple sectors , or the entire device. The Sector Address Tables indicate the address range that each sector occupies. A "sector address" consists of the address inputs required to uniquely select a sector. See the "Command Definitions" section for details on erasing a s ector or the entire chip, or suspending/resuming the erase operation. After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate f rom the memory array) on I/O 7 - I/O0. Standard read cycle timings apply in this mode. Refer to the "Autoselect Mode" and "Autoselect Command Sequence" sections for more information. ICC2 in the Characteristics table represents the active current specificat ion for the write mode. The "AC Characteristics" section contains timing specification tables and timing diagrams for write operations. Program and Erase Operation Status During an erase or program operation, the system may check the status of the operat ion by reading the status bits on I/O 7 - I/O 0. Standard read cycle timings and I CC read specifications apply. Refer to "Write Operation Status" for more information, and to each AC Characteristics section for timing diagrams. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE input. The device enters the CMOS standby mode when the CE is held at V CC ± 0.5V. (Note that this is a more restricted voltage range than V IH.) The device enters the TTL standby mode when CE is held at V IH. The device requires the standard access time (tCE) before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. ICC3 in the DC Characteristics tables represents the standby current specification. Output Disable Mode When the OE input is at V IH, output from the device is disabled. The output pins are placed in the high impedance state.

PRELIMINARY (November, 2001, Version 0.0) 6 AMIC Technology, Inc. Table 2. A29512 Block Sector Address Table Table 3. A29512 Autoselect Codes (High Voltage Method)

PRELIMINARY (November, 2001, Version 0.0) 7 AMIC Technology, Inc. Sector Protection/Unprotection The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re -enables both program and erase operations in previously protected sectors. Sector protection/unprotection must be implemented using programming equipment. The procedure requires a high voltage (VID) on address pin A9 and the control pins. The device is shipped with all sectors unprotected. It is possible to determine whether a sector is protected or unprotected. See "Autoselect Mode" for details. Hardware Data Protection The requirement of command unlocking sequence for programming or erasing provides data protecti on against inadvertent writes (refer to the Command Definitions table). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up transitions, or from system noise. The device is powered up to read array data to avoid accidentally writing data to the array. Write Pulse "Glitch" Protection Noise pulses of less than 5ns (typical) on OE , CE or WE do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE =VIL, CE = V IH or WE = V IH. To initiate a write cycle, CE and WE must be a logical zero while OE is a logical one. Power-Up Write Inhibit If WE = CE = V IL and OE = V IH during power up, the device does not accept commands on the rising edge of WE . The internal state machine is automatically reset to reading array data on the initial power-up. Command Definitions Writing specific address and data commands or sequences into t he command register initiates device operations. The Command Definitions table defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. All addresses are latched on the falling edge of WE or CE , whichever happens later. All data is latched on the rising edge of WE or CE , whichever happens first. Refer to the appropriate timing diagrams in the "AC Characteristics" section. Reading Array Data The device is automatically set to reading array data after device power -up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address withi n erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See "Erase Suspend/Erase Resume Commands" for more information on this mode. The system must issue the reset command to re -enable the device for reading array data if I/O 5 goes high, or while in the autoselect mode. See the "Reset Command" section, next. See also "Requirements for Reading Array Data" in the "Device Bus Operations" section for more information. The Read Operations table provides the read parameters, and Read Operation Timings diagram shows the timing diagram. Reset Command Writing the reset command to the device resets the device to reading array d ata. Address bits are don't care for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignor es reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Sus pend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend). If I/O5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Suspend).

PRELIMINARY (November, 2001, Version 0.0) 8 AMIC Technology, Inc. for the byte program command sequence. Operation Status" for information on these status bits. Figure 1. Program Operation

PRELIMINARY (November, 2001, Version 0.0) 9 AMIC Technology, Inc. Chip Erase Command Sequence Chip erase is a six -bus-cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set -up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. The Command Definitions table shows the address and data requirements for the chip erase command sequence. Any command s written to the chip during the Embedded Erase algorithm are ignored. The system can determine the status of the erase operation by using I/O 7, I/O6, or I/O2. See "Write Operation Status" for information on these status bits. When the Embedded Erase algor ithm is complete, the device returns to reading array data and addresses are no longer latched. Figure 2 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in "AC Characteristics" for parameters, and to the Chip/Sec tor Erase Operation Timings for timing waveforms. Sector Erase Command Sequence Sector erase is a six -bus-cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set -up command. Two additional unlock wr ite cycles are then followed by the address of the sector to be erased, and the sector erase command. The Command Definitions table shows the address and data requirements for the sector erase command sequence. The device does not require the system to pr eprogram the memory prior to erase. The Embedded Erase algorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time - out of 50 µs begins. During the time -out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 µs, otherwise the last address and command might not be accepted, and erasure may begin. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re -enabled after the last Sector Erase command is written. If the time between additional sector erase commands can be assumed to be less than 50 µs, the system need not monitor I/O 3. Any command other than Sector Erase or Erase Suspend during the time -out period resets the device to reading array data. The system must rewrite the command sequence and any additional sector addresses and commands. The system can monitor I/O 3 to determine if the sector erase timer has timed out. (See the " I/O 3: Sector Erase Timer" section.) The time-out begins from the rising edge of the final WE pulse in the command sequence. Once the sector erase operation has begun, only the E rase Suspend command is valid. All other commands are ignored. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by using I/O 7, I/O 6, or I/O 2. Refer to "Write Operation Status" for information on these status bits.

PRELIMINARY (November, 2001, Version 0.0) 11 AMIC Technology, Inc. Table 4. A29512 Command Definitions RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data latches on the rising edge of WE or CE pulse, whichever happens first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A15 select a unique sector.

1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles are write operation.
4. Address bits A15 - A12 are don't cares for unlock and command cycles, unless SA or PA required.
5. No unlock or command cycles required when reading array data.
6. The Reset command is required to return to reading array data when device is in the autoselect mode, or if I/O 5 goes high

(while the device is providing status data).

1. The fourth cycle of the autoselect command sequence is a read cycle.
2. The data is 00h for an unprotected sector and 01h for a protected sector. See "Autoselect Command Sequence" for more
3. The system may read and program in non -erasing sectors, or enter the autoselect mode, when in the Erase Suspend
4. The Erase Resume command is valid only during the Erase Suspend mode.
5. The time between each command cycle has to be less than 50µs.

PRELIMINARY (November, 2001, Version 0.0) 12 AMIC Technology, Inc. the A29512 to determine the status of a write operatio n. completed, or whether the device is in Erase Suspend. pulse in the program or erase command sequence. for erasure to read valid status information on I/O 7. Polling on I/O7. Figure 3 shows the Data Polling algorithm.

1. VA = Valid address for programming. During a sector

address is any non-protected sector address.

1. I/O7 should be rechecked even if I/O5 = "1" because

I/O7 may change simultaneously with I/O5. Figure 3. Data Polling Algorithm

PRELIMINARY (November, 2001, Version 0.0) 13 AMIC Technology, Inc. I/O6: Toggle Bit I Toggle Bit I on I/O 6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause I/O6 to toggle. (The system may use either OE or CE to control the read cycles.) When the operation is complete, I/O6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, I/O 6 toggles for approximately 100µs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use I/O 6 and I/O 2 together to determine whether a sector is actively erasing or is erase -suspended. When the device is actively erasing (that is, the Embe dded Erase algorithm is in progress), I/O 6 toggles. When the device enters the Erase Suspend mode, I/O 6 stops toggling. However, the system must also use I/O 2 to determine which sectors are erasing or erase -suspended. Alternatively, the system can use I/O 7 (see the subsection on " I/O7 : Data Polling"). If a program address falls within a protected sector, I/O 6 toggles for approximately 2 µs after the program command sequence is written, then returns to reading array data. I/O6 also toggles during the erase -suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. The Write Operation Status table shows the outputs for Toggle Bit I on I/O 6. Refer to Figure 4 for the toggle bit algorithm, and to the Toggle B it Timings figure in the "AC Characteristics" section for the timing diagram. The I/O 2 vs. I/O6 figure shows the differences between I/O 2 and I/O 6 in graphical form. See also the subsection on " I/O 2: Toggle Bit II". I/O2: Toggle Bit II The "Toggle Bit I I" on I/O 2, when used with I/O 6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase -suspended. Toggle Bit II is valid after the rising edge of the final WE pulse in the command sequence. I/O2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE or CE to control the read cycles.) But I/O 2 cannot distinguish whether the sector is actively erasing or is erase -suspended. I/O 6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thu s, both status bits are required for sector and mode information. Refer to Table 6 to compare outputs for I/O2 and I/O6. Figure 4 shows the toggle bit algorithm in flowchart form, and the section " I/O 2: Toggle Bit II" explains the algorithm. See also the " I/O6: Toggle Bit I" subsection. Refer to the Toggle Bit Timings figure for the toggle bit timing diagram. The I/O2 vs. I/O6 figure shows the differences between I/O 2 and I/O6 in graphical form. Reading Toggle Bits I/O6, I/O2 Refer to Figure 4 for the fo llowing discussion. Whenever the system initially begins reading toggle bit status, it must read I/O7 - I/O0 at least twice in a row to determine whether a toggle bit is toggling. Typically, a system would note and store the value of the toggle bit after t he first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on I/O 7 - I/O 0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of I/O 5 is high (see the section on I/O 5). If it is, the system should then det ermine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as I/O 5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and I/O 5 has not gone high. The system may continue to monitor the toggle bit and I/O 5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at th e beginning of the algorithm when it returns to determine the status of the operation (top of Figure 4). I/O5: Exceeded Timing Limits I/O5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these condit ions I/O 5 produces a "1." This is a failure condition that indicates the program or erase cycle was not successfully completed. The I/O5 failure condition may appear if the system tries to program a "1 "to a location that is previously programmed to "0." Only an erase operation can change a "0" back to a "1." Under this condition, the device halts the operation, and when the operation has exceeded the timing limits, I/O5 produces a "1." Under both these conditions, the system must issue the reset command to return the device to reading array data.

PRELIMINARY (November, 2001, Version 0.0) 14 AMIC Technology, Inc. applies after each additional sector erase command. "Sector Erase Command Sequence" section. been accepted. Table 5 shows the outputs for I/O3.

1. Read toggle bit twice to determine whether or not it is
2. Recheck toggle bit because it may stop toggling as I/O5

Figure 4. Toggle Bit Algorithm

PRELIMINARY (November, 2001, Version 0.0) 15 AMIC Technology, Inc. Table 5. Write Operation Status

1. I/O7 and I/O2 require a valid address when reading status information. Refer to the appropriate subsection for further
2. I/O5 switches to “1” when an Embedded Program or Embedded Erase operation has exceeded the maximum timing

limits. See “I/O5: Exceeded Timing Limits” for more information.

PRELIMINARY (November, 2001, Version 0.0) 16 AMIC Technology, Inc. DC Characteristics TTL/NMOS Compatible Parameter Symbol Parameter Description Test Description Min. Typ. Max. Unit ILI Input Load Current VIN = VSS to VCC. VCC = VCC Max ±1.0 µA ILIT A9 &OE Input Load Current VCC = VCC Max, A9 & OE = 12.5V 100 µA ILO Output Leakage Current VOUT = VSS to VCC. VCC = VCC Max ±1.0 µA ICC1 VCC Active Read Current (Notes 1, 2) CE = VIL, OE = VIH 20 30 mA ICC2 VCC Active Write (Program/Erase) Current (Notes 2, 3, 4) CE = VIL, OE =VIH 30 40 mA ICC3 VCC Standby Current (Note 2) CE = VIH 0.4 1.0 mA VIL Input Low Level -0.5 0.8 V VIH Input High Level 2.0 VCC+0.5 V VID Voltage for Autoselect VCC = 5.25 V 10.5 12.5 V VOL Output Low Voltage IOL = 12mA, VCC = VCC Min 0.45 V VOH Output High Voltage IOH = -2.5 mA, VCC = VCC Min 2.4 V CMOS Compatible Parameter Symbol Parameter Description Test Description Min. Typ. Max. Unit ILI Input Load Current VIN = VSS to VCC, VCC = VCC Max ±1.0 µA ILIT A9 & OE Input Load Current VCC = VCC Max, A9 & OE = 12.5V 100 µA ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC Max ±1.0 µA ICC1 VCC Active Read Current (Notes 1,2) CE = VIL, OE = VIH 20 30 mA ICC2 VCC Active Program/Erase Current (Notes 2,3,4) CE = VIL, OE = VIH 30 40 mA ICC3 VCC Standby Current (Notes 2, 5) CE = VCC ± 0.5 V 1 5 µA VIL Input Low Level -0.5 0.8 V VIH Input High Level 0.7 x VCC VCC+0.3 V VID Voltage for Autoselect VCC = 5.25 V 10.5 12.5 V VOL Output Low Voltage IOL = 12.0 mA, VCC = VCC Min 0.45 V VOH1 IOH = -2.5 mA, VCC = VCC Min 0.85 x VCC V VOH2 Output High Voltage IOH = -100 µA. VCC = VCC Min VCC-0.4 V Notes for DC characteristics (both tables): 1. The ICC current listed includes both the DC operation current and the frequency dependent component (at 6 MHz). The frequency component typically is less than 2 mA/MHz, with OE at VIH. 2. Maximum ICC specifications are tested with VCC = VCC max. 3. ICC active while Embedded Algorithm (program or erase) is in progress. 4. Not 100% tested. 5. For CMOS mode only, ICC3 = 20µA max at extended temperatures (> +85°C).

PRELIMINARY (November, 2001, Version 0.0) 17 AMIC Technology, Inc. AC Characteristics Read Only Operations Parameter Symbols Speed JEDEC Std Description Test Setup -55 -70 -90 Unit tAVAV tRC Read Cycle Time (Note 2) Min. 55 70 90 ns tAVQV tACC Address to Output Delay CE = VIL OE = VIL Max. 55 70 90 ns tELQV tCE Chip Enable to Output Delay OE = VIL Max. 55 70 90 ns tGLQV tOE Output Enable to Output Delay Max. 30 30 35 ns Read Min. 0 0 0 ns tOEH Output Enable Hold Time (Note 2) Toggle and Data Polling Min. 10 10 10 ns tEHQZ tDF Chip Enable to Output High Z (Notes 1,2) Max. 18 20 20 ns tGHQZ tDF Output Enable to Output High Z (Notes 1,2) 18 20 20 ns tAXQX tOH Output Hold Time from Addresses, CE or OE , Whichever Occurs First Min. 0 0 0 ns Notes: 1. Output driver disable time. 2. Not 100% tested. Timing Waveforms for Read Only Operation Addresses Addresses Stable CE OE WE Output Valid High-ZOutput tRC tOEH tOE tCE High-Z tOH tDF tACC

PRELIMINARY (November, 2001, Version 0.0) 18 AMIC Technology, Inc. AC Characteristics Erase and Program Operations Parameter Symbols Speed JEDEC Std

Description

-55 -70 -90 Unit tAVAV tWC Write Cycle Time (Note 1) Min. 55 70 90 ns tAVWL tAS Address Setup Time Min. 0 ns tWLAX tAH Address Hold Time Min. 40 45 45 ns tDVWH tDS Data Setup Time Min. 25 30 45 ns tWHDX tDH Data Hold Time Min. 0 ns tOES Output Enable Setup Time Min. 0 ns tGHWL tGHWL Read Recover Time Before Write (OE high to WE low) Min. 0 ns tELWL tCS CE Setup Time Min. 0 ns tWHEH tCH CE Hold Time Min. 0 ns tWLWH tWP Write Pulse Width Min. 30 35 45 ns Min. 20 ns tWHWL tWPH Write Pulse Width High Max. 50 µs tWHWH1 tWHWH1 Byte Programming Operation (Note 2) Typ. 7 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ. 1 sec tVCS VCC Set Up Time (Note 1) Min. 50 µs Notes: 1. Not 100% tested. 2. See the "Erase and Programming Performance" section for more information.

PRELIMINARY (November, 2001, Version 0.0) 19 AMIC Technology, Inc. Timing Waveforms for Program Operation Addresses CE OE WE Data VCC A0h PD tWC PA Program Command Sequence (last two cycles) PA DOUT ~~~~ PA Status tAS tVCS Read Status Data (last two cycles) 555h tAH tWHWH1 tCH tGHWL tWP tWPHtCS tDS tDH Note : PA = program addrss, PD = program data, Dout is the true data at the program address.

PRELIMINARY (November, 2001, Version 0.0) 20 AMIC Technology, Inc. Addresses CE OE WE Data VCC 55h 30h tWC SA Erase Command Sequence (last two cycles) VA Complete ~~~~ VA In Progress tAS tVCS Read Status Data 2AAh tAH tWHWH2 tCH tGHWL tWP tWPH tCS tDS tDH Note : SA = Sector Address. VA = Valid Address for reading status data. 555h for chip erase 10h for chip erase Timing Waveforms for Chip/Sector Erase Operation

PRELIMINARY (November, 2001, Version 0.0) 21 AMIC Technology, Inc. Timing Waveforms for Data Polling (During Embedded Algorithms) Addresses CE OE WE I/O7 tRC VAVA VA Complement ~~ Complement True Valid Data High-Z Status Data ~~ Status Data True Valid Data High-Z I/O0 - I/O6 tACC tCE tCH tOE tOEH tDF tOH Note : VA = Valid Address. Illustation shows first status cycle after command sequence, last status read cycle, and array data read cycle.

PRELIMINARY (November, 2001, Version 0.0) 22 AMIC Technology, Inc. Timing Waveforms for Toggle Bit (During Embedded Algorithms) Note: VA = Valid Address; not required for I/O6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle. Addresses CE OE WE I/O6 , I/O2 tRC VAVA VA Valid Status tACC tCE tCH tOE tOEH tDF tOH VA Valid Status Valid Status Valid Status (first read) (second read) (stop togging)

PRELIMINARY (November, 2001, Version 0.0) 23 AMIC Technology, Inc. Timing Waveforms for I/O2 vs. I/O6 AC Characteristics Erase and Program Operations Alternate CE Controlled Writes Parameter Symbols Speed JEDEC Std -55 -70 -90 Unit tAVAV tWC Write Cycle Time (Note 1) Min. 55 70 90 ns tAVEL tAS Address Setup Time Min. 0 ns tELAX tAH Address Hold Time Min. 40 45 45 ns tDVEH tDS Data Setup Time Min. 25 30 45 ns tEHDX tDH Data Hold Time Min. 0 ns tGHEL tGHEL Read Recover Time Before Write Min. 0 ns tWLEL tWS WE Setup Time Min. 0 ns tEHWH tWH WE Hold Time Min. 0 ns tELEH tCP Write Pulse Width Min. 30 35 45 ns tEHEL tCPH Write Pulse Width High Min. 20 20 20 ns tWHWH1 tWHWH1 Byte Programming Operation (Note 2) Typ. 7 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ. 1 sec Notes: 3. Not 100% tested. 4. See the "Erase and Programming Performance" section for more informat ion. Enter Embedded Erasing Erase Suspend Enter Erase Suspend Program Erase Resume WE I/O6 I/O2 Erase Erase Suspend Read Erase Suspend Read Erase Erase Complete I/O2 and I/O6 toggle with OE and CE Note : Both I/O6 and I/O2 toggle with OE or CE. See the text on I/O6 and I/O2 in the section "Write Operation Statue" for more information. ~~Erase Suspend Program ~~~~

PRELIMINARY (November, 2001, Version 0.0) 24 AMIC Technology, Inc. Timing Waveforms for Alternate CE Controlled Write Operation Erase and Programming Performance Parameter Typ. (Note 1) Max. (Note 2) Unit Comments Sector Erase Time 1 8 sec Chip Erase Time 8 64 sec Excludes 00h programming prior to erasure (Note 4) Byte Programming Time 35 300 µs Chip Programming Time (Note 3) 3.6 10.8 sec Excludes system-level overhead (Note 5) Notes: 1. Typical program and erase times assume the following conditions: 25 °C, 5.0V VCC, 100,000 cycles. Ad ditionally, programming typically assumes checkerboard pattern. 2. Under worst case conditions of 90°C, VCC = 4.5V (4.75V for -55), 100,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, sin ce most bytes program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then does the device set I/O5 = 1. See the section on I/O5 for further information. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System -level overhead is the time required to execute the four -bus-cycle command sequence for programming. See Table 4 for further information on command definitions. 6. The device has a guaranteed minimum erase and program cycle endurance of 100,000 cycles. Addresses WE OE CE Data 555 for program 2AA for erase PA DOUT ~~~~ I/O7 Data Polling Note : 1. PA = Program Address, PD = Program Data, SA = Sector Address, I/O7 = Complement of Data Input, DOUT = Array Data. 2. Figure indicates the last two bus cycles of the command sequence. PD for program 30 for sector erase 10 for chip erase tBUSY tWHWH1 or 2 tAH tAStWC tWH tGHEL tCP tWS tCPH PA for program SA for sector erase 555 for chip erase A0 for program 55 for erase tRH tDS tDH

PRELIMINARY (November, 2001, Version 0.0) 25 AMIC Technology, Inc. Latch-up Characteristics Description Min. Max. Input Voltage with respect to VSS on all I/O pins -1.0V VCC+1.0V VCC Current -100 mA +100 mA Input voltage with respect to VSS on all pins except I/O pins (including A9 and OE ) -1.0V 12.5V Includes all pins except VCC. Test conditions: VCC = 5.0V, one pin at time. TSOP Pin Capacitance Parameter Symbol Parameter Description Test Setup Typ. Max. Unit CIN Input Capacitance VIN=0 6 7.5 pF COUT Output Capacitance VOUT=0 8.5 12 pF CIN2 Control Pin Capacitance VIN=0 7.5 9 pF Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25°C, f = 1.0MHz PLCC and P-DIP Pin Capacitance Parameter Symbol Parameter Description Test Setup Typ. Max. Unit CIN Input Capacitance VIN=0 4 6 pF COUT Output Capacitance VOUT=0 8 12 pF CIN2 Control Pin Capacitance VPP=0 8 12 pF Notes: 3. Sampled, not 100% tested. 4. Test conditions TA = 25°C, f = 1.0MHz Data Retention Parameter Test Conditions Min Unit 150°C 10 Years Minimum Pattern Data Retention Time 125°C 20 Years

PRELIMINARY (November, 2001, Version 0.0) 26 AMIC Technology, Inc. Test Conditions Test Specifications Test Condition -55 All others Unit Output Load 1 TTL gate Output Load Capacitance, CL(including jig capacitance) 30 100 pF Input Rise and Fall Times 5 20 ns Input Pulse Levels 0.0 - 3.0 0.45 - 2.4 V Input timing measurement reference levels 1.5 0.8, 2.0 V Output timing measurement reference levels 1.5 0.8, 2.0 V Test Setup 6.2 KΩ Device Under Test CL Diodes = IN3064 or Equivalent 2.7 KΩ 5.0 V

PRELIMINARY (November, 2001, Version 0.0) 27 AMIC Technology, Inc.

Ordering Information

Part No. Access Time (ns) Active Read Current Typ. (mA) Program/Erase Current Typ. (mA) Standby Current Typ. (µA) Package A29512-55 32Pin DIP A29512L-55 32Pin PLCC A29512V-55 55 20 30 1 32Pin TSOP A29512-70 32Pin DIP A29512L-70 32Pin PLCC A29512V-70 70 20 30 1 32Pin TSOP A29512-90 32Pin DIP A29512L-90 32Pin PLCC A29512V-90 90 20 30 1 32Pin TSOP

PRELIMINARY (November, 2001, Version 0.0) 28 AMIC Technology, Inc.

Package Information

P-DIP 32L Outline Dimensions unit: inches/mm EA2 AL EA D C θ B Base Plane Seating Plane e Dimensions in inches Dimensions in mm Symbol Min Nom Max Min Nom Max Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins.

PRELIMINARY (November, 2001, Version 0.0) 29 AMIC Technology, Inc. PLCC 32L Outline Dimension unit: inches/mm A1 A2 A e D y HD D GD b GE c 21 29 E HE L θ Dimensions in inches Dimensions in mm Symbol Min Nom Max Min Nom Max Notes: 1. Dimensions D and E do not include resin fins. 2. Dimensions GD & GE are for PC Board surface mount pad pitch design reference only.

PRELIMINARY (November, 2001, Version 0.0) 30 AMIC Technology, Inc. TSOP 32L TYPE I (8 X 20mm) Outline Dimensions unit: inches/mm e LE L A c D y Detail "A" S b HD D E θ Detail "A" Dimensions in inches Dimensions in mm Symbol Min Nom Max Min Nom Max A1 0.002 - 0.006 0.05 - 0.15 c 0.004 - 0.008 0.11 - 0.20 E - 0.315 0.319 - 8.00 8.10 e 0.020 BSC 0.50 BSC θ 0° - 5° 0° - 5° Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension S includes end flash.