A29160A

A29160A AMICC | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 43

Technical content

2M X 8 Bit / 1M X 16 Bit CMOS 5.0 Volt-only, Boot Sector Flash Memory (August, 2014, Version 1.2) AMIC Technology, Corp. Document Title 2M X 8 Bit / 1M X 16 Bi t CMOS 5.0 Volt-only, Boot Sector Flash Memory

Revision History

Rev. No. History Issue Date Remark

0.0 Initial issue May 27, 2013 Preliminary

1.0 Update I CC3, ICC4, Absolute Maximum Rating, Program/Erase time May 8, 2014 Final

1.1 Page 6 “Writing Commands/Command Sequences” section : August 5, 2014

The “Word/Byte Program Command Seque nce” section has details on programming data to the device using both standard and Unlock Bypass command sequence. Into The “Word/Byte Program Command Sequence” and “Unlock Bypass Command Sequence” has detail descriptions on programming data to the device using both standard and Unlock Bypass command sequence.

1.2 Page 18: Delete Note 8 and adjust t he Notes in the Table 9 August 11, 2014

2M X 8 Bit / 1M X 16 Bit CMOS 5.0 Volt-only, Boot Sector Flash Memory (August, 2014, Version 1.2) 1 AMIC Technology, Corp.

Features

„ Single power supply operation - Full voltage range: 4.5 to 5.5 volt for read and write operations „ Access time: - 55ns (max.) „ Current: - 20mA typical active read current - 30mA typical program/erase current - 6uA typical CMOS standby ( WP = VCC or Float) „ Flexible sector architecture - 16 Kbyte/ 8 KbyteX2/ 32 Kbyte/ 64 KbyteX31 sectors - 8 Kword/ 4 KwordX2/ 16 Kword/ 32 KwordX31 sectors - Any combination of sectors can be erased - Supports full chip erase - Sector protection: A hardware method of protecting sectors to prevent any inadvertent program or eras e operations within that sector. Temporary Sector Unpr otect feature allows code changes in previously locked sectors „ Industrial operating temperatur e range: -40ºC to +85ºC for -U series „ Unlock Bypass Program Command - Reduces overall programming time when issuing multiple program command sequence „ Top or bottom boot block configurations available „ Embedded Algorithms - Embedded Erase algorithm will automatically erase the entire chip or any combination of designated sectors and verify the erased sectors - Embedded Program algorithm automatically writes and verifies data at specified addresses „ Minimum 100,000 program/erase cycles per sector „ 20-year data retention at 125ºC - Reliable operation for the life of the system „ CFI (Common Flash Interface) compliant - Provides device-specific information to the system, allowing host software to easily reconfigure for different Flash devices „ Compatible with JEDEC-standards - Pinout and software compatible with single-power-supply Flash memory standard - Superior inadvertent write protection „ Data Polling and toggle bits - Provides a software method of detecting completion of program or erase operations „ Ready / BUSY pin (RY / BY) - Provides a hardware method of detecting completion of program or erase operations „ Erase Suspend/Erase Resume - Suspends a sector erase operation to read data from, or program data to, a non-erasing sector, then resumes the erase operation „ Hardware reset pin ( RESET ) - Hardware method to reset the device to reading array data „ WP input pin (48 pins TSOP, TFBGA) - At V IL, protects the 16Kbyte bo ot sector from erasure regardless of sector protect/unprotect status. - At VIH, allows removal of boot sector protection. „ Package options - 48-pin TSOP (I) or 48-ball TFBGA - All Pb-free (Lead-free) products are RoHS2.0 compliant General Description The A29160A is a 16Mbit, 5.0 volt-only Flash memory organized as 2,097,152 bytes of 8 bits or 1,048,576 words of 16 bits each. The 8 bits of data appear on I/O 0 - I/O7; the 16 bits of data appear on I/O 0~I/O15. The is offered in 48-ball FBGA and 48-Pin TSOP packages. This device is designed to be programmed in-system wi th the standard system 5.0 volt VCC supply. Additional 12. 0 volt VPP is not required for in-system write or erase operations. However, the A29160A can also be programmed in standard EPROM programmers. The A29160A has the first toggle bit, I/O 6, which indicates whether an Embedded Program or Erase is in progress, or it is in the Erase Suspend. Besides the I/O 6 toggle bit, the A29160A has a second toggle bit, I/O 2, to indicate whether the addressed sector is being selected for erase. The A29160A also offers the ability to program in the Erase Suspend mode. The standard A29160A offers access time of 55ns, allowing high-speed microprocessors to operate without wait states. To elim inate bus contention the device has separate chip enable ( CE ), write enable ( WE ) and output enable (OE ) controls. The device requires only a single 5.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provid ed for the program and erase operations. The A29160A is entirely software command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write ti mings. Register contents serve as input to an internal st ate-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by writing the proper program command sequence. This initiates the Embedded Program

(August, 2014, Version 1.2) 2 AMIC Technology, Corp. algorithm - an internal algorithm that automatically times the program pulse widths and verifies proper program margin. Device erasure occurs by executing the proper erase command sequence. This initiates the Embedded Erase algorithm - an internal algor ithm that automatically preprograms the array (if it is not already programmed) before executing the erase oper ation. During erase, the device automatically times the erase pulse widths and verifies proper erase margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. The host system can detect w hether a program or erase operation is complete by observing the RY / BY pin, or by reading the I/O 7 ( Data Polling) and I/O 6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The A29160A is fully erased when shipped from the factory. The hardware sector protection feature disables operations for both program and erase in any combination of the sectors of memory. This can be achieved via programming equipment. The Write Protect ( WP ) features protects the 16 Kbyte boot sector from erasure by asserting a logic low on the WP pin, whether or not the sector had been previously protected. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any other se ctor that is not selected for erasure. True background erase can thus be achieved. The hardware RESET pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. The device offers power-savi ng features. The system can place the device into the st andby mode. Power consumption is greatly reduced in the standby modes. Pin Configurations „ TSOP (I) A29160AV A14 A13 A12 A11 A10 NC WE RESETNC WP RY/BYA18

33 I/O

I/O15(A-1) VSS BYTE A16A15 A19 24 25

32 I/O 9

(August, 2014, Version 1.2) 3 AMIC Technology, Corp. Pin Configurations (continued)

(August, 2014, Version 1.2) 4 AMIC Technology, Corp. Block Diagram Pin Descriptions Pin No. Description A0 - A19 Address Inputs I/O0 - I/O14 Data Inputs/Outputs I/O15 Data Input/Output, Word Mode I/O15 (A-1) A-1 LSB Address Input, Byte Mode CE Chip Enable WE Write Enable WP Write Protection OE Output Enable RESET Hardware Reset BYTE Selects Byte Mode or Word Mode RY/BY Ready/BUSY - Output VSS Ground VCC Power Supply NC Pin not connected internally State Control Command Register Address Latch X-decoder Y-Decoder Chip Enable Output Enable Logic Cell Matrix Y-Gating VCC Detector PGM Voltage Generator Data Latch Input/Output BuffersErase Voltage Generator VCC VSS WE CE OE A0-A19 I/O0 - I/O15 (A-1) Timer STB STB RESET Sector Switches BYTE RY/BY WP

(August, 2014, Version 1.2) 5 AMIC Technology, Corp.

1. Minimum DC voltage on input or I/O pins is -0.5V. During
2. Minimum DC input voltage on A9, OE and RESET is -

may overshoot VSS to -2.0V for periods of up to 20ns. overshoot to 12.5V for periods up to 20ns.

1. No more than one output is s horted at a time. Duration of

the short circuit should not be greater than one second. Ratings" may cause permanent damage to this device. may affect device reliability. functionally of the device is guaranteed. these operations in further detail. Table 1. A29160A Device Bus Operations

1. Addresses are A19:A0 in word mode (BYTE=VIH), A19: A-1 in byte mode (BYTE=VIL).
2. See the “Sector Protection/Unprotection” section and Temporary Sector Unprotect for more information.
3. The 16Kbyte boot sector is protected from erasure when WP = VIL
4. In CMOS mode, WP must be at VCC or left floating.

(August, 2014, Version 1.2) 6 AMIC Technology, Corp. Word/Byte Configuration The BYTE pin determines whether the I/O pins I/O 15-I/O0 operate in the byte or word configuration. If the BYTE pin is set at logic ”1”, the device is in word configuration, I/O 15-I/O0 are active and controlled by CE and OE . If the BYTE pin is set at logic “0”, the device is in byte configuration, and only I/O 0-I/O7 are active and controlled by CE and OE . I/O8-I/O14 are tri-stated, and I/O 15 pin is used as an input for the LSB(A-1) address function. Requirements for Reading Array Data To read array data from the out puts, the system must drive the CE and OE pins to V IL. CE is the power control and selects the device. OE is the output cont rol and gates array data to the output pins. WE should remain at VIH all the time during read operation. The BYTE pin determines whether the device outputs array data in words and bytes. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the devi ce data outputs. The device remains enabled for read access until the command register contents are altered. See "Reading Array Data" for more information. Refer to the AC Read Operations table for timing specifications and to the Read Operations Timings diagram for the timing waveforms, l CC1 in the DC Characteristics table represents the active current specification for reading array data. Writing Commands/Command Sequences To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE and CE to V IL, and OE to V IH. For program operations, the BYTE pin determines whether the device accepts program data in bytes or words, Refer to “Word/Byte Configuration” for more information. The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The “Word/Byte Program Command Sequence” and “Unlock Bypass Command Sequence” has detail descriptions on programming data to the device using both standard and Unlock Bypass command sequence. An erase operation can erase one sector, multiple sect ors, or the ent ire device. The Sector Address Tables indicate the address range that each sector occupies. A "sector address" consists of the address inputs required to uniquely select a sector. See the "Command Definitions" section for details on erasing a sector or the entire chip, or sus pending/resuming the erase operation. After the system writes the autoselect command sequence, the device enters the autoselec t mode. The system can then read autoselect codes from the in ternal register (which is separate from the memory array) on I/O 7 - I/O 0. Standard read cycle timings apply in this mode. Refer to the "Autoselect Mode" and "Autoselect Command Sequence" sections for more information. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The "AC Characteristics" section contai ns timing specification tables and timing diagrams for write operations. Program and Erase Operation Status During an erase or program operation, the system may check the status of the operation by readin g the status bits on I/O 7 - I/O 0. Standard read cycle timings and I CC read specifications apply. Refer to "Write Operation Status" for more information, and to each AC Characteristics section for timing diagrams. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatl y reduced, and the outputs are placed in the high impedanc e state, indepen dent of the OE input. The device enters the CMOS standby mode when the CE & RESET pins are both held at VCC ± 0.5V. (Note that this is a more restricted voltage range than V IH.) If CE and RESET are held at V IH, but not within VCC ± 0.5V, the device will be in the standby mode, but the st andby current will be greater. The device requires the standard access time (t CE) before it is ready to read data. If the device is deselected during erasure or programming, the device draws active curr ent until the operation is completed. ICC3 and ICC4 in the DC Characteristics tables represent the standby current specification. Output Disable Mode When the OE input is at V IH, output from the device is disabled. The output pins are placed in the high impedance state. RESET : Hardware Reset Pin The RESET pin provides a hardware method of resetting the device to reading array data. When the system drives the RESET pin low for at least a period of t RP, the device immediately terminates any operat ion in progress, tristates all data output pins, and ignores all read/write attempts for the duration of the RESET pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced fo r the duration of the RESET pulse. When RESET is held at VSS ± 0.5V, the device draws CMOS standby current (I CC4). If RESETis held at V IL but not within VSS ± 0.5V, the standby current will be greater. The RESET pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET is asserted during a progr am or erase operation, the RY/ BY pin remains a “0” (busy) until the internal reset operation is complete, which requires a time t READY (during Embedded Algorithms). The sy stem can thus monitor RY/ BY to determine whether the reset operation is complete. If RESET is asserted when a program or erase

(August, 2014, Version 1.2) 7 AMIC Technology, Corp. the RESET pin return to VIH. Table 2. A29160A Top Boot Block Sector Address Table Address range is A19 : A-1 in byte mode and A19 : A0 in word mode. See “Word/Byte Configuration” section.

(August, 2014, Version 1.2) 8 AMIC Technology, Corp. Table 3. A29160A Bottom Boot Block Sector Address Table Address range is A19 : A-1 in byte mode and A19 : A0 in word mode. See “Word/Byte Configuration” section.

(August, 2014, Version 1.2) 9 AMIC Technology, Corp. also be accessed in-system through the command register. Table 4. A29160A Autoselect Codes (High Voltage Method) L=Logic Low= VIL, H=Logic High=VIH, SA=Sector Address, X=Don’t Care. Note: The autoselect codes may also be accessed in-system via command sequences.

(August, 2014, Version 1.2) 10 AMIC Technology, Corp. erase operations in previously protected sectors. unprotected. See “Autoselect Mode” for details. The device is shipped with all sectors unprotected. unprotected. See "Autoselect Mode" for details. inadvertent writes (refer to the Command Definitions table). program/erase circuits are disabled, and the device resets. do not initiate a write cycle. WE must be a logical zero while OE is a logical one. reading array data on the initial power-up. Unprotect mode is activated by setting the RESET pin to VID. programmed or erased by select ing the sector addresses. shows the timing waveforms, for this feature.

1. All protected sectors unprotected.
2. All previously protected sectors are protected once again.

Figure 1. Temporary Sector Unprotect Operation

(August, 2014, Version 1.2) 11 AMIC Technology, Corp. Figure 2. In-System Sector Protect/Unprotect Algorithms

(August, 2014, Version 1.2) 12 AMIC Technology, Corp. interface for long-term compatibility. mode, the upper address bits (A7-MSB) must be all zeros. reset command to return the device to the autoselect mode. Table 5. CFI Query Identification String Table 6. System Interface String

(August, 2014, Version 1.2) 13 AMIC Technology, Corp. Table 7. Device Geometry Definition

(August, 2014, Version 1.2) 14 AMIC Technology, Corp. Table 8. Primary Vendor-Specific Extended Query

(August, 2014, Version 1.2) 15 AMIC Technology, Corp. Command Definitions Writing specific address and data commands or sequences into the command register initiates device operations. The Command Definitions table defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. All addresses are latched on the falling edge of WE or CE , whichever happens later. All data is latched on the rising edge of WE or CE , whichever happens first. Refer to the appropriate timing diagrams in the "AC Characteristics" section. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See "Erase Suspend/Erase Resume Commands" for more information on this mode. The system must issue the reset command to re-enable the device for reading array data if I/O 5 goes high, or while in the autoselect mode. See the "Reset Command" section, next. See also "Requirements for Reading Array Data" in the "Device Bus Operations" section for more information. The Read Operations table provi des the read parameters, and Read Operation Timings diagram shows the timing diagram. Reset Command Writing the reset command to t he device resets the device to reading array data. Address bits are don't care for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend). If I/O5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. The Command Definitions table shows the address and data requirements. This method is an alternative to that shown in the Autoselect Codes (High Voltage Method) table, which is intended for PROM programmers and requires VID on address bit A9. The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. The device then enters the autoselec t mode, and the system may read at any address any number of times, without initiating another command sequence. A read cycle at address XX00h retrieves the manufacturer code and another read cycle at XX11h retrieves the continuation code. A read cycle at address XX01h returns the device code. A read cycle containing a sector address (SA) and the address 02h in returns 01h if that sector is protected, or 00h if it is unprotected. Refer to the Sector Address tables for valid sector addresses. When a Read occurs at an address within the 16Kbyte boot sector (SA 34 for the top boot devices and SA0 for the bottom boot devices), the input on the WP pin may determine what code is returned. 16Kbyte Sector Protection WP Input Autoselect Code Protected V IH 01 (Protected) Protected V IL 01 (Protected) Unprotected V IH 00 (Unprotected) Unprotected V IL 01 (Protected) 1 Note 1. Sector is protected fr om erasure. Programming within the sector is still permitted. The system must write the reset command to exit the autoselect mode and return to reading array data. Word/Byte Program Command Sequence The system may program the device by word or byte, depending on the state of the BYTE pin. Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The dev ice automatically provides internally generated program pulses and verify the programmed cell margin. Table 9 shows the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are longer latched. The system c an determine the st atus of the program operation by using I/O 7, I/O6, or RY/ BY . See “White Operation Status” for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the progr amming operation. The Byte Program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a “0” back to a “1”. Attempting to do so may halt the operation and set I/O5 to “1”, or cause the Data Polling algorithm to indicate the operation was successful. Howe ver, a succeeding read will show that the data is still “0 ”. Only erase operations can convert a “0” to a “1”.

(August, 2014, Version 1.2) 18 AMIC Technology, Corp. Table 9. A29160A Command Definitions RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data latches on the rising edge of WE or CE pulse, whichever happens first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A19 - A12 select a unique sector.

1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles are write operation.
4. Address bits A19 - A11 are don't cares for unlock and command cycles, unless SA or PA required.
5. No unlock or command cycles required when reading array data.
6. The Reset command is required to return to reading arra y data when device is in the autoselect mode, or if I/O 5 goes high

(while the device is providing status data).

1. The fourth cycle of the autoselec t command sequence is a read cycle.
2. The data is 00h for an unprotected sect or and 01h for a protected sector. See "A utoselect Command Sequence" for more
3. Command is valid when device is ready to read array data or when device is in autoselect mode.
4. The Unlock Bypass command is required prior to the Unlock Bypass Program command.
5. The Unlock Bypass Reset command is required to return to reading array data when the device is in the Unlock Bypass
6. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode.
7. The Erase Resume command is valid only during the Erase Suspend mode.

(August, 2014, Version 1.2) 19 AMIC Technology, Corp. the A29160A to determine the st atus of a write operation. program or erase command sequence. 7 the complement of the datum programmed to I/O 7. complete, the device outputs the datum programmed to I/O 7. sectors, and ignores the selected sectors that are protected. Polling on I/O7. Figure 5 shows the Data Polling algorithm.

1. VA = Valid address for programming. During a sector

address is any non-protected sector address. I/O7 may change simultaneously with I/O5. Figure 5. Data Polling Algorithm

(August, 2014, Version 1.2) 20 AMIC Technology, Corp. RY/BY : Read/Busy The RY/ BY is a dedicated, open-drain output pin that indicates whether an Embedded algorithm is in progress or complete. The RY/ BY status is valid after the rising edge of the final WE pulse in the command sequence. Since RY/ BY is an open-drain output, several RY/ BY pins can be tied together in parallel with a pull-up resistor to VCC. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is ready to read array data (inc luding during the Erase Suspend mode), or is in the standby mode. Table 10 shows the outputs for RY/ BY . Refer to “ RESET Timings”, “Timing Waveforms for Program Operation” and “Timing Waveforms for Chip/Sector Erase Operation” for more information. I/O6: Toggle Bit I Toggle Bit I on I/O 6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE pulse in the command sequence (prior to the program or erase operation) , and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause I/O 6 to toggle. (The system may use either OE or CE to control the read cycles.) When the operation is complete, I/O6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, I/O 6 toggles for approximately 100μs, then returns to reading array data. If not all selected sectors are pr otected, the Embedded Erase algorithm erases the unprotec ted sectors, and ignores the selected sectors that are protected. The system can use I/O 6 and I/O 2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), I/O6 toggles. When the device enters the Erase Suspend mode, I/O 6 stops toggling. However, the system must also use I/O 2 to determine which sectors are erasing or erase- suspended. Alternatively, the system can use I/O 7 (see the subsection on " I/O 7: Data Polling"). If a program address falls within a protected sector, I/O 6 toggles for approximately 2 μs after the program command sequence is written, then returns to reading array data. I/O6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. The Write Operation Status table shows the outputs for Toggle Bit I on I/O 6. Refer to Figure 6 for the toggle bit algorithm, and to the Toggle Bit Timings figure in the "AC Characteristics" section for the timing diagram. The I/O 2 vs. I/O6 figure shows the differences between I/O 2 and I/O 6 in graphical form. See also the subsection on " I/O 2: Toggle Bit II". I/O2: Toggle Bit II The "Toggle Bit II" on I/O 2, when used with I/O 6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE pulse in the command sequence. I/O2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE or CE to control the read cycles.) But I/O 2 cannot distinguish whether the sect or is actively erasing or is erase-suspended. I/O6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required fo r sector and mode information. Refer to Table 10 to compare outputs for I/O2 and I/O6. Figure 6 shows the toggle bit algor ithm in flowchart form, and the section " I/O 2: Toggle Bit II" explains the algorithm. See also the " I/O 6: Toggle Bit I" subsection. Refer to the Toggle Bit Timings figure for the togg le bit timing diagram. The I/O 2 vs. I/O6 figure shows the differences between I/O 2 and I/O6 in graphical form. Reading Toggle Bits I/O6, I/O2 Refer to Figure 6 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read I/O7 - I/O 0 at least twice in a row to determine whether a toggle bit is toggling. Typically, a system would note and store the value of the toggle bit after the first read. After the second read, the system would compar e the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or eras e operation. The system can read array data on I/O7 - I/O0 on the following read cycle. However, if after the initia l two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of I/O 5 is high (see the section on I/O 5). If it is, the system should then determine again whether the toggle bit is togg ling, since the toggle bit may have stopped toggling just as I/O 5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and I/O 5 has not gone high. The system may continue to monitor the toggle bit and I/O 5 through successive read cycles, determining the status as described in the previous paragr aph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 6). I/O5: Exceeded Timing Limits I/O5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions I/O5 produces a "1." This is a failure condition that indicates the program or erase cycle was not successfully completed.

(August, 2014, Version 1.2) 21 AMIC Technology, Corp. command to return the device to reading array data. accepted. Table 10 shows the outputs for I/O3.

1. Read toggle bit twice to determine whether or not it is
2. Recheck toggle bit because it may stop toggling as I/O

Figure 6. Toggle Bit Algorithm

(August, 2014, Version 1.2) 22 AMIC Technology, Corp. Table 10. Write Operation Status

1. I/O 7 and I/O2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
2. I/O5 switches to “1” when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

See “I/O5: Exceeded Timing Limits” for more information.

(August, 2014, Version 1.2) 23 AMIC Technology, Corp. DC Characteristics CMOS Compatible Parameter Symbol Parameter Description Test Description Min. Typ. Max. Unit ILI Input Leakage Current V IN = VSS to VCC. VCC = VCC Max ±2.0 μA ILIT A9 Input Load Current VCC = V CC Max, A9 =11.5V 35 μA ILO Output Leakage Current V OUT = VSS to VCC. VCC = VCC Max ±2.0 μA

5 MHz 8 40 CE = VIL, OE = VIH

Byte Mode 1 MHz 1.6 8

5 MHz 12 50

ICC1 VCC Active Read Current (Notes 1, 2) CE = VIL, OE = VIH Word Mode 1 MHz 2.4 10 mA ICC2 VCC Active Write (Program/Erase) Current (Notes 2, 3, 4) CE = VIL, OE =VIH 30 50 mA ICC3 VCC Standby Current (Note 2) CE = VIH, RESET= VCC ± 0.5V WP = VCC or Float 6 150 uA ICC4 VCC Standby Current During Reset (Note 2) RESET= VSS ± 0.5V WP = VCC or Float 6 150 μA VIL Input Low Level -0.5 0.8 V VIH Input High Level 3.3 VCC + 0.5 V VID Voltage for Autoselect and Temporary Unprotect Sector VCC = 5.0 V 9.5 10.5 11.5 V VOL Output Low Voltage I OL = 6.0mA, VCC = VCC Min 0.45 V VOH1 I OH = -2.5 mA, VCC = VCC Min 0.8 x VCC V VOH2 Output High Voltage IOH = -100 μA, VCC = VCC Min VCC - 0.4 V VLKO Low VCC Lockout Voltage (Note 4) 3.1 3.6 4.1 V Notes: 1. The ICC current listed is typically less than 2mA/MHz, withOE at VIH. Typical VCC is 5.0V. 2. Maximum ICC specifications are tested with VCC = VCC max. 3. ICC active while Embedded Algorithm (program or erase) is in progress. 4. Not 100% tested.

(August, 2014, Version 1.2) 24 AMIC Technology, Corp. DC Characteristics (continued) Typical Word Mode Active Read Current, T=25°C 0.0 5.0 10.0 15.0 20.0 25.0 30.0 23456789 1 0 Frequency In MHz Power Supply Current in mA 4.5V 5.0V 5.5V

(August, 2014, Version 1.2) 25 AMIC Technology, Corp. AC Characteristics Read Only Operations Parameter Symbols Speed JEDEC Std Description Test Setup -55 Unit tAVAV t RC Read Cycle Time (Note 1) Min. 55 ns tAVQV t ACC Address to Output Delay CE = VIL OE = VIL Max. 55 ns tELQV tCE Chip Enable to Output Delay OE = VIL Max. 55 ns tGLQV t OE Output Enable to Output Delay Max. 25 ns Read Min. 0 ns tOEH Output Enable Hold Time (Note 1) Toggle and Data Polling Min. 10 ns tEHQZ tDF Chip Disable to Output High Z (Notes 1) Max. 20 ns tGHQZ t DF Output Disable to Output High Z (Notes 1) Max. 20 ns tAXQX t OH Output Hold Time from Addresses, CE or OE , Whichever Occurs First (Note 1) Min. 0 ns Notes: 1. Not 100% tested. 2. See Test Conditions and Test Setup for test specifications. Timing Waveforms for Read Only Operation Addresses Addresses Stable CE OE WE Output Valid High-ZOutput tRC tOEH tOE tCE High-Z tOH tDF tACC RESET RY/BY

(August, 2014, Version 1.2) 26 AMIC Technology, Corp. AC Characteristics Hardware Reset (RESET ) Parameter JEDEC Std Description Test Setup All Speed Options Unit tREADY RESET Pin Low (During Embedded Algorithms) to Read or Write (See Note) Max 20 μs tREADY RESET Pin Low (Not During Embedded Algorithms) to Read or Write (See Note) Max 500 ns t RP RESET Pulse Width Min 500 ns t RH RESET High Time Before Read (See Note) Min 50 ns t RB RY/BY Recovery Time Min 0 ns t RPD RESET Low to Standby Mode Min 20 μs Note: Not 100% tested. RESET Timings CE, OE RESET tRH tRP tReady Reset Timings NOT during Embedded Algorithms RESET tRP Reset Timings during Embedded Algorithms RY/BY tRB tReady CE, OE RY/BY

(August, 2014, Version 1.2) 27 AMIC Technology, Corp. Temporary Sector Unprotect Parameter JEDEC Std Description All Speed Options Unit t VIDR V ID Rise and Fall Time (See Note) Min 500 ns t RSP RESET Setup Time for Temporary Sector Unprotect Min 4 μs Note: Not 100% tested. Temporary Sector Unprotect Timing Diagram AC Characteristics Word/Byte Configuration (BYTE) Parameter JEDEC Std Description All Speed Options Unit t ELFL/tELFH CE to BYTE Switching Low or High Max 5 ns t FLQZ BYTE Switching Low to Output High-Z Max 25 ns t HQV BYTE Switching High to Output Active Min 55 ns Program or Erase Command Sequence RESET 10.5V 0 or 5V tVIDR tVIDR 0 or 5V tRSP CE WE RY/BY

(August, 2014, Version 1.2) 28 AMIC Technology, Corp. Data Output (I/O0-I/O14) Data Output (I/O0-I/O7) I/O15 Output Address Input Data Output (I/O0-I/O14) Data Output (I/O0-I/O7) I/O15 OutputAddress Input tFHQV tFLQZ tELFH tELFL CE OE BYTE I/O0-I/O14 I/O15 (A-1) BYTE I/O0-I/O14 I/O15 (A-1) BYTE Switching from word to byte mode BYTE Switching from byte to word mode BYTE Timings for Read Operations BYTE Timings for Write Operations Note: Refer to the Erase/Program Operations table for tAS and tAH specifications. The falling edge of the last WE signal tHOLD(tAH) tSET (tAS) CE BYTE WE

(August, 2014, Version 1.2) 29 AMIC Technology, Corp. AC Characteristics Erase and Program Operations Parameter Speed JEDEC Std

Description

-55 Unit tAVAV t WC Write Cycle Time (Note 1) Min. 55 ns tAVWL t AS Address Setup Time Min. 0 ns tWLAX t AH Address Hold Time Min. 40 ns tDVWH t DS Data Setup Time Min. 30 ns tWHDX t DH Data Hold Time Min. 0 ns t OES Output Enable Setup Time Min. 0 ns tGHWL t GHWL Read Recover Time Before Write (OE high to WE low) Min. 0 ns tELWL t CS CE Setup Time Min. 0 ns tWHEH t CH CE Hold Time Min. 0 ns tWLWH t WP Write Pulse Width Min. 35 ns tWHWL t WPH Write Pulse Width High Min. 20 ns Byte Typ. 6 tWHWH1 t WHWH1 Byte Programming Operation (Note 2) Word Typ. 11 μs tWHWH2 t WHWH2 Sector Erase Operation (Note 2) Typ. 0.3 sec t vcs VCC Set Up Time (Note 1) Min. 50 μs t RB Recovery Time from RY/BY Min 0 ns t BUSY Program/Erase Valid to RY/BY Delay Min 30 ns Notes: 1. Not 100% tested. 2. See the "Erase and Programming Performance" section for more information.

(August, 2014, Version 1.2) 30 AMIC Technology, Corp. Timing Waveforms for Program Operation Addresses CE OE WE Data VCC A0h PD tWC PA Program Command Sequence (last two cycles) PA DOUT ~~~~ PA Status tAS tVCS Read Status Data (last two cycles) 555h tAH tWHWH1 tCH tWP tWPHtCS tDS tDH Note : 1. PA = program addrss, PD = program data, Dout is the true data at the program address. 2. Illustration shows device in word mode. tRB tBUSY RY/BY

(August, 2014, Version 1.2) 31 AMIC Technology, Corp. Addresses CE OE WE Data VCC 55h 30h tWC SA Erase Command Sequence (last two cycles) VA Complete ~~~~ VA In Progress tAS tVCS Read Status Data 2AAh tAH tWHWH2 tCH tWP tWPH tCS tDS tDH Note : 1. SA = Sector Address (for Sector Erase), VA = Valid Address for reading status data (see "Write Operaion Ststus"). 2. Illustratin shows device in word mode. 555h for chip erase 10h for chip erase tRBtBUSY RY/BY Timing Waveforms for Chip/Sector Erase Operation

(August, 2014, Version 1.2) 32 AMIC Technology, Corp. Timing Waveforms for Data Polling (During Embedded Algorithms) Addresses CE OE WE I/O7 tRC VAVA VA Complement ~~ Complement True Valid Data High-Z Status Data ~~ Status Data True Valid Data High-Z I/O0 - I/O6 tACC tCE tCH tOE tOEH tDF tOH Note : VA = Valid Address. Illustation shows first status cycle after command sequence, last status read cycle, and array data read cycle. tBUSY RY/BY High-Z

(August, 2014, Version 1.2) 33 AMIC Technology, Corp. Timing Waveforms for Toggle Bit (During Embedded Algorithms) Note: VA = Valid Address; not required for I/O 6. Illustration shows first two status cy cle after command sequence, last status read cycle, and array data read cycle. Addresses CE OE WE I/O6 , I/O2 tRC VAVA VA Valid Status tACC tCE tCH tOE tOEH tDF tOH VA Valid Status Valid Status Valid Data (first read) (second read) (stop togging) RY/BY tBUSY High-Z

(August, 2014, Version 1.2) 34 AMIC Technology, Corp. Timing Waveforms for Sector Protect/Unprotect VID Note : For sector protect, A6=0, A1=1, A0=0. For sector unprotect, A6=1, A1=1, A0=0 VIHRESET SA, A6, A1, A0 Data CE WE OE Valid* Valid* Valid* 60h 60h 40h Status Sector Protect/Unprotect Verify 1us Sector Protect:150us Sector Unprotect:15ms Timing Waveforms for I/O 2 vs. I/O6 Enter Embedded Erasing Erase Suspend Enter Erase Suspend Program Erase Resume WE I/O6 I/O2 Erase Erase Suspend Read Erase Suspend Read Erase Erase Complete I/O2 and I/O6 toggle with OE and CE Note : Both I/O6 and I/O2 toggle with OE or CE. See the text on I/O6 and I/O2 in the section "Write Operation Status" for more information. Erase Suspend Program ~~~~

(August, 2014, Version 1.2) 35 AMIC Technology, Corp. AC Characteristics Erase and Program Operations Alternate CE Controlled Writes Parameter Speed JEDEC Std -55 Unit tAVAV t WC Write Cycle Time (Note 1) Min. 55 ns tAVEL t AS Address Setup Time Min. 0 ns tELAX t AH Address Hold Time Min. 40 ns tDVEH t DS Data Setup Time Min. 30 ns tEHDX t DH Data Hold Time Min. 0 ns t OES Output Enable Setup Time Min. 0 ns tGHEL t GHEL Read Recover Time Before Write (OE High to WE Low) Min. 0 ns tWLEL t WS WE Setup Time Min. 0 ns tEHWH t WH WE Hold Time Min. 0 ns tELEH t CP CE Pulse Width Min. 35 ns tEHEL t CPH CE Pulse Width High Min. 20 ns Byte Typ. 6 tWHWH1 t WHWH1 Programming Operation (Note 2) Word Typ. 11 μs tWHWH2 t WHWH2 Sector Erase Operation (Note 2) Typ. 0.3 sec Notes: 1. Not 100% tested. 2. See the "Erase and Programming Perfo rmance" section for more information.

(August, 2014, Version 1.2) 36 AMIC Technology, Corp. Timing Waveforms for Alternate CE Controlled Write Operation Addresses WE OE CE Data 555 for program 2AA for erase PA DOUT ~~~~ I/O7 Data Polling Note : 1. PA = Program Address, PD = Program Data, SA = Sector Address, I/O7 = Complement of Data Input, DOUT = Array Data. 2. Figure indicates the last two bus cycles of the command sequence. PD for program 30 for sector erase 10 for chip erase tBUSY tWHWH1 or 2 tAH tAStWC tWH tCP tWS tCPH PA for program SA for sector erase 555 for chip erase A0 for program 55 for erase tRH tDS tDH ~~~~ RESET RY/BY Erase and Programming Performance Parameter Typ. (Note 1) Max. (Note 2) Unit Comments Sector Erase Time 0.3 1.5 sec Chip Erase Time 8 32 sec Excludes 00h programming prior to erasure Byte Programming Time 6 100 μs Word Programming Time 11 180 μs Byte Mode 8 16 sec Chip Programming Time (Note 3) Word Mode 3 12 sec Excludes system-level overhead (Note 5) Notes: 1. Typical program and erase times assume the following conditions: 25°C, 5.0V VCC, 10,000 cycles. Additionally, programming typically assumes checkerboard pattern. 2. Under worst case conditions of 90°C, VCC = 4.5V, 100,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum byte program time listed. If t he maximum byte program time given is exceeded, only then does the device set I/O5 = 1. See the section on I/O5 for further information. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 9 for further information on command definitions. 6. The device has a guaranteed minimum erase and program cycle endurance of 100,000 cycles.

(August, 2014, Version 1.2) 37 AMIC Technology, Corp. Latch-up Characteristics Description Min. Max. Input Voltage with respect to VSS on all I/O pins -1.0V VCC+1.0V VCC Current -100 mA +100 mA Input voltage with respect to VSS on all pins except I/O pins (including A9, OE and RESET) -1.0V 11.5V Includes all pins except VCC. Test conditions: VCC = 5.0V, one pin at time. TSOP Pin Capacitance Parameter Symbol Parameter Description Test Setup Typ. Max. Unit CIN Input Capacitance VIN=0 6 7.5 pF COUT Output Capacitance VOUT=0 8.5 12 pF CIN2 Control Pin Capacitance VIN=0 7.5 9 pF Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25°C, f = 1.0MHz Data Retention Parameter Test Conditions Min Unit 150°C 10 Years Minimum Pattern Data Retention Time 125°C 20 Years

(August, 2014, Version 1.2) 38 AMIC Technology, Corp. Test Conditions Test Specifications Test Condition -55 Unit Output Load 1 TTL gate Output Load Capacitance, CL (including jig capacitance) 30 pF Input Rise and Fall Times 5 ns Input Pulse Levels 0.0 - 3.0 V Input timing measurement reference levels 1.5 V Output timing measurement reference levels 1.5 V Test Setup 6.2 K Device Under Test CL Diodes = IN3064 or Equivalent 2.7 K 5.0 V Ω Ω

(August, 2014, Version 1.2) 39 AMIC Technology, Corp. Part Numbering Scheme A29 X Package Type V = 48-pin TSOP G = 48-ball BGA Device Version* A = A Chip Version Device Type A29 = AMIC 5V Single Bank Parallel NOR Flash Device Density 400 = 4Mbits 800 = 8Mbits 801 = 8Mbits 160 = 16Mbits Temperature* X Package Material F = PB free X * Optional XXXX / X Packing Q = Tape & Reel X T = Top Boot U = Bottom Boot XX Speed Grade C85 ~C40-U °+°= C70 ~C0Blank °+°=

(August, 2014, Version 1.2) 40 AMIC Technology, Corp.

Ordering Information

Part No. Access Time (ns) Active Read Current Typ. (mA) Program/Erase Current Typ. (mA) Standby Current Typ. (μA) Package A29160ATV-55F 48 Pin Pb-Free TSOP A29160ATV-55UF 48 Pin Pb-Free TSOP A29160ATG-55F 48 ball Pb-Free TFBGA A29160ATG-55UF 55 20 30 0.5 48 ball Pb-Free TFBGA -U is for industrial operating temperature range: -40°C to +85°C. Bottom Boot Sector Flash Part No. Access Time (ns) Active Read Current Typ. (mA) Program/Erase Current Typ. (mA) Standby Current Typ. (μA) Package A29160AUV-55F 48 Pin Pb-Free TSOP A29160AUV-55UF 48 Pin Pb-Free TSOP A29160AUG-55F 48 ball Pb-Free TFBGA A29160AUG-55UF 55 20 30 0.5 48 ball Pb-Free TFBGA -U is for industrial operating temperature range: -40°C to +85°C.

(August, 2014, Version 1.2) 41 AMIC Technology, Corp.

Package Information

TSOP 48L (Type I) Outline Dimensions unit: inches/mm E c D L θ Detail "A" 0.25 24 25 D y eS A1 A2 A Detail "A" b Dimensions in inches Dimensions in mm Symbol Min Nom Max Min Nom Max A1 0.002 - 0.006 0.05 - 0.15 c 0.004 - 0.008 0.12 - 0.20 E - 0.472 0.476 - 12.00 12.10 e 0.020 BASIC 0.50 BASIC S 0.011 Typ. 0.28 Typ. θ 0° - 8° 0° - 8° Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension S includes end flash.

(August, 2014, Version 1.2) 42 AMIC Technology, Corp.

48 Balls CSP (6 x 8 mm) Outline Dimensions unit: mm

(48TFBGA) H G F E D C B A TOP VIEW SIDE VIEW C SEATING PLANE 654321 BOTTOM VIEW Ball*A1 CORNER H G F E D C B A E e e D b 0.10 C A 123456 Dimensions in mm Symbol Min. Nom. Max. A - - 1.20 A1 0.20 0.25 0.30 b 0.30 - 0.40 D 5.90 6.00 6.10 D1 4.00 BSC e - 0.80 - E 7.90 8.00 8.10 E1 5.60 BSC