A29001_07 AMICC | Alldatasheet

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128K X 8 Bit CMOS 5.0 Volt-only, Boot Sector Flash Memory Document Title 128K X 8 Bit CMOS 5.0 Volt-only, Boot Sector Flash Memory

Revision History

Rev. No. History Issue Date Remark

0.0 Initial issue October 19, 2000 Preliminary

0.1 Change ILIT from 50µA to 100µA January 3, 2001

Change typical byte programming time from 7µs to 35µs

0.2 Erase VCC supply voltage for ± 5% devices in Operation Ranges February 6, 2001

Add the time limit tWPH max. = 50µs of command cycle sequence

0.3 Correct the Continuation ID command to hexadecimal August 21, 2001

0.4 Error Correction: December 24, 2002

P.8: Autoselect Command Sequence (line 15), XX11h → XX03h

1.0 Final version release October 7, 2003 Final

1.1 Add 32Pin Pb-Free TSOP package type for A290011UV-70(U)F & February 16, 2004

A290011TV-70(U)F

1.2 Add Pb-Free package type for all parts August 5, 2004

1.3 Add sTSOP package type. December 1, 2004 (December, 2004, Version 1.3) AMIC Technology, Corp.

128K X 8 Bit CMOS 5.0 Volt-only, Boot Sector Flash Memory (December, 2004, Version 1.3) 1 AMIC Technology, Corp.

Features

„ 5.0V ± 10% for read and write operations „ Access times: - 55/70/90 (max.) „ Current: - 20 mA typical active read current - 30 mA typical program/erase current - 1 µA typical CMOS standby „ Flexible sector architecture - 8 Kbyte/ 4 KbyteX2/ 16 Kbyte/ 32 KbyteX3 sectors - Any combination of sectors can be erased - Supports full chip erase - Sector protection: A hard ware m ethod of protecting sectors t o prev ent any in advertent program or erase o perations within that sector „ Top or bottom boot block configurations available „ Embedded Erase Algorithms - Embedded Er ase alg orithm will aut omatically er ase the entir e chi p or a ny co mbination of designated sectors and verify the erased sectors - Embedded Pr ogram a lgorithm automatic ally writes and verifies bytes at specified addresses „ Typical 100,000 program/erase cycles per sector „ 20-year data retention at 125°C - Reliable operation for the life of the system „ Compatible with JEDEC-standards - Pinout an d so ftware comp atible with si ngle-power- supply Flash memory standard - Superior inadvertent write protection „ Data Polling and toggle bits - Provides a software method of detecting completion of program or erase operations „ Erase Suspend/Erase Resume - Suspends a s ector erase operation to re ad data from, or program data to, a non-erasing sector, then resumes the erase operation „ Hardware reset pin (RESET ) - Hardware method to reset the device to reading array data (not available on A290011) „ Industrial operating temperature range: -40°C to +85°C for – U „ Package options: 32-pin P-DIP, PLCC, TSOP or sTSOP (Forward type) General Description The A29001 is a 5.0 volt-onl y Flash memory organized as 131,072 b ytes of 8 bits e ach. T he A29 001 offers th e RESET function, b ut i t is not av ailable on A 290011. T he

128 Kbytes of data are further divided into seven sectors for

flexible sector erase capability. The 8 bits of data appear on I/O0 - I/O7 while the addr esses are input on A0 to A16. The A29001 is offered in 32-pin PLCC, TSOP, sTSOP and PDIP packages. T his device is designe d to be programm ed i n- system with the standar d syst em 5.0 vol t VCC suppl y. Additional 12.0 volt VPP is not requir ed for in-system write or erase operations. Ho wever, the A29 001 can a lso b e programmed in standard EPROM programmers. The A29001 h as the first toggle bit, I/O 6, w hich indicates whether an Embedded Program or Erase is in progress, or it is in the Eras e Suspe nd. B esides th e I/O 6 toggle bit, the A29001 has a second toggl e bit, I/O 2, to indicate whether the address ed sector is being selected for erase. T he A29001 als o offers the abi lity to pro gram in the Erase Suspend mod e. The standar d A2900 1 offe rs access times of 55, 70 and 90 ns allowing high-speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chi p enable ( CE ), write enable ( WE ) and output enable (OE ) controls. The device requires o nly a s ingle 5.0 volt po wer supply for both rea d an d write functi ons. Internal ly generat ed a nd regulated v oltages are provided for the pr ogram an d eras e operations. The A29001 is entirel y soft ware command set compatible with the JEDEC singl e-power-supply F lash stand ard. Commands ar e written to the comma nd register us ing standard microproc essor write timings. Register contents serve as input to an internal state-machine that controls the erase an d p rogramming c ircuitry. W rite c ycles als o internally latch address es and data need ed for the programming and erase op erations. R eading d ata o ut of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by writing the proper program command sequence. This initiates the Embedded Program algorithm - an internal al gorithm that automaticall y times the pro gram pulse widths and v erifies p roper pr ogram margin. Device erasure occurs b y executing the proper erase command s equence. T his initiates the Em bedded Eras e algorithm - an intern al a lgorithm that automatical ly preprograms the arra y (if it is not alread y programme d) before executing the eras e operation. D uring er ase, the device a utomatically tim es the erase p ulse widths an d verifies proper erase margin. The host sy stem can detect w hether a pro gram or erase operation is c omplete b y re ading the I/O 7 ( Data Polling) and I/O 6 (toggle) status bits. A fter a program or erase cycle has bee n complete d, the devic e is read y t o rea d array data or accept another command.

The sector era se architecture allo ws memor y s ectors to be erase d and reprogramme d without affecting the data contents of ot her sectors. The A2 9001 is full y erased when shipped from the factory. The hardware sector protection feature disables operations for both program and erase in any combination of the sectors o f memory. This can be achieved via programming equipment. The Erase Suspend feature enables the user to put erase on hol d for an y p eriod of time to read data from, or program data to, an y other sector that is not selected for erasure. True background erase can thus be achieved. Power consumption is greatly reduced when the device is placed in the standby mode. The hard ware RESET pin terminat es an y o peration in progress and resets the internal state machine to readin g array data (This feature is not available on the A290011). Pin Configurations „ DIP „ PLCC RESET A16 A15 A12 I/O0 I/O1 I/O2 I/O3VSS I/O4 I/O5 I/O6 I/O7 CE A10 OE A13 WE NC A14 VCC A11 A29001/A290011 16 17 I/O0 21 CE I/O7 A10 A29001L/ A290011L OE A11 A13 A14 I/O1 I/O2 VSS I/O3 I/O4 I/O5 I/O6 A12 A15 A16 RESET VCC WE NC NC on A290011 NC on A290011 „ TSOP/sTSOP (Forward type) A29001V/A290011V A29001X/A290011X A13 A14 NC WE VCC A16 A15 A12 17 A3 I/O0 I/O1 I/O2 VSS I/O3 I/O4 I/O5 I/O6 I/O7 CE A10 OEA11 RESET NC on A290011 (December, 2004, Version 1.3) 2 AMIC Technology, Corp.

(N/A A290011) Pin Descriptions Pin No. Description A0 - A16 Address Inputs I/O0 - I/O7 Data Inputs/Outputs CE Chip Enable WE Write Enable OE Output Enable RESET Hardware Reset (N/A A290011) VSS Ground VCC Power Supply (December, 2004, Version 1.3) 3 AMIC Technology, Corp.

  1. Minimum DC voltage on in put or I/O pins is -0.5V.

+2.0V for periods up to 20ns.

  1. Minimum DC input voltage on A9 pins is -0.5V. During

overshoot VS S to -2.0V for perio ds of u p to 20ns. which may overshoot to 13.5V for periods up to 20ns.

  1. No mor e tha n on e o utput is shorte d a t a time.

Ratings" ma y cause perm anent damag e to this device. periods may affect device reliability. functionally of the device is guaranteed. Table 1. A29001/A290011 Device Bus Operations Note: 1. See the "Sector Protection/Unprotection" section and Temporary Sector Unprotect for more information.

  1. This function is not available on A290011.

(December, 2004, Version 1.3) 4 AMIC Technology, Corp.

Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE and OE pins to V IL. CE is th e po wer con trol and selects the device. OE is the output control and gate s array data to the output pins. WE should remain at VIH all the time duri ng read op eration. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no sp urious alteration of the memor y content occ urs during the p ower transition. No comman d is necessar y i n this mode to obtain arr ay data. Standar d microproc essor read c ycles that assert valid addresses on the device address inputs produce valid data on the device d ata o utputs. The device rema ins enabled for read access until the com mand reg ister contents are altered. See "Re ading Array D ata" fo r more information. Refer to the AC Read Operations table for timing specifications and to the Re ad Operations T imings d iagram for the timi ng waveforms, lCC1 in the DC Characteri stics table repres ents the active current specification for reading array data. Writing Commands/Command Sequences To write a c ommand or command s equence ( which includes pr ogramming data to the devic e and er asing sectors of memor y), the s ystem must drive WE and CE to VIL, and OE to VIH. An erase oper ation can erase one sector, multiple sectors, or the entire d evice. The Sector Address T ables in dicate t he ad dress ra nge th at eac h sector occupies. A "sector address" consists of the address inputs r equired to u niquely select a se ctor. See the "Command D efinitions" sect ion for d etails on eras ing a sector or the entire chip, or suspending/resuming the erase operation. After the system writes the autoselect command sequence, the devic e ent ers the autose lect mode. T he s ystem ca n then re ad autoselect c odes from the int ernal reg ister (which is separate from the memory array) on I/O 7 - I/O0. Standard read cy cle timings apply i n this mode. Refer to the "Autose lect Mode" a nd "Autos elect Comman d Sequence" sections for more information. ICC2 in the Characteristics table re presents the active current specif ication for the write mo de. The "AC Characteristics" section contains timing specification tables and timing diagrams for write operations. Program and Erase Operation Status During an erase or pro gram operati on, th e s ystem ma y check the status of the operation by reading the status bits on I/O 7 - I/O 0. Standard r ead c ycle timin gs and I CC re ad specifications apply. Refer to "Write Operation Status" for Standby Mode When the s ystem is not reading or writing to the device, it can plac e the device i n the standby mo de. In this mode, current cons umption is gr eatly red uced, and the o utputs are placed in the high impedance state, independent of the OE input. The device enters the CMOS standby mode when the CE & RESET pins ( CE only on A290 011) are both hel d at VCC ± 0.5V. ( Note that this is a more restricted voltage range than V IH.) The device enters the T TL standby mode when CE is hel d at V IH, w hile RESET (Not available on A290011) is h eld at VCC ±0.5V. The devic e requir es the standard access time (tCE) before it is ready to read data. If the device is deselected during erasure or programming, the devic e dr aws active cu rrent until the operati on i s completed. ICC3 in the DC Ch aracteristics tabl es represents th e standby current specification. Output Disable Mode When the OE input is at V IH, output from the device is disabled. The output pins are placed in the high impedance state. RESET : Hardware Reset Pin (N/A on A290011) The RESET pin provides a hardware method of re setting the device to r eading array data. When the system drives the RESET pin low for at least a period of t RP, the device immediately terminates any operation in progress, tristates all data output pins, and i gnores all read/write attempts for the durati on of the RESET pulse. T he devic e als o resets the intern al state machin e to readi ng arr ay d ata. T he operation th at w as interr upted sho uld be r einitiated once the device is ready to accept another command sequence, to ensure data integrity. The RESET pin may be tied to th e system reset circuitry. A sy stem rese t would thus a lso reset the F lash memor y, enabling the system to read t he boot-up firmware from the Flash memory. Refer to the AC Ch aracteristics tabl es for RESET parameters and diagram. more information, and to eac h AC Characte ristics section for timing diagrams. (December, 2004, Version 1.3) 5 AMIC Technology, Corp.

Table 2. A29001/A290011 Top Boot Block Sector Address Table Table 3. A29001/A290011 Bottom Boot Block Sector Address Table through the command register. mode req uires V ID (11.5V to 12.5 V) on ad dress pinA 9. details on using the autoselect mode. Table 4. A29001/A290011 Autoselect Codes (High Voltage Method) (December, 2004, Version 1.3) 6 AMIC Technology, Corp.

  1. All protected sectors unprotected.
  2. All previously protected sectors are protected once again.

Figure 1. Temporary Sector Unprotect Operation voltage (VID) on address pin A9 and the control pins. The device is shipped with all sectors unprotected. unprotected. See "Autoselect Mode" for details. avoid accidentally writing data to the array. WE do not initiate a write cycle. WE must be a logical zero while OE is a logical one. reading array data on the initial power-up. programmed or erased by selecting the sector addresses. diagram shows the timing waveforms, for this feature. (December, 2004, Version 1.3) 7 AMIC Technology, Corp.

Writing sp ecific addr ess and data c ommands or sequences into the comma nd reg ister in itiates d evice operations. T he Comman d Definitions tab le defi nes the valid r egister command s equences. W riting i ncorrect address and data valu es or writing th em in the improp er sequence resets the device to reading array data. All address es are latche d on the falling ed ge of WE or CE , whichever ha ppens later. Al l data is latched o n th e rising edge of WE or CE , whichever happens first. Refer to the ap propriate timin g dia grams in the " AC Characteristics" section. Reading Array Data The device is automatic ally set to reading array data after device power-up. No comm ands ar e req uired to retriev e data. T he d evice i s a lso ready to rea d a rray da ta a fter completing an Embed ded P rogram or Em bedded Erase algorithm. After the devic e accepts a n Erase Sus pend command, th e device enters the Erase S uspend mod e. The system can read array data using the standard read timings, except that if it r eads at an address within erase- suspended sectors, the devic e outputs status data. After completing a programmin g operati on in the Erase Suspend mo de, the s ystem ma y o nce a gain re ad arra y data with the same exc eption. See "Erase Suspe nd/Erase Resume Commands" for more information on this mode. The sy stem must issue the reset command to re-enabl e the device for reading array data if I/O5 goes high, or while in the autos elect mode. See the "Res et Command" section, next. See a lso "R equirements for Reading Arra y Data" i n the "Device Bus Operations" section for more information. The Read Operations table provides the read parameters, and Read Oper ation T imings diagr am sho ws the timing diagram. Reset Command Writing the reset command to the device resets the device to reading array data. Address bits are do n't care for this command. T he reset comm and m ay be written bet ween the seq uence c ycles in a n erase comm and se quence before eras ing begins. T his resets the devi ce to readin g array d ata. Once er asure begins, however, the devic e ignores reset commands until the operation is complete. The reset command ma y be written bet ween th e sequence cycles in a program command sequence before programming begins. T his resets the d evice to rea ding array data (also applies to programming in Erase Suspend mode). Once programming begins, h owever, the d evice ignores reset commands until the operation is complete. The reset command ma y be written bet ween th e sequence c ycles in a n auto select comma nd seq uence. Once in the autoselect mode, the reset command must be written to retu rn to rea ding array d ata (al so ap plies t o autoselect during Erase Suspend). If I/ O5 goes high dur ing a p rogram or er ase oper ation, writing the res et command r eturns the dev ice to readi ng array data (also applies during Erase Suspend). Autoselect Command Sequence The autosele ct command sequ ence al lows the host system to access the m anufacturer a nd devices c odes, and d etermine whether or n ot a sector is protected. T he Command Def initions tabl e sho ws the a ddress and d ata requirements. This method is an alternative to that sho wn in the Autos elect Codes (H igh Volta ge M ethod) ta ble, which is inte nded for PRO M programm ers and re quires VID on address bit A9. The autoselect command se quence is initiated by writing two u nlock c ycles, follo wed by th e autos elect command. The device then enters the autoselect mode, an d the system ma y r ead at an y a ddress an y number of times, without initiating another command sequence. A read cycle at address XX00h retrieves the manufacturer code a nd another rea d c ycle at XX03h retrieves the continuation code. A read c ycle at address XX01h returns the device code. A read c ycle containing a sector address (SA) and th e address 02h in returns 01h if that sector is protected, or 00h if it is unpr otected. Refer to the Sector Address tables for valid sector addresses. The s ystem must write the reset comma nd to exit the autoselect mode and return to reading array data. Byte Program Command Sequence Programming i s a four-bus-c ycle op eration. The progra m command sequence is initiated by writing two unlock write cycles, follo wed b y the pro gram set-up command. T he program address and data are written next, which in turn initiate the Em bedded Progr am algorithm. T he s ystem is not req uired t o prov ide further co ntrols or timings. T he device aut omatically pro vides intern ally g enerated program p ulses and verif y the pro grammed cell marg in. The Command Definitio ns table sho ws th e address an d data requ irements for the b yte pr ogram command sequence. When the Embed ded Program algorithm is complete, the device the n returns to readin g arra y d ata and addr esses are no lo nger latched. T he sy stem can determin e the status of the program operation by using I/O7 or I/O6. See "Write Operati on Status" for information o n these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a "0" back to a "1 ". Attempting to do so may halt the operation and set I/O5 to "1", or cause the Data Polling alg orithm to indicat e the oper ation was successful. However, a succeeding read will show that the data is still "0". Only erase operations can convert a "0" to a "1". (December, 2004, Version 1.3) 8 AMIC Technology, Corp.

cares" when writing the Erase Suspend command. (December, 2004, Version 1.3) 10 AMIC Technology, Corp.

  1. See the appropriate Command Definitions table for erase
  2. See "I/O3 : Sector Erase Timer" for more information.

Figure 3. Erase Operation time-out period and suspends the erase operation. information on these status bits. Operation Status" for more information. sequence when the device is in the Erase Suspend mode. "Autoselect Command Sequence" for more information.

Table 5. A29001/A290011 Command Definitions RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data latches on the rising edge of WE or CE pulse, whichever happens first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A16 - A12 select a unique sector.

  1. See Table 1 for description of bus operations.
  2. All values are in hexadecimal.
  3. Except when reading array or autoselect data, all bus cycles are write operation.
  4. Address bits A16 - A12 are don't cares for unlock and command cycles, unless SA or PA required.
  5. No unlock or command cycles required when reading array data.
  6. The Reset command is required to return to reading array data when device is in the autoselect mode, or if I/O5 goes high

(while the device is providing status data).

  1. The fourth cycle of the autoselect command sequence is a read cycle.
  2. The data is 00h for an unprotected sector and 01h for a protected sector. See "Autoselect Command Sequence" for more
  3. The system may read and program in non-erasing sectors, or enter the autoselect mo de, when in the Erase Suspe nd
  4. The Erase Resume command is valid only during the Erase Suspend mode.
  5. The time between each command cycle has to be less than 50µs.

(December, 2004, Version 1.3) 11 AMIC Technology, Corp.

  1. VA = Valid address for programming. During a sector

address is any non-protected sector address.

  1. I/O7 should be rechecked even if I/O5 = "1" because

I/O7 may change simultaneously with I/O5. Figure 4. Data Polling Algorithm completed, or whether the device is in Er ase Sus pend. pulse in the program or erase command sequence. for erasure to read valid status information on I/O7. (December, 2004, Version 1.3) 12 AMIC Technology, Corp.

I/O6: Toggle Bit I Toggle Bit I on I/O 6 indica tes whether a n Embedd ed Program or Er ase algorithm is in progr ess or complete, o r whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE pulse in th e co mmand sequence (pr ior to the progra m or erase op eration), an d during the sector erase time-out. During an Embed ded Pro gram or Erase algor ithm operation, suc cessive rea d cycl es to an y a ddress caus e I/O6 to toggle. (T he system may use either OE or CE to control the rea d cycles.) When the operatio n is complete, I/O6 stops toggling. After an erase command sequence is written, if all sectors selected for erasin g are protected, I/O 6 toggles for approximately 100µs, then returns to readi ng array data. If not all s elected sectors ar e protected, the Embe dded Erase al gorithm erases th e unprotect ed sectors, an d ignores the selected sectors that are protected. The sy stem can use I/O 6 a nd I/O 2 together to determin e whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase alg orithm is in progre ss), I/O 6 toggles. W hen the device e nters the Erase Suspe nd mod e, I/O 6 stops toggling. Ho wever, the s ystem must also use I/O 2 to determine which sectors are erasing or er ase-suspended. Alternatively, the s ystem can use I/O 7 (see the subsection on " I/O7 : Data Polling"). If a program address fa lls within a protected sector, I/O 6 toggles for approximately 2µs after the progr am command sequence is written, then returns to reading array data. I/O6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. The W rite Op eration Status table sh ows t he o utputs for Toggle Bit I on I/O 6. Refer to F igure 5 for the togg le b it algorithm, and to the Toggle Bit Timings figure in the "AC Characteristics" section for the timin g dia gram. The I/O 2 vs. I/O6 figure shows the differences between I/O2 and I/O6 in gr aphical form. See also the s ubsection on " I/O 2: Toggle Bit II". I/O2: Toggle Bit II The "Toggle Bit II" on I/O 2, when used with I/O6, indicates whether a particular sector is activel y erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is eras e-suspended. Toggle Bit II is valid after the rising e dge o f the final WE pulse i n th e co mmand sequence. I/O2 toggles when th e s ystem reads at ad dresses within those sectors that have b een selected for erasure. (T he system ma y u se either OE or CE to control the rea d cycles.) But I/O 2 cannot disti nguish whether the sector is actively erasing or is erase-susp ended. I/O 6, b y comparison, i ndicates whether the d evice is activel y erasing, or is in Eras e Susp end, b ut can not distin guish which sectors are selected fo r erasure. Thus, both status bits are required for sector and mode information. Refer to Table 6 to compare outputs for I/O2 and I/O6. Figure 5 sho ws the toggle bit algorithm in flo wchart form, and the section " I/O2: Toggle Bit II" explains the algorithm. See also the " I/O6: Toggle Bit I" subsecti on. Refer to t he Toggle Bit Timings figure for the toggle bit timing diagram. The I/O2 vs. I/O6 figure shows the differences between I/O2 and I/O6 in graphical form. Reading Toggle Bits I/O6, I/O2 Refer to F igure 5 for the follo wing discuss ion. W henever the system initially begins reading toggle bit status, it must read I/O7 - I/O0 at least twice in a row to determine whether a toggle bit is toggling. Typically, a system would note and store the valu e of t he toggle bit after the fi rst read. After the second read, the system would compare the new value of the toggle bit with the first. If the tog gle bit is not toggling, the d evice has com pleted the pro gram or erase operation. The system can r ead array data on I/O 7 - I/O0 on the following read cycle. However, if after the initi al t wo rea d c ycles, the s ystem determines tha t the toggle bit is still togg ling, the s ystem also should note whether the value of I/O5 is high (see the section on I/O 5). If it is, the system sho uld then determine again whether the toggle bit is toggling, since the toggle bit may have sto pped togg ling just as I/O 5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or eras e o peration. If it is still toggling, the device d id n ot complete the oper ation successfully, and the s ystem must write the reset command to return to reading array data. The remainin g scenari o i s that the system in itially determines that the toggl e bit is togg ling and I/O5 has no t gone high. The system may continue to monitor the toggle bit an d I/O 5 th rough success ive rea d c ycles, determini ng the status as descri bed in the prev ious para graph. Alternatively, it may choose to perform other system tasks. In this case, th e system must start at the be ginning of th e algorithm when it returns to determin e the status of th e operation (top of Figure 5). I/O5: Exceeded Timing Limits I/O5 indicates whether the program or er ase time h as exceeded a s pecified i nternal pu lse c ount limit. Unde r these cond itions I/O 5 produces a "1." This is a failur e condition that indicates the program or erase cycle was not successfully completed. The I/O5 failure condition may appear if the system tries t o program a "1 "to a locati on that is previ ously programmed to "0." Only an erase operation can change a "0" back to a "1." Un der this conditi on, the device halts t he o peration, and when the operati on h as exc eeded th e timing lim its, I/O5 produces a "1." Under both th ese con ditions, the s ystem must issue th e reset command to return the device to reading array data. I/O3: Sector Erase Timer After writing a sector er ase comma nd sequence, th e system ma y r ead I/O 3 to d etermine whether or not an erase operation has beg un. (The sector erase timer does not apply to the chip erase command.) If additional sectors are sel ected f or erasur e, the entire tim e-out also a pplies after each ad ditional s ector erase c ommand. W hen th e time-out is complete, I/O 3 s witches from "0" to "1." T he system ma y ignore I/O 3 if th e s ystem can guarantee that the time bet ween ad ditional sector erase commands will always be l ess than 50 µs. See als o the "Sector Erase Command Se quence" s ection. After the sector eras e command sequence is written, the system should read the status on I/O 7 ( Data Polling) or I/O6 (T oggle Bit 1) to ensure the de vice has acce pted the com mand sequence, (December, 2004, Version 1.3) 13 AMIC Technology, Corp.

check, the last command mi ght not have b een acc epted. Table 6 shows the outputs for I/O3.

  1. Read toggle bit twice to determine whether or not it is
  2. Recheck toggle bit because it may stop toggling as I/O5

Figure 5. Toggle Bit Algorithm (December, 2004, Version 1.3) 14 AMIC Technology, Corp.

Table 6. Write Operation Status

1 No toggle 0 N/A Toggle

  1. I/O 7 and I/O2 require a valid address when reading status information. Refer to the appropriate subsection for further
  2. I/O5 switches to “1” when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

See “I/O5: Exceeded Timing Limits” for more information. (December, 2004, Version 1.3) 15 AMIC Technology, Corp.

Parameter Description Test Description Min. Typ. Max. Unit ILI Input Load Current VIN = VSS to VCC. VCC = VCC Max ±1.0 µA ILIT A9,OE &RESET Input Load Current VCC = VCC Max, A9,OE & RESET=12.5V 100 µA ILO Output Leakage Current VOUT = VSS to VCC. VCC = VCC Max ±1.0 µA ICC1 VCC Active Read Current (Notes 1, 2) CE = VIL, OE = VIH 20 30 mA ICC2 VCC Active Write (Program/Erase) Current (Notes 2, 3, 4) CE = VIL, OE =VIH 30 40 mA ICC3 VCC Standby Current (Note 2) CE = VIH, RESET= VCC ± 0.5V 0.4 1.0 mA VIL Input Low Level -0.5 0.8 V VIH Input High Level 2.0 VCC+0.5 V VID Voltage for Autoselect and Temporary Unprotect Sector VCC = 5.25 V 10.5 12.5 V VOL Output Low Voltage IOL = 12mA, VCC = VCC Min 0.45 V VOH Output High Voltage IOH = -2.5 mA, VCC = VCC Min 2.4 V CMOS Compatible Parameter Symbol Parameter Description Test Description Min. Typ. Max. Unit ILI Input Load Current VIN = VSS to VCC, VCC = VCC Max ±1.0 µA ILIT A9,OE & RESET Input Load Current VCC = VCC Max, A9,OE & RESET= 12.5V 100 µA ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC Max ±1.0 µA ICC1 VCC Active Read Current (Notes 1,2) CE = VIL, OE = VIH 20 30 mA ICC2 VCC Active Program/Erase Current (Notes 2,3,4) CE = VIL, OE = VIH 30 40 mA ICC3 VCC Standby Current (Notes 2, 5) CE = RESET = VCC ± 0.5 V 1 5 µA VIL Input Low Level -0.5 0.8 V VIH Input High Level 0.7 x VCC VCC+0.3 V VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 5.25 V 10.5 12.5 V VOL Output Low Voltage IOL = 12.0 mA, VCC = VCC Min 0.45 V VOH1 IOH = -2.5 mA, VCC = VCC Min 0.85 x VCC V VOH2 Output High Voltage IOH = -100 µA. VCC = VCC Min VCC-0.4 V Notes for DC characteristics (both tables): 1. The ICC current listed includes both the DC operation current and the frequency dependent component (at 6 MHz). The frequency component typically is less than 2 mA/MHz, withOE at VIH. 2. Maximum ICC specifications are tested with VCC = VCC max. 3. ICC active while Embedded Algorithm (program or erase) is in progress. 4. Not 100% tested. 5. For CMOS mode only, ICC3 = 20µA max at extended temperatures (> +85°C). 6. RESET is not available on A290011. (December, 2004, Version 1.3) 16 AMIC Technology, Corp.

-55 -70 -90 Unit tAVAV tRC Read Cycle Time (Note 2) Min. 55 70 90 ns tAVQV tACC Address to Output Delay CE = VIL OE = VIL Max. 55 70 90 ns tELQV tCE Chip Enable to Output Delay OE = VIL Max. 55 70 90 ns tGLQV tOE Output Enable to Output Delay Max. 30 30 35 ns Read Min. 0 0 0 ns tOEH Output Enable Hold Time (Note 2) Toggle and Data Polling Min. 10 10 10 ns tEHQZ tDF Chip Enable to Output High Z Max. 18 20 20 ns tGHQZ tDF Output Enable to Output High Z 18 20 20 ns tAXQX tOH Output Hold T ime from Address es, CE or OE , Whichever Occurs First Min. 0 0 0 ns Notes: 1. Output driver disable time. 2. Not 100% tested. Timing Waveforms for Read Only Operation (RESET =VIH on A29001) Addresses Addresses Stable CE OE WE Output Valid High-ZOutput tRC tOEH tOE tCE High-Z tOH tDF tACC (December, 2004, Version 1.3) 17 AMIC Technology, Corp.

Hardware Reset (RESET )(N/A on A290011) Parameter JEDEC Std Description Test Setup All Speed Options Unit tREADY RESET Pin Low (During Embedded Algorithms) to Read or Write (See Note) Max 20 µs tREADY RESET Pin Low (Not During Embedded Algorithms) to Read or Write (See Note) Max 500 ns tRP RESET Pulse Width Min 500 ns tRH RESET High Time Before Read (See Note) Min 50 ns CE, OE RESET tRH tRP tReady Reset Timings NOT during Embedded Algorithms RESET tRP Reset Timings during Embedded Algorithms Note: Not 100% tested. RESET Timings Temporary Sector Unprotect (N/A on A290011) Parameter JEDEC Std Description All Speed Options Unit tVIDR VID Rise and Fall Time (See Note) Min 500 ns tRSP RESET Setup Time for Temporary Sector Unprotect Min 4 µs Program or Erase Command Sequence RESET 12V 0 or 5V tVIDR tVIDR 0 or 5V tRSP CE WE Note: Not 100% tested. Temporary Sector Unprotect Timing Diagram (December, 2004, Version 1.3) 18 AMIC Technology, Corp.

Erase and Program Operations Parameter Symbols Speed JEDEC Std

Description

-55 -70 -90 Unit tAVAV tWC Write Cycle Time (Note 1) Min. 55 70 90 ns tAVWL tAS Address Setup Time Min. 0 ns tWLAX tAH Address Hold Time Min. 40 45 45 ns tDVWH tDS Data Setup Time Min. 25 30 45 ns tWHDX tDH Data Hold Time Min. 0 ns tOES Output Enable Setup Time Min. 0 ns tGHWL tGHWL Read Recover Time Before Write (OE high to WE low) Min. 0 ns tELWL tCS CE Setup Time Min. 0 ns tWHEH tCH CE Hold Time Min. 0 ns tWLWH tWP Write Pulse Width Min. 30 35 45 ns Min. 20 ns tWHWL tWPH Write Pulse Width High Max. 50 µs tWHWH1 tWHWH1 Byte Programming Operation (Note 2) Typ. 7 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ. 1 sec tVCS VCC Set Up Time (Note 1) Min. 50 µs Notes: 1. Not 100% tested. 2. See the "Erase and Programming Performance" section for more information. (December, 2004, Version 1.3) 19 AMIC Technology, Corp.

Timing Waveforms for Program Operation Addresses CE OE WE Data VCC A0h PD tWC PA Program Command Sequence (last two cycles) PA DOUT ~~~~ PA Status tAS tVCS Read Status Data (last two cycles) 555h tAH tWHWH1 tCH tGHWL tWP tWPHtCS tDS tDH Note : PA = program addrss, PD = program data, Dout is the true data at the program address. (December, 2004, Version 1.3) 20 AMIC Technology, Corp.

Timing Waveforms for Chip/Sector Erase Operation Addresses CE OE WE Data VCC 55h 30h tWC SA Erase Command Sequence (last two cycles) VA Complete ~~~~ VA In Progress tAS tVCS Read Status Data 2AAh tAH tWHWH2 tCH tGHWL tWP tWPH tCS tDS tDH Note : SA = Sector Address. VA = Valid Address for reading status data. 555h for chip erase 10h for chip erase (December, 2004, Version 1.3) 21 AMIC Technology, Corp.

Timing Waveforms for Data Polling (During Embedded Algorithms) Addresses CE OE WE I/O7 tRC VAVA VA Complement ~~ Complement True Valid Data High-Z Status Data ~~ Status Data True Valid Data High-Z I/O0 - I/O6 tACC tCE tCH tOE tOEH tDF tOH Note : VA = Valid Address. Illustation shows first status cycle after command sequence, last status read cycle, and array data read cycle. (December, 2004, Version 1.3) 22 AMIC Technology, Corp.

Timing Waveforms for Toggle Bit (During Embedded Algorithms) Note: VA = Valid Address; not required for I/O6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle. Addresses CE OE WE I/O6 , I/O2 tRC VAVA VA Valid Status tACC tCE tCH tOE tOEH tDF tOH VA Valid Status Valid Status Valid Status (first read) (second read) (stop togging) (December, 2004, Version 1.3) 23 AMIC Technology, Corp.

Timing Waveforms for I/O2 vs. I/O6 AC Characteristics Erase and Program Operations Alternate CE Controlled Writes Enter Embedded Erasing Erase Suspend Enter Erase Suspend Program Erase Resume WE I/O6 I/O2 Erase Erase Suspend Read Erase Suspend Read Erase Erase Complete I/O2 and I/O6 toggle with OE and CE Note : Both I/O6 and I/O2 toggle with OE or CE. See the text on I/O6 and I/O2 in the section "Write Operation Statue" for more information. Erase Suspend Program ~~~~ Parameter Symbols Speed JEDEC Std -55 -70 -90 Unit tAVAV tWC Write Cycle Time (Note 1) Min. 55 70 90 ns tAVEL tAS Address Setup Time Min. 0 ns tELAX tAH Address Hold Time Min. 40 45 45 ns tDVEH tDS Data Setup Time Min. 25 30 45 ns tEHDX tDH Data Hold Time Min. 0 ns tGHEL tGHEL Read Recover Time Before Write Min. 0 ns tWLEL tWS WE Setup Time Min. 0 ns tEHWH tWH WE Hold Time Min. 0 ns tELEH tCP Write Pulse Width Min. 30 35 45 ns tEHEL tCPH Write Pulse Width High Min. 20 20 20 ns tWHWH1 tWHWH1 Byte Programming Operation (Note 2) Typ. 7 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ. 1 sec Notes: 3. Not 100% tested. 4. See the "Erase and Programming Performance" section for more information. (December, 2004, Version 1.3) 24 AMIC Technology, Corp.

Timing Waveforms for Alternate CE Controlled Write Operation Erase and Programming Performance Addresses WE OE CE Data 555 for program 2AA for erase PA DOUT ~~~~ I/O7 Data Polling Note : 1. PA = Program Address, PD = Program Data, SA = Sector Address, I/O7 = Complement of Data Input, DOUT = Array Data. 2. Figure indicates the last two bus cycles of the command sequence. PD for program 30 for sector erase 10 for chip erase tBUSY tWHWH1 or 2 tAH tAStWC tWH tGHEL tCP tWS tCPH PA for program SA for sector erase 555 for chip erase A0 for program 55 for erase tRH tDS tDH Parameter Typ. (Note 1) Max. (Note 2) Unit Comments Sector Erase Time 1 8 sec Chip Erase Time 8 64 sec Excludes 00h programming prior to erasure (Note 4) Byte Programming Time 35 300 µs Chip Programming Time (Note 3) 3.6 10.8 sec Excludes system-level overhead (Note 5) Notes: 1. T ypical program a nd er ase times ass ume the fol lowing co nditions: 25 °C, 5.0 V VCC, 10 0,000 c ycles. Add itionally, programming typically assumes checkerboard pattern. 2. Under worst case conditions of 90°C, VCC = 4.5V (4.75V for -55), 100,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the ma ximum byte program time liste d. If the maxi mum byte program time give n is exc eeded, only then does the device set I/O5 = 1. See the section on I/O5 for further information. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 4 for further information on command definitions. 6. The device has a guaranteed minimum erase and program cycle endurance of 100,000 cycles. (December, 2004, Version 1.3) 25 AMIC Technology, Corp.

Description Min. Max. Input Voltage with respect to VSS on all I/O pins -1.0V VCC+1.0V VCC Current -100 mA +100 mA Input voltage with respect to VSS on all pins except I/O pins (including A9, OE and RESET) -1.0V 12.5V Includes all pins except VCC. Test conditions: VCC = 5.0V, one pin at time. RESET N/A on A290011. TSOP/sTSOP Pin Capacitance Parameter Symbol Parameter Description Test Setup Typ. Max. Unit CIN Input Capacitance VIN=0 6 7.5 pF COUT Output Capacitance VOUT=0 8.5 12 pF CIN2 Control Pin Capacitance VIN=0 7.5 9 pF Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25°C, f = 1.0MHz PLCC and P-DIP Pin Capacitance Parameter Symbol Parameter Description Test Setup Typ. Max. Unit CIN Input Capacitance VIN=0 4 6 pF COUT Output Capacitance VOUT=0 8 12 pF CIN2 Control Pin Capacitance VPP=0 8 12 pF Notes: 3. Sampled, not 100% tested. 4. Test conditions TA = 25°C, f = 1.0MHz Data Retention Parameter Test Conditions Min Unit 150°C 10 Years Minimum Pattern Data Retention Time 125°C 20 Years (December, 2004, Version 1.3) 26 AMIC Technology, Corp.

Test Condition -55 All others Unit Output Load 1 TTL gate Output Load Capacitance, CL(including jig capacitance) 30 100 pF Input Rise and Fall Times 5 20 ns Input Pulse Levels 0.0 - 3.0 0.45 - 2.4 V Input timing measurement reference levels 1.5 0.8, 2.0 V Output timing measurement reference levels 1.5 0.8, 2.0 V Test Setup 6.2 KΩ Device Under Test CL Diodes = IN3064 or Equivalent 2.7 KΩ 5.0 V (December, 2004, Version 1.3) 27 AMIC Technology, Corp.

Ordering Information

Part No. Access Time (ns) Active Read Current Typ. (mA) Program/Erase Current Typ. (mA) Standby Current Typ. (µA) Package A29001T-55 32Pin DIP A29001T-55F 32Pin Pb-Free DIP A290011T-55 32Pin DIP A290011T-55F 32Pin Pb-Free DIP A29001TL-55 32Pin PLCC A29001TL-55F 32Pin Pb-Free PLCC A290011TL-55 32Pin PLCC A290011TL-55F 32Pin Pb-Free PLCC A29001TV-55 32Pin TSOP A29001TV-55F 32Pin Pb-Free TSOP A290011TV-55 32Pin TSOP A290011TV-55F 32Pin Pb-Free TSOP A29001TX-55 32Pin sTSOP A29001TX-55F 32Pin Pb-Free sTSOP A290011TX-55 32Pin sTSOP A290011TX-55F 55 20 30 1 32Pin Pb-Free sTSOP A29001T-70 32Pin DIP A29001T-70F 32Pin Pb-Free DIP A290011T-70 32Pin DIP A290011T-70F 32Pin Pb-Free DIP A29001TL-70 32Pin PLCC A29001TL-70F 32Pin Pb-Free PLCC A290011TL-70 32Pin PLCC A290011TL-70F 32Pin Pb-Free PLCC A29001TV-70 32Pin TSOP A29001TV-70F 32Pin Pb-Free TSOP A290011TV-70 32Pin TSOP A290011TV-70F 32Pin Pb-Free TSOP A290011TV-70UF 32Pin Pb-Free TSOP A29001TX-70 32Pin sTSOP A29001TX-70F 32Pin Pb-Free sTSOP A290011TX-70 32Pin sTSOP A290011TX-70F 32Pin Pb-Free sTSOP A290011TX-70UF 70 20 30 1 32Pin Pb-Free sTSOP (December, 2004, Version 1.3) 28 AMIC Technology, Corp.

Ordering Information (continued) Top Boot Sector Flash Part No. Access Time (ns) Active Read Current Typ. (mA) Program/Erase Current Typ. (mA) Standby Current Typ. (µA) Package A29001T-90 32Pin DIP A29001T-90F 32Pin Pb-Free DIP A290011T-90 32Pin DIP A290011T-90F 32Pin Pb-Free DIP A29001TL-90 32Pin PLCC A29001TL-90F 32Pin Pb-Free PLCC A290011TL-90 32Pin PLCC A290011TL-90F 32Pin Pb-Free PLCC A29001TV-90 32Pin TSOP A29001TV-90F 32Pin Pb-Free TSOP A290011TV-90 32Pin TSOP A290011TV-90F 32Pin Pb-Free sSOP A29001TX-90 32Pin sTSOP A29001TX-90F 32Pin Pb-Free sTSOP A290011TX-90 32Pin sTSOP A290011TX-90F 90 20 30 1 32Pin Pb-Free sTSOP Note: -U is for industrial operating temperature range (December, 2004, Version 1.3) 29 AMIC Technology, Corp.

Ordering Information (continued) Bottom Boot Sector Flash Part No. Access Time (ns) Active Read Current Typ. (mA) Program/Erase Current Typ. (mA) Standby Current Typ. (µA) Package A29001U-55 32Pin DIP A29001U-55F 32Pin Pb-Free DIP A290011U-55 32Pin DIP A290011U-55F 32Pin Pb-Free DIP A29001UL-55 32Pin PLCC A29001UL-55F 32Pin Pb-Free PLCC A290011UL-55 32Pin PLCC A290011UL-55F 32Pin Pb-Free PLCC A29001UV-55 32Pin TSOP A29001UV-55F 32Pin Pb-Free TSOP A290011UV-55 32Pin TSOP A290011UV-55F 32Pin Pb-Free TSOP A29001UX-55 32Pin sTSOP A29001UX-55F 32Pin Pb-Free sTSOP A290011UX-55 32Pin sTSOP A290011UX-55F 55 20 30 1 32Pin Pb-Free sTSOP A29001U-70 32Pin DIP A29001U-70F 32Pin Pb-Free DIP A290011U-70 32Pin DIP A290011U-70F 32Pin Pb-Free DIP A29001UL-70 32Pin PLCC A29001UL-70F 32Pin Pb-Free PLCC A290011UL-70 32Pin PLCC A290011UL-70F 32Pin Pb-Free PLCC A29001UV-70 32Pin TSOP A29001UV-70F 32Pin Pb-Free TSOP A290011UV-70 32Pin TSOP A290011UV-70F 32Pin Pb-Free TSOP A290011UV-70UF 32Pin Pb-Free TSOP A29001UX-70 32Pin sTSOP A29001UX-70F 32Pin Pb-Free sTSOP A290011UX-70 32Pin sTSOP A290011UX-70F 32Pin Pb-Free sTSOP A290011UX-70UF 70 20 30 1 32Pin Pb-Free sTSOP (December, 2004, Version 1.3) 30 AMIC Technology, Corp.

Ordering Information (continued) Bottom Boot Sector Flash Part No. Access Time (ns) Active Read Current Typ. (mA) Program/Erase Current Typ. (mA) Standby Current Typ. (µA) Package A29001U-90 32Pin DIP A29001U-90F 32Pin Pb-Free DIP A290011U-90 32Pin DIP A290011U-90F 32Pin Pb-Free DIP A29001UL-90 32Pin PLCC A29001UL-90F 32Pin Pb-Free PLCC A290011UL-90 32Pin PLCC A290011UL-90F 32Pin Pb-Free PLCC A29001UV-90 32Pin TSOP A29001UV-90F 32Pin Pb-Free TSOP A290011UV-90 32Pin TSOP A290011UV-90F 32Pin Pb-Free TSOP A29001UX-90 32Pin sTSOP A29001UX-90F 32Pin Pb-Free sTSOP A290011UX-90 32Pin sTSOP A290011UX-90F 90 20 30 1 32Pin Pb-Free sTSOP Note: -U is for industrial operating temperature range (December, 2004, Version 1.3) 31 AMIC Technology, Corp.

Package Information

P-DIP 32L Outline Dimensions unit: inches/mm EA2 AL EA D C θ B Base Plane Seating Plane e Dimensions in inches Dimensions in mm Symbol Min Nom Max Min Nom Max Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. (December, 2004, Version 1.3) 32 AMIC Technology, Corp.

PLCC 32L Outline Dimension unit: inches/mm A1 A2 A e D y HD D GD b GE c 21 29 E HE L θ Dimensions in inches Dimensions in mm Symbol Min Nom Max Min Nom Max Notes: 1. Dimensions D and E do not include resin fins. 2. Dimensions GD & GE are for PC Board surface mount pad pitch design reference only. (December, 2004, Version 1.3) 33 AMIC Technology, Corp.

TSOP 32L TYPE I (8 X 20mm) Outline Dimensions unit: inches/mm e LE L A c D y Detail "A" S b HD D E θ Detail "A" Dimensions in inches Dimensions in mm Symbol Min Nom Max Min Nom Max A1 0.002 - 0.006 0.05 - 0.15 c 0.004 - 0.008 0.11 - 0.20 E - 0.315 0.319 - 8.00 8.10 e 0.020 BSC 0.50 BSC θ 0° - 5° 0° - 5° Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension S includes end flash. (December, 2004, Version 1.3) 34 AMIC Technology, Corp.

sTSOP 32L TYPE I (8 X 13.4mm) Outline Dimensions unit: inches/mm e Detail "A" D 0.076MM Detail "A" S b E D LE L A c θ SEATING PLANE Dimensions in inches Dimensions in mm Symbol Min Nom Max Min Nom Max e 0.020 TYP 0.50 TYP S 0.0109 TYP 0.278 TYP Notes: 1. The maximum value of dimension D1 includes end flash. 2. Dimension E does not include resin fins. 3. Dimension S includes end flash. (December, 2004, Version 1.3) 35 AMIC Technology, Corp.