A26E001A AMICC | Alldatasheet

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Technical content

(November, 1998, Version 2.1) AMIC Technology, Inc. Document Title 2M and 256K MaskRAM

Revision History

Rev. No. History Issue Date Remark

2.0 Final spec release October 12, 1998 Final

2.1 Change tOE speed from 150ns to 200ns November 20, 1998

(November, 1998, Version 21) 1 AMIC Technology, Inc.

Features

nPower supply range: 1.8V to 3.3V nAccess time: 450 ns (max.) nCurrent: Low power version: Operating: 4mA (max.) Standby: 10µA (max.) nExtended operating temperature range: -25 °C to 85°C nFull static operation, no clock or refreshing required nAll inputs and outputs are CMOS compatible nCommon I/O using three-state output nData retention voltage: 1.6V (min.) nAvailable in 32-pin TSOP and sTSOP packages General Description The A26E001A is a low operating current 262,144 x 8 bit CMOS MASK ROM and 32,768 x 8 bit CMOS SRAM integrated into one chip. It operates on a low power supply voltage from 1.8V to 3.3V, with two chip selects to enable the MASK ROM or SRAM independently. Inputs and three-state outputs are CMOS compatible and allow for direct interfacing with common system bus structures. Minimum standby power is drawn by this device when ROMCE and RAMCE are at a high level, independent of the other input levels. Data retention is guaranteed at a power supply voltage as low as 1.6V. Pin Configuration Pin Description Pin No. Symbol Description 1 - 6, 10 - 20, 31 A0 - A17 Address Inputs

7 RAMCE SRAM Enable

9 WE Write Enable

21 - 23, 25 - 29 D0 - D7 Data Input/Outputs

30 ROMCE ROM Enable

32 OE Output Enable

8 VCC Power Supply

24 GND Ground

(November, 1998, Version 2.1) 2 AMIC Technology, Inc. Block Diagram ADDRESS BUFFER DATA BUFFER CIRCUIT CONTROL CIRCUIT RAM A0-A14 D0-D7 D0-D7 A0-A14 A15-A17 ROMCE OE WE RAMCE OE WE ROM D0 - D7 A15 - A17 A0 - A14 VCC GND WE OE RAMCE ROMCE Truth Table Mode ROMCE RAMCE OE WE D0 - D7 Supply Current Standby H H X X High Z ISB, ISB1 Output Disable L H H X High Z ICCR ROM Read L H L X DOUT ICCR Output Disable H L H H High Z ICCS SRAM Read H L L H DOUT ICCS SRAM Write H L X L DIN ICCS Notes: 1. X = H or L 2. A15 - A17 are only valid for ROM. 3. In case that ROMCE and RAMCE are "L" at the same time, both ROM and SRAM will be disabled.

(November, 1998, Version 2.1) 3 AMIC Technology, Inc. Recommended DC Operating Conditions (TA = -25°C to + 85°C) Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage 1.8 3.0 3.3 V GND Ground 0 0 0 V VIH Input High Voltage VCC x 0.7 - VCC + 0.3 V VIL Input Low Voltage -0.3 - VCC x 0.3 V Absolute Maximum Ratings* *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. Symbol Parameter Min. Max. Unit Conditions ILI Input Leakage Current - 1 µA VIN = GND to VCC ILO Output Leakage Current - 1 µA VI/O = GND to VCC ICCR ROM Operating Current - 4 mA Min. Cycle, Duty = 100% ROMCE = VIL and RAMCE = VIH, II/O = 0mA, VIN = VCC or GND ICCS SRAM Operating Current - 4 mA Min. Cycle, Duty = 100% ROMCE = VIH and RAMCE = VIL, II/O = 0mA, VIN = VCC or GND ISB - 50 µA ROMCE = VIH and RAMCE = VIH ISB1 Standby Supply Current - 10 µA ROMCE ≥ VCC - 0.2V and RAMCE ≥ VCC - o.2V VOL Output Low Voltage - 0.4 V IOL = 200µA VOH Output High Voltage VCC - 0.4 - V IOH = -200µA

(November, 1998, Version 2.1) 4 AMIC Technology, Inc. Capacitance (TA = 25°C, f = 1.0MHz) Symbol Parameter Min. Max. Unit Conditions CI* Input Capacitance 6 pF TA = 25°C CO* Input/Output Capacitance 8 pF f = 1.0MHz * These parameters are sampled and not 100% tested. AC Characteristics (ROM/SRAM Selection) (TA = -25°C to +85°C, VCC = 1.8V to 3.3V) Symbol Parameter Min. Max. Unit tRTS ROMCE Disable to RAMCE Enable Time 10 - ns tSTR RAMCE Disable to ROMCE Enable Time 10 - ns AC Characteristics (ROM Selected) (TA = -25°C to +85°C, VCC = 1.8V to 3.3V) Symbol Parameter Min. Max. Unit tRC Read Cycle Time 500 - ns tAA Address Access Time - 450 ns tACE ROMCE Chip Enable Access Time - 450 ns tOE Output Enable to Output Valid - 200 ns tCLZ ROMCE Chip Enable to Output in Low Z 10 - ns tOLZ Output Enable to Output in Low Z 10 - ns tCHZ ROMCE Chip Disable to Output in High Z - 100 ns tOHZ Output Disable to Output in High Z - 100 ns tOH Output Hold from Address Change 10 - ns Notes: tCHZ, and t OHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels.

(November, 1998, Version 2.1) 5 AMIC Technology, Inc. AC Characteristics (SRAM Selected) (TA = -25°C to +85°C, VCC = 1.8V to 3.3V) Symbol Parameter Min. Max. Unit Read Cycle tRC Read Cycle Time 500 - ns tAA Address Access Time - 450 ns tACE RAMCE Chip Enable Access Time - 450 ns tOE Output Enable to Output Valid - 200 ns tCLZ RAMCE Chip Enable to Output in Low Z 10 - ns tOLZ Output Enable to Output in Low Z 10 - ns tCHZ RAMCE Chip Disable to Output in High Z - 100 ns tOHZ Output Disable to Output in High Z - 100 ns tOH Output Hold from Address Change 10 - ns Write Cycle tWC Write Cycle Time 500 - ns tCW RAMCE Chip Enable to End of Write 220 - ns tAS Address Setup Time 0 - ns tAW Address Valid to End of Write 220 - ns tWP Write Pulse Width 200 - ns tWR Write Recovery Time 0 - ns tWHZ Write to Output in High Z - 100 ns tDW Data to Write Time Overlap 100 - ns tDH Data Hold from Write Time 0 - ns tOW Output Active from End of Write 10 - ns Notes: tCHZ, t OHZ and t WHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltag e levels.

(November, 1998, Version 2.1) 6 AMIC Technology, Inc. Timing Waveforms (ROM/SRAM Selection) tRTS tSTR RAMCE ROMCE Timing Waveforms (ROM Selected) Read from Address ( ROMCE = Active, OE = Active) tAA tRC tOH ADDRESS INPUTS DATA OUT Read from ROMCE Chip Enable or Output Enable (Address Valid) tOE tOHZ tCLZ DATA OUT tOLZ ROMCE tACE OE tCHZ

(November, 1998, Version 2.1) 7 AMIC Technology, Inc. Timing Waveforms (SRAM Selected) Read Cycle 1 (1) tRC tAA tOH Address DOUT tOHZ5 tCHZ5 tACE tCLZ5 tOLZ5 tOE OE RAMCE Read Cycle 2 (1, 2, 4) tRC tOH tAA tOH Address DOUT

(November, 1998, Version 2.1) 8 AMIC Technology, Inc. Timing Waveforms (SRAM Selected continued) Read Cycle 3 (1, 3, 4) tCLZ 5 tACE tCHZ 5 DOUT RAMCE Notes: 1. WE is high for Read Cycle. 2. Device is continuously enabled, RAMCE = VIL. 3. Address valid prior to or coincident with RAMCE transition low. 4. OE = VIL. 5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested. Write Cycle 1(6) (Write Enable Controlled) tWC Address DIN tOW 7 tDHtDW tWHZ 7 tWP2tAS1 (4) tCW5 tAW tWR 3 DOUT RAMCE WE

(November, 1998, Version 2.1) 9 AMIC Technology, Inc. Timing Waveforms (SRAM Selected continued) Write Cycle 2 (6) (Chip Enable Controlled) tWC Address DIN tDHtDW (4) tCW5 tAW tWR 3 DOUT tWHZ7 tWP2 tAS1RAMCE WE Notes: 1. tAS is measured from the address valid to the beginning of Write. 2. A Write occurs during the overlap (t WP) of a low RAMCE and a low WE . 3. tWR is measured from the earliest of RAMCE or WE going high to the end of the Write cycle. 4. If the RAMCE low transition occurs simultaneously with the WE low transition or after the WE transition, outputs remain in a high impedance state. 5. tCW is measured from the later of RAMCE going low to the end of Write. 6. OE level is high or low. 7. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.

(November, 1998, Version 2.1) 10 AMIC Technology, Inc. Figure 1. Output Load

(November, 1998, Version 2.1) 11 AMIC Technology, Inc.

Ordering Information

Part No. Access Time (ns) Operation Current Max. (mA) Standby Current Max. (mA) Package A26E001AV 450 4 10 32L TSOP A26E001AX 450 4 10 32L sTSOP

(November, 1998, Version 2.1) 12 AMIC Technology, Inc.

Package Information

TSOP 32L TYPE I (8 X 20mm) Outline Dimensions unit: inches/mm e LE L A c D y Detail "A" S b HD D E θ Detail "A" Dimensions in inches Dimensions in mm Symbol Min Nom Max Min Nom Max A1 0.002 - 0.006 0.05 - 0.15 c 0.004 - 0.008 0.11 - 0.20 E - 0.315 0.319 - 8.00 8.10 e 0.020 BSC 0.50 BSC θ 0° - 5° 0° - 5° Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension S includes end flash.

(November, 1998, Version 2.1) 13 AMIC Technology, Inc. sTSOP 32L TYPE I (8 X 13.4mm) Outline Dimensions unit: inches/mm e Detail "A" D 0.076MM Detail "A" S b E D LE L A c θ SEATING PLANE Dimensions in inches Dimensions in mm Symbol Min Nom Max Min Nom Max e 0.020 TYP 0.50 TYP S 0.0109 TYP 0.278 TYP Notes: 1. The maximum value of dimension D 1 includes end flash. 2. Dimension E does not include resin fins. 3. Dimension S includes end flash.