A25L20P AMICC | Alldatasheet
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A25L20P/A25L10P/A25L05P Series 2Mbit / 1Mbit / 512Kbit, Low Voltage, Serial Flash Memory With 85MHz SPI Bus Interface (August, 2007, Version 1.0) AMIC Technology Corp. Document Title 2Mbit / 1Mbit / 512Kbit, Low Voltage, Serial Flash Memory With 85MHz SPI Bus Interface
Revision History
Rev. No. History Issue Date Remark
0.0 Initial issue February 13, 2007 Preliminary
0.1 Add transient voltage (<20ns) on any pin to ground potential spec. April 24, 2007
1.0 Final version release August 9, 2007 Final
A25L20P/A25L10P/A25L05P Series 2Mbit / 1Mbit / 512Kbit, Low Voltage, Serial Flash Memory With 85MHz SPI Bus Interface (August, 2007, Version 1.0) 1 AMIC Technology Corp.
FEATURES
2Mbit / 1Mbit / 512Kbit of Flash Memory Flexible Sector Architecture Bulk Erase (typical) - 25L20P (2M) in 6s - A25L10P (1M) in 4s - A25L05P (512K) in 3s Sector Erase (512 Kbit) in 1s (typical) Page Program (up to 256 Bytes) in 3ms (typical) 2.7 to 3.6V Single Supply Voltage SPI Bus Compatible Serial Interface 85MHz Clock Rate (maximum) Deep Power-down Mode 1µA (typical) Top or Bottom boot block configuration available Electronic Signatures - JEDEC Standard Two-Byte Signature A25L20P: (2012h, Bottom) or (2022h, top) A25L10P: (2011h, Bottom) or (2021h, top) A25L05P: (2010h, Bottom) or (2020h, top) - RES Instruction, One-Byte, Signature, for backward compatibility A25L20P (11h) A25L10P (10h) A25L05P (05h) Package options - 8-pin SOP (150mil or 209mil), 8-pin DIP (300mil) or 8-pin QFN - All Pb-free (Lead-free) products are RoHS compliant GENERAL DESCRIPTION The A25L20P/A25L10P/A25L05P are 2M/1M/512 bit Serial Flash Memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction. The memory is organized as 4/2/ 1 sectors, each containing 256 pages. Each page is 256 bytes wide. Thus, the whole memory can be viewed as consisting of 1024/512/256 pages, or 262,144 /131,072/65,536 bytes. The whole memory can be erased using the Bulk Erase instruction, or a sector at a time, using the Sector Erase instruction. Pin Configurations SO8 Connections DIP8 Connections QFN8 Connections A25L20P/ A25L10P/ A25L05P VCC C DO DIO S W HOLD VSS VCC C DO DIO S W HOLD VSS 1 8 2 7 3 6 4 5 VCC C DO DIO S W HOLD VSS 1 8 2 7 3 6 4 5 A25L20P/ A25L10P/ A25L05P A25L20P/ A25L10P/ A25L05P
A25L20P/A25L10P/A25L05P Series (August, 2007, Version 1.0) 2 AMIC Technology Corp. Block Diagram Control Logic High Voltage Generator I/O Shift Register Address register and Counter
256 Byte
256 Byte (Page Size)
C 000FFh00000h HOLD W S 3FFFh (2M), 1FFFh (1M), FFFh (512K) Pin Descriptions Pin No. Description C Serial Clock DIO Serial Data Input 1 DO Serial Data Output 2 S Chip Select W Write Protect HOLD Hold VCC Supply Voltage VSS Ground Notes: 1. The DIO is also used as an output pin when the Fast Read Dual Output instruction and the Fast Read Dual Input-Output instruction are executed. 2. The DO is also used as an input pin when the Fast Read Dual Input-Output instruction is executed. Logic Symbol A25L20P/ A25L10P/ A25L05P DODIO S W HOLD VSS VCC C
A25L20P/A25L10P/A25L05P Series (August, 2007, Version 1.0) 3 AMIC Technology Corp. SIGNAL DESCRIPTION Serial Data Output (DO). This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C). The DO pin is also used as an input pin when the Fast Read Dual Input-Output instruction is executed. Serial Data Input (DIO). This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be programmed. Values are latched on the rising edge of Serial Clock (C). The DIO pin is also used as an output pin when the Fast Read Dual Output instruction and the Fast Read Dual Input-Output instruction are executed. Serial Clock (C). This input signal provides the timing of the serial interface. Instructions, addresses, or data present at Serial Data Input (DIO) are latched on the rising edge of Serial Clock (C). Data on Serial Data Output (DO) changes after the falling edge of Serial Clock (C). Chip Select ( S ). When this input signal is High, the device is deselected and Serial Data Output (DO) is at high impedance. Unless an internal Program, Erase or Write Status Register cycle is in progress, the device will be in the Standby mode (this is not the Deep Power-down mode). Driving Chip Select (S) Low enables the device, placing it in the active power mode. After Power-up, a falling edge on Chip Select ( S) is required prior to the start of any instruction. Hold ( HOLD ). The Hold ( HOLD ) signal is used to pause any serial communications with the device without deselecting the device. During the Hold condition, the Serial Data Output (DO) is high impedance, and Serial Data Input (DIO) and Serial Clock (C) are Don’t Care. To start the Hold condition, the device must be selected, with Chip Select ( S) driven Low. Write Protect ( W ). The main purpose of this input signal is to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the BP1 and BP0 bits of the Status Register). SPI MODES These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: – CPOL=0, CPHA=0 – CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C). The difference between the two modes, as shown in Figure 2, is the clock polarity when the bus master is in Stand-by mode and not transferring data: – C remains at 0 for (CPOL=0, CPHA=0) – C remains at 1 for (CPOL=1, CPHA=1)
A25L20P/A25L10P/A25L05P Series (August, 2007, Version 1.0) 5 AMIC Technology Corp. OPERATING FEATURES Page Programming To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal Program cycle (of duration tPP). To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on the same page of memory. Sector Erase and Bulk Erase The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be applied, the bytes of memory need to have been erased to all 1s (FFh). This can be achieved, a sector at a time, using the Sector Erase (SE) instruction, or throughout the entire memory, using the Bulk Erase (BE) instruction. This starts an internal Erase cycle (of duration tSE or tBE). The Erase instruction must be preceded by a Write Enable (WREN) instruction. Polling During a Write, Program or Erase Cycle A further improvement in the time to Write Status Register (WRSR), Program (PP) or Eras e (SE or BE) can be achieved by not waiting for the worst case delay (tW, tPP, tSE, or tBE). The Write In Progress (WIP) bit is provided in the Status Register so that the application program can monitor its value, polling it to establish when the previous Write cycle, Program cycle or Erase cycle is complete. Active Power, Stand-by Power and Deep Power-Down Modes When Chip Select ( S) is Low, the device is enabled, and in the Active Power mode. When Chip Select ( S) is High, the device is disabled, but could remain in the Active Power mode until all internal cycles have completed (Program, Erase, Write Status Register). The device then goes in to the Stand-by Power mode. The device consumption drops to ICC1. The Deep Power-down mode is entered when the specific instruction (the Enter Deep Power-down Mode (DP) instruction) is executed. The device consumption drops further to I CC2. The device remains in this mode until another specific instruction (the Release from Deep Power-down Mode and Read Electronic Signature (RES) instruction) is executed. All other instructions are ignored while the device is in the Deep Power-down mode. This can be used as an extra software protection mechanism, when the device is not in active use, to protect the device from inadvertent Write, Program or Erase instructions. Status Register The Status Register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status Register, Program or Erase cycle. WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch, BP1, and BP0 bits. The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase instructions. SRWD bit. The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write Protect ( W ) signal. The Status Register Write Disable (SRWD) bit and Write Protect ( W ) signal allow the device to be put in the Hardware Protected mode. In this mode, the non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits. Protection Modes The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the A25L20P/A25L10P/A25L05P boasts the following data protection mechanisms: Power-On Reset and an internal timer (t PUW) can provide protection against inadvertant changes while the power supply is outside the operating specification. Program, Erase and Write Status Register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution. All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events: - Power-up - Write Disable (WRDI) instruction completion - Write Status Register (WRSR) instruction completion - Page Program (PP) instruction completion - Sector Erase (SE) instruction completion - Bulk Erase (BE) instruction completion The Block Protect (BP1, BP0) bits allow part of the memory to be configured as read-only. This is the Software Protected Mode (SPM). The Write Protect ( W ) signal allows the Block Protect (BP1, BP0) bits and Status Register Write Disable (SRWD) bit to be protected. This is the Hardware Protected Mode (HPM). In addition to the low power consumption feature, the Deep Power-down mode offers extra software protection from inadvertant Write, Program and Erase instructions, as all instructions are ignored except one particular instruction (the Release from Deep Power-down instruction).
(August, 2007, Version 1.0) 6 AMIC Technology Corp. Table 1. Protected Area Sizes Note: 1. The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP1, BP0) are 0.
- A25L20P: The sector 3 include sector 3-0, sect or 3-1, sector 3-2, sector 3-3 and sector 3-4.
A25L10P: The sector 1 include sector 1-0, sector 1-1, sector 1-2, sector 1-3 and sector 1-4. A25L05P: The sector 0 include sector 0-0, sector 0-1, sector 0-2, sector 0-3 and sector 0-4. Note: 1. The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP1, BP0) are 0.
- The sector 0 include sector 0-0, sector 0-1, sector 0-2, sector 0-3, and sector 0-4.
(August, 2007, Version 1.0) 7 AMIC Technology Corp. that is currently in progress. (C) being Low (as shown in Figure 3.). Serial Clock (C) next goes Low. This is shown in Figure 3. unchanged from the moment of entering the Hold condition. Figure 3. Hold Condition Activation
(August, 2007, Version 1.0) 8 AMIC Technology Corp. 1024 pages (256 bytes each). Erasable (bits are erased from 0 to 1) but not Page Erasable. Table 2. Memory Organization
(August, 2007, Version 1.0) 9 AMIC Technology Corp. 512 pages (256 bytes each). Erasable (bits are erased from 0 to 1) but not Page Erasable. Table 3. Memory Organization
(August, 2007, Version 1.0) 10 AMIC Technology Corp. 256 pages (256 bytes each). Erasable (bits are erased from 0 to 1) but not Page Erasable. Table 4. Memory Organization
(August, 2007, Version 1.0) 11 AMIC Technology Corp. the device, most significant bit first. being latched on the rising edges of Serial Clock (C). The instruction set is listed in Table 5. address bytes, or by data bytes, or by both or none. sequence is being shifted out. is an exact multiple of eight. Erase cycle continues unaffected. Table 5. Instruction Set
(August, 2007, Version 1.0) 13 AMIC Technology Corp. Table 6. Status Register Format reset to 0 no such cycle is in progress. Program or Erase instruction is accepted. are written with the Write Status Register (WRSR) instruction. only if, both Block Protect (BP1, BP0) bits are 0. operated in conjunction with the Write Protect ( W ) signal. (SRWD) bit is set to 1, and Write Protect ( W ) is driven Low). Figure 6. Read Status Register (RDSR) Instruction Sequence and Data-Out Sequence
(August, 2007, Version 1.0) 14 AMIC Technology Corp. the Write Enable Latch (WEL). and the data byte on Serial Data Input (DIO). read to check the value of the Write In Progress (WIP) bit. Write Status Register cycle, and is 0 when it is completed. Hardware Protected Mode (HPM) is entered. Figure 7. Write Status Register (WRSR) Instruction Sequence
(August, 2007, Version 1.0) 15 AMIC Technology Corp. Table 7. Protection Modes Note: 1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 1. ( W ) is driven High or Low. Register are rejected, and are not accepted for execution). protected against data modification. Status Register Write Disable (SRWD) bit. once entered is to pull Write Protect (W ) High. (BP1, BP0) bits of the Status Register, can be used.
(August, 2007, Version 1.0) 16 AMIC Technology Corp. The device is first selected by driving Chip Select ( S) Low. being latched-in during the rising edge of Serial Clock (C). sequence to be continued indefinitely. Figure 8. Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence Note: Address bits A23 to A18 are Don’t Care, for A25L20P. Address bits A23 to A17 are Don’t Care, for A25L10P.
(August, 2007, Version 1.0) 17 AMIC Technology Corp. The device is first selected by driving Chip Select ( S) Low. C, during the falling edge of Serial Clock (C). allowing the read sequence to be continued indefinitely. Figure 9. Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence and Data-Out Sequence Note: Address bits A23 to A18 are Don’t Care, for A25L20P. Address bits A23 to A17 are Don’t Care, for A25L10P.
(August, 2007, Version 1.0) 18 AMIC Technology Corp. the rate of standard SPI devices. Figure 10. FAST_READ_DUAL_OUTPUT Instruction Sequence and Data-Out Sequence Note: Address bits A23 to A18 are Don’t Care, for A25L20P. Address bits A23 to A17 are Don’t Care, for A25L10P.
(August, 2007, Version 1.0) 19 AMIC Technology Corp. Figure 11. FAST_READ_DUAL_INPUT-OUTPUT Instruction Sequence and Data-Out Sequence Note: Address bits A23 to A18 are Don’t Care, for A25L20P. Address bits A23 to A17 are Don’t Care, for A25L10P.
(August, 2007, Version 1.0) 20 AMIC Technology Corp. programmed in the memory (changing bits from 1 to 0). the entire duration of the sequence. other bytes of the same page. Program (PP) instruction is not executed. Enable Latch (WEL) bit is reset. and Table 1) is not executed. Figure 12. Page Program (PP) Instruction Sequence Note: Address bits A23 to A18 are Don’t Care, for A25L20P. Address bits A23 to A17 are Don’t Care, for A25L10P.
(August, 2007, Version 1.0) 21 AMIC Technology Corp. The Sector Erase (SE) instruction sets all bits to 1 (FFh). entire duration of the sequence. cycle is completed, the Write Enable Latch (WEL) bit is reset. instruction is ignored if one, or more, sectors are protected. Figure 13. Sector Erase (SE) Instruction Sequence Note: Address bits A23 to A18 are Don’t Care, for A25L20P. Address bits A23 to A17 are Don’t Care, for A25L10P.
(August, 2007, Version 1.0) 22 AMIC Technology Corp. entire duration of the sequence. the self-timed Bulk Erase cycle, and is 0 when it is completed. Write Enable Latch (WEL) bit is reset. is ignored if one, or more, sectors are protected. Figure 14. Bulk Erase (BE) Instruction Sequence Note: Address bits A23 to A18 are Don’t Care, for A25L20P. Address bits A23 to A17 are Don’t Care, for A25L10P.
(August, 2007, Version 1.0) 23 AMIC Technology Corp. Program and Erase instructions. Power-down and Read Electronic Signature (RES) instruction. to be output on Serial Data Output (DO). sequence is shown in Figure 15. having any effects on the cycle that is in progress. Figure 15. Deep Power-down (DP) Instruction Sequence
(August, 2007, Version 1.0) 24 AMIC Technology Corp. 20h(Top) or 10h(Bottom) for A25L05P). effect on the cycle that is in progress. The device is first selected by driving Chip Select ( S) Low. Then, the 8-bit instruction code for the instruction is shifted in. S) High at any time during data output. Table 8. Read Identification (READ_ID) Data-Out Sequence Figure 16. Read Identification (RDID) Data-Out Sequence
(August, 2007, Version 1.0) 25 AMIC Technology Corp. no effect on the cycle that is in progress. The instruction sequence is shown in Figure 17. Electronic Signature to be output repeatedly. Figure 17. Release from Deep Power-down and Read Electronic Signature (RES) Instruction Sequence and
3 Dummy Bytes
Note: The value of the 8-bit Electronic Signature, for the A25L20P is 11h, A25L10P is 10h, and A25L05P is 05h.
(August, 2007, Version 1.0) 26 AMIC Technology Corp. Figure 18. Release from Deep Power-down (RES) Instruction Sequence that it can receive, decode and execute instructions.
(August, 2007, Version 1.0) 27 AMIC Technology Corp. used to insure safe and proper Power-up and Power-down. during power up, a Power On Reset (POR) circuit is included. and the device does not respond to any instruction. These values are specified in Table 9. even if the tPUW delay is not yet fully elapsed. The Write Enable Latch (WEL) bit is reset. disabled and the device does not respond to any instruction. Figure 19. Power-up Timing
(August, 2007, Version 1.0) 28 AMIC Technology Corp. Table 9. Power-Up Timing Note: These parameters are characterized only. 00h (all Status Register bits are 0).
(August, 2007, Version 1.0) 29 AMIC Technology Corp. Transient Voltage (<20ns) on Any Pin to Ground Potential . .
- Compliant with JEDEC Std J-STD-020B (for small body,
conditions, and the DC and AC characteristics of the device. Measurement Conditions summarized in the relevant tables. Table 10. Operating Conditions Table 11. Data Retention and Endurance Table 12. Capacitance Note: Sampled only, not 100% tested, at TA=25°C and a frequency of 33 MHz.
(August, 2007, Version 1.0) 30 AMIC Technology Corp. Table 13. DC Characteristics Table 14. Instruction Times Table 15. AC Measurement Conditions Note: Output Hi-Z is defined as the point where data out is no longer driven.
(August, 2007, Version 1.0) 31 AMIC Technology Corp. Figure 20. AC Measurement I/O Waveform
(August, 2007, Version 1.0) 32 AMIC Technology Corp. Table 16. AC Characteristics
4 Write Protect Setup Time 20 ns
- Value guaranteed by characterization, not 100% tested in production.
- Expressed as a slew-rate.
- Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
A25L20P/A25L10P/A25L05P Series (August, 2007, Version 1.0) 35 AMIC Technology Corp. Part Numbering Scheme Package M = 209 mil SOP 8 O = 150 mil SOP 8 Q = QFN 8 Device Voltage L = 2.7-3.6V Device Version* Device Type A25 = AMIC Serial Flash 05 = 512 Kbit 20 = 2 Mbit 10 = 1 Mbit 40 = 4 Mbit 80 = 8 Mbit 16 = 16 Mbit Device Function P = Page Program & Sector Erase Device Density Temperature* Package Material Blank: normal F: PB free * Optional Boot Sector T = Top type U = Bottom type
A25L20P/A25L10P/A25L05P Series (August, 2007, Version 1.0) 36 AMIC Technology Corp.
Ordering Information
Part No. Speed (MHz) Active Read Current Typ. (mA) Program/Erase Current Typ. (mA) Standby Current Typ. (μA) Package A25L20PT-F A25L20PT-UF
8 Pin Pb-Free DIP (300 mil)
8 Pin Pb-Free SOP (150 mil)
8 Pb-Free Pin SOP (209mil)
8 Pin Pb-Free QFN
-U is for industrial operating temperature range: -40°C ~ +85°C
A25L20P/A25L10P/A25L05P Series (August, 2007, Version 1.0) 37 AMIC Technology Corp. Ordering Information (continued) Part No. Speed (MHz) Active Read Current Typ. (mA) Program/Erase Current Typ. (mA) Standby Current Typ. (μA) Package A25L10PT-F A25L10PT-UF -U is for industrial operating temperature range: -40°C ~ +85°C
A25L20P/A25L10P/A25L05P Series (August, 2007, Version 1.0) 38 AMIC Technology Corp. Ordering Information (continued) Part No. Speed (MHz) Active Read Current Typ. (mA) Program/Erase Current Typ. (mA) Standby Current Typ. (μA) Package A25L05PT-F A25L05PT-UF -U is for industrial operating temperature range: -40°C ~ +85°C
A25L20P/A25L10P/A25L05P Series (August, 2007, Version 1.0) 39 AMIC Technology Corp.
Package Information
P-DIP 8L Outline Dimensions unit: inches/mm Dimensions in inches Dimensions in mm Symbol Min Nom Max Min Nom Max EA 0.345 - 0.385 8.76 - 9.78 Notes: 1. Dimension D and E1 do not include mold flash or protrusions. 2. Dimension B1 does not include dambar protrusion. 3. Tolerance: ±0.010” (0.25mm) unless otherwise specified.
A25L20P/A25L10P/A25L05P Series (August, 2007, Version 1.0) 40 AMIC Technology Corp. SOP 8L (150mil) Outline Dimensions unit: mm HE D A E b L°° 8~0 e Symbol Dimensions in mm A 1.35~1.75 A1 0.10~0.25 b 0.33~0.51 D 4.7~5.0 E 3.80~4.00 e 1.27 BSC HE 5.80~6.20 L 0.40~1.27 Notes: 1. Maximum allowable mold flash is 0.15mm. 2. Complies with JEDEC publication 95 MS –012 AA. 3. All linear dimensions ar e in millimeters (max/min). 4. Coplanarity: Max. 0.1mm
A25L20P/A25L10P/A25L05P Series (August, 2007, Version 1.0) 41 AMIC Technology Corp. SOP 8L (209mil) Outline Dimensions unit: mm E e b D A L θ 0.25 GAGE PLANE SEATING PLANE C Dimensions in mm Symbol Min Nom Max A 1.75 1.95 2.16 A1 0.05 0.15 0.25 A2 1.70 1.80 1.91 b 0.35 0.42 0.48 C 0.19 0.20 0.25 D 5.13 5.23 5.33 E 7.70 7.90 8.10 E1 5.18 5.28 5.38 e 1.27 BSC L 0.50 0.65 0.80 θ 0° - 8° Notes: Maximum allowable mold flash is 0.15mm at the package ends and 0.25mm between leads
A25L20P/A25L10P/A25L05P Series (August, 2007, Version 1.0) 42 AMIC Technology Corp. QFN 8L (6 X 5 X 0.8mm) Outline Dimensions unit: mm/mil 0.25 C 0.25 C E D e b L A 0.10// C y C Seating Plane Pin1 ID Area 567 14 32 C0.30 Dimensions in mm Dimensions in mil Symbol Min Nom Max Min Nom Max A3 0.203 REF 8.0 REF e 1.270 BSC 50.0 BSC y 0 - 0.080 0 - 3.2 Note: 1. Controlling dimension: millimeters 2. Leadframe thickness is 0.203mm (8mil)