A25L016 AMICC | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 41
Technical content
16Mbit Low Voltage, Serial Flash Memory With 100MHz Uniform 4KB Sectors (April, 2008, Version 0.0) AMIC Technology Corp. Document Title 16Mbit, Low Voltage, Serial Flash Memory With 100MHz Uniform 4KB Sectors
Revision History
Rev. No. History Issue Date Remark
0.0 Initial issue April 2, 2008 Final
16Mbit Low Voltage, Serial Flash Memory With 100MHz Uniform 4KB Sectors (April, 2008, Version 0.0) 1 AMIC Technology Corp.
FEATURES
Family of Serial Flash Memories - A25L016: 16M-bit /2M-byte Flexible Sector Architecture with 4KB sectors - Sector Erase (4K-bytes) in 60ms (typical) - Block Erase (64K-bytes) in 0.5s (typical) Page Program (up to 256 Bytes) in 0.8ms (typical) 2.7 to 3.6V Single Supply Voltage Dual input / output instructions resulting in an equivalent clock frequency of 200MHz: - Dual Output Fast Read Instruction - Dual Input and Output Fast Read Instruction SPI Bus Compatible Serial Interface 100MHz Clock Rate (maximum) Deep Power-down Mode 5µA (Max) 16Mbit Flash memory - Uniform 4-Kbyte sectors - Uniform 64-Kbyte blocks Electronic Signatures - JEDEC Standard Two-Byte Signature A25L016: (3015h) - RES Instruction, One-Byte, Signature, for backward compatibility A25L016 (14h) Package options - 8-pin SOP (209mil), 16-pin SOP (300mil), 8-pin DIP (300mil) - All Pb-free (Lead-free) products are RoHS compliant GENERAL DESCRIPTION The A25L016 is 16M bit Serial Flash Memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction. The memory is organized as 32 blocks, each containing 16 sectors. Each sector is comp osed of 16 pages. Each page is 256 bytes wide. Thus, the whole memory can be viewed as consisting of 8,192 pages, or 2,097,152 bytes. The whole memory can be erased using the Chip Erase instruction, a block at a time, using Block Erase instruction, or a sector at a time, using the Sector Erase instruction. Pin Configurations SOP8 Connections SOP16 Connections DIP8 Connections VCC C DO DIO S W HOLD VSS 1 8 2 7 3 6 4 5 A25L016 A25L016 VCC C DO DIO S W HOLD VSS 1 8 2 7 3 6 4 5 VCC C DU DO S HOLD VSS 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 A25L016 DU DU DU DIO DU DU DU DU W Note: DU = Do not Use
(April, 2008, Version 0.0) 2 AMIC Technology Corp. Block Diagram Control Logic High Voltage Generator I/O Shift Register Address register and Counter
256 Byte
256 Byte (Page Size)
C 000FFh00000h HOLD W S 1FFFFF Pin Descriptions Pin No. Description C Serial Clock DIO Serial Data Input 1 DO Serial Data Output 2 S Chip Select W Write Protect HOLD Hold VCC Supply Voltage VSS Ground Notes: 1. The DIO is also used as an output pin when the Fast Read Dual Output instruct ion and the Fast Read Dual Input-Output instruction are executed. 2. The DO is also used as an input pin when the Fast Read Dual Input-Output instruction. Logic Symbol A25L016 DODIO S W HOLD VSS VCC C
(April, 2008, Version 0.0) 3 AMIC Technology Corp. SIGNAL DESCRIPTION Serial Data Output (DO). This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C). The DO pin is also used as an input pin when the Fast Read Dual Input-Output instruction and Dual Input Fast Program is executed. Serial Data Input (DIO). This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be programmed. Values are latched on the rising edge of Serial Clock (C). The DIO pin is also used as an output pin when the Fast Read Dual Output instruction and the Fast Read Dual Input-Output instruction are executed. Serial Clock (C). This input signal provides the timing of the serial interface. Instructions, addresses, or data present at Serial Data Input (DIO) are latched on the rising edge of Serial Clock (C). Data on Serial Data Output (DO) changes after the falling edge of Serial Clock (C). Chip Select ( S ). When this input signal is High, the device is deselected and Serial Data Output (DO) is at high impedance. Unless an internal Program, Erase or Write Status Register cycle is in progress, the device will be in the Standby mode (this is not the Deep Power-down mode). Driving Chip Select ( S) Low enables the device, placing it in the active power mode. After Power-up, a falling edge on Chip Select ( S) is required prior to the start of any instruction. Hold ( HOLD ). The Hold ( HOLD ) signal is used to pause any serial communications with the device without deselecting the device. During the Hold condition, the Serial Data Output (DO) is high impedance, and Serial Data Input (DIO) and Serial Clock (C) are Don’t Care. To start the Hold condition, the device must be selected, with Chip Select ( S) driven Low. Write Protect ( W ). The main purpose of this input signal is to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the BP2, BP1, and BP0 bits of the Status Register).
(April, 2008, Version 0.0) 5 AMIC Technology Corp. OPERATING FEATURES Page Programming To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal Program cycle (of duration tPP). To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on the same page of memory. Sector Erase, Block Erase, and Chip Erase The Page Program (PP) instruction and Dual Input Fast Program (DIFP) instruction allow bits to be reset from 1 to 0. Before this can be applied, the bytes of memory need to have been erased to all 1s (FFh). This can be achieved, a sector at a time, using the Sector Erase (SE) instruction, a block at a time, using the Block Erase (BE) instruction, or throughout the entire memory, using the Chip Erase (CE) instruction. This starts an internal Erase cycle (of duration tSE, tBE, or tCE). The Erase instruction must be preceded by a Write Enable (WREN) instruction. Polling During a Write, Program or Erase Cycle A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase (SE, BE, or CE) can be achieved by not waiting for the worst case delay (t W, tPP, tSE, tBE, t CE). The Write In Progress (WIP) bit is provided in the Status Register so that the application program can monitor its value, polling it to establish when the previous Write cycle, Program cycle or Erase cycle is complete. Active Power, Stand-by Power and Deep Power-Down Modes When Chip Select ( S) is Low, the device is enabled, and in the Active Power mode. When Chip Select ( S) is High, the device is disabled, but could remain in the Active Power mode until all internal cycles have completed (Program, Erase, Write Status Register). The device then goes in to the Stand-by Power mode. The device consumption drops to ICC1. The Deep Power-down mode is entered when the specific instruction (the Deep Power-down Mode (DP) instruction) is executed. The device consumption drops further to I CC2. The device remains in this mode until another specific instruction (the Release from Deep Power-down Mode and Read Electronic Signature (RES) instruction) is executed. All other instructions are ignored while the device is in the Deep Power-down mode. This can be used as an extra software protection mechanism, when the device is not in active use, to protect the device from inadvertent Write, Program or Erase instructions. Status Register The Status Register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status Register, Program or Erase cycle. WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. BP2, BP1, BP0 bits. The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase instructions. SRWD bit. The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write Protect ( W ) signal. The Status Register Write Disable (SRWD) bit and Write Protect ( W ) signal allow the device to be put in the Hardware Protected mode. In this mode, the non-volatile bits of the Status Register (SRWD, TB, BP2, BP1, BP0) become read-only bits. Protection Modes The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the A25L016 boasts the following data protection mechanisms: Power-On Reset and an internal timer (t PUW) can provide protection against inadvertent changes while the power supply is outside the operating specification. Program, Erase and Write Status Register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution. All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events: - Power-up - Write Disable (WRDI) instruction completion - Write Status Register (WRSR) instruction completion - Page Program (PP) instruction completion - Sector Erase (SE) instruction completion - Block Erase (BE) instruction completion - Chip Erase (CE) instruction completion The Block Protect (BP2, BP1, BP0) bits allow part of the memory to be configured as read-only. This is the Software Protected Mode (SPM). The Write Protect ( W ) signal allows the Block Protect (BP2, BP1, BP0) bits and Status Register Write Disable (SRWD) bit to be protected. This is the Hardware Protected Mode (HPM). In addition to the low power consumption feature, the Deep Power-down mode offers extra software protection from inadvertent Write, Program and Erase instructions, as all instructions are ignored except one particular instruction (the Release from Deep Power-down instruction).
(April, 2008, Version 0.0) 6 AMIC Technology Corp. Table 1. Protected Area Sizes
- The device is ready to accept a Chip Erase instructi on if, and only if, all Block Protect (BP2, BP1, BP0) are 0.
(April, 2008, Version 0.0) 7 AMIC Technology Corp. that is currently in progress. (C) being Low (as shown in Figure 3.). Serial Clock (C) next goes Low. This is shown in Figure 3. unchanged from the moment of entering the Hold condition. Figure 3. Hold Condition Activation
(April, 2008, Version 0.0) 8 AMIC Technology Corp. Erasable (bits are erased from 0 to 1) but not Page Erasable. Table 2. Memory Organization
240 F0000h F0FFFh
224 E0000h E0FFFh
208 D0000h D0FFFh
192 C0000h C0FFFh
176 B0000h B0FFFh
160 A0000h A0FFFh
(April, 2008, Version 0.0) 9 AMIC Technology Corp. Memory Organization (continued) Block Sector Address range 159 9F000h 9FFFFh ... ... ... 9 144 90000h 90FFFh 143 8F000h 8FFFFh ... ... ... 8 128 80000h 80FFFh 127 7F000h 7FFFFh ... ... ... 112 70000h 70FFFh 111 6F000h 6FFFFh ... ... ... 96 60000h 60FFFh 95 5F000h 5FFFFh ... ... ... 80 50000h 50FFFh 79 4F000h 4FFFFh ... ... ... 4 64 40000h 40FFFh Block Sector Address range 63 3F000h 3FFFFh ... ... ... 48 30000h 30FFFh 47 2F000h 2FFFFh ... ... ... 32 20000h 20FFFh 31 1F000h 1FFFFh ... ... ... 16 10000h 10FFFh 15 0F000h 0FFFFh ... ... ... 4 04000h 04FFFh 3 03000h 03FFFh 2 02000h 02FFFh 1 01000h 01FFFh 0 00000h 00FFFh
(April, 2008, Version 0.0) 10 AMIC Technology Corp. the device, most significant bit first. being latched on the rising edges of Serial Clock (C). The instruction set is listed in Table 3. address bytes, or by data bytes, or by both or none. the data-out sequence is being shifted out. (S) being driven Low is an exact multiple of eight. Erase cycle continues unaffected. Table 3. Instruction Set
(April, 2008, Version 0.0) 12 AMIC Technology Corp. Table 4. Status Register Format reset to 0 no such cycle is in progress. Program or Erase instruction is accepted. software protected against Program and Erase instructions. only if, all Block Protect (BP2, BP1, BP0) bits are 0. operated in conjunction with the Write Protect ( W ) signal. longer accepted for execution. Figure 6. Read Status Register (RDSR) Instruction Sequence and Data-Out Sequence
(April, 2008, Version 0.0) 13 AMIC Technology Corp. device sets the Write Enable Latch (WEL). code and the data byte on Serial Data Input (DIO). Write Enable Latch (WEL) is reset. Figure 7. Write Status Register (WRSR) Instruction Sequence
(April, 2008, Version 0.0) 14 AMIC Technology Corp. Table 5. Protection Modes Note: 1. As defined by the values in the Block Protect (TB, BP2, BP1, BP0) bits of the Status Register, as shown in Table 1. ( W ) is driven High or Low. Register are rejected, and are not accepted for execution). hardware protected against data modification. Status Register Write Disable (SRWD) bit. once entered is to pull Write Protect (W ) High. (BP2, BP1, BP0) bits of the Status Register, can be used.
(April, 2008, Version 0.0) 15 AMIC Technology Corp. The device is first selected by driving Chip Select ( S) Low. being latched-in during the rising edge of Serial Clock (C). sequence to be continued indefinitely. Figure 8. Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence Note:. Address bits A23 to A21 are Don’t Care, for A25L016.
(April, 2008, Version 0.0) 16 AMIC Technology Corp. The device is first selected by driving Chip Select ( S) Low. C, during the falling edge of Serial Clock (C). allowing the read sequence to be continued indefinitely. Figure 9. Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence and Data-Out Sequence Note:. Address bits A23 to A21 are Don’t Care, for A25L016.
(April, 2008, Version 0.0) 17 AMIC Technology Corp. Figure 10. FAST_READ_DUAL_OUTPUT Instruction Sequence and Data-Out Sequence Note:. Address bits A23 to A21 are Don’t Care, for A25L016.
(April, 2008, Version 0.0) 18 AMIC Technology Corp. rate of standard SPI devices. Figure 11. FAST_READ_DUAL_INPUT-OUTPUT Instruction Sequence and Data-Out Sequence Note:. Address bits A23 to A21 are Don’t Care, for A25L016.
(April, 2008, Version 0.0) 19 AMIC Technology Corp. programmed in the memory (changing bits from 1 to 0). the entire duration of the sequence. other bytes of the same page. Program (PP) instruction is not executed. Enable Latch (WEL) bit is reset. table 1 and table 2) is not executed. Figure 12. Page Program (PP) Instruction Sequence Note:. Address bits A23 to A21 are Don’t Care, for A25L016.
(April, 2008, Version 0.0) 20 AMIC Technology Corp. decoded, the device sets the Write Enable Latch (WEL). entire duration of the sequence. cycle is completed, the Write Enable Latch (WEL) bit is reset. table 1 and table 2) is not executed. Figure 13. Sector Erase (SE) Instruction Sequence Note:. Address bits A23 to A21 are Don’t Care, for A25L016.
(April, 2008, Version 0.0) 21 AMIC Technology Corp. (WREN) instruction must previously have been executed. the device sets the Write Enable Latch (WEL). entire duration of the sequence. completed, the Write Enable Latch (WEL) bit is reset. table 1and table 2) is not executed. Figure 14. Block Erase (BE) Instruction Sequence Note:. Address bits A23 to A21 are Don’t Care, for A25L016.
(April, 2008, Version 0.0) 22 AMIC Technology Corp. entire duration of the sequence. completed, the Write Enable Latch (WEL) bit is reset. instruction is ignored if one, or more, blocks are protected. Figure 15. Chip Erase (CE) Instruction Sequence Note:. Address bits A23 to A21 are Don’t Care, for A25L016.
(April, 2008, Version 0.0) 23 AMIC Technology Corp. Program and Erase instructions. Power-down and Read Electronic Signature (RES) instruction. to be output on Serial Data Output (DO). sequence is shown in Figure 16. having any effects on the cycle that is in progress. Figure 16. Deep Power-down (DP) Instruction Sequence
(April, 2008, Version 0.0) 24 AMIC Technology Corp. effect on the cycle that is in progress. The device is first selected by driving Chip Select ( S) Low. Then, the 8-bit instruction code for the instruction is shifted in. Select (S) High at any time during data output. Table 6. Read Identification (READ_ID) Data-Out Sequence Figure 17. Read Identification (RDID) Instruction Sequence and Data-Out Sequence
(April, 2008, Version 0.0) 25 AMIC Technology Corp. Data Input (DIO) during the rising edge of Serial Clock (C). Table 7. Read Electronic Manufacturer ID & Device ID (REMS) Data-Out Sequence Figure 18. Read Electronic Manufacturer ID & Device ID (REMS) Instruction Sequence and Data-Out Sequence
2 Dummy Bytes
(April, 2008, Version 0.0) 26 AMIC Technology Corp. no effect on the cycle that is in progress. The instruction sequence is shown in Figure 19. Electronic Signature to be output repeatedly. Figure 19. Release from Deep Power-down and Read Electronic Signature (RES) Instruction Sequence and
3 Dummy Bytes
Note: The value of the 8-bit Electronic Signature is 14h.
(April, 2008, Version 0.0) 27 AMIC Technology Corp. Figure 20. Release from Deep Power-down (RES) Instruction Sequence that it can receive, decode and execute instructions.
(April, 2008, Version 0.0) 28 AMIC Technology Corp. used to insure safe and proper Power-up and Power-down. during power up, a Power On Reset (POR) circuit is included. and the device does not respond to any instruction. These values are specified in Table 8. even if the tPUW delay is not yet fully elapsed. The Write Enable Latch (WEL) bit is reset. disabled and the device does not respond to any instruction. Figure 21. Power-up Timing
(April, 2008, Version 0.0) 29 AMIC Technology Corp. Table 8. Power-Up Timing Note: These parameters are characterized only. 00h (all Status Register bits are 0).
(April, 2008, Version 0.0) 30 AMIC Technology Corp. Transient Voltage (<20ns) on Any Pin to Ground Potential . .
- Compliant with JEDEC Std J-STD-020B (for small body,
conditions, and the DC and AC characteristics of the device. Measurement Conditions summarized in the relevant tables. Table 9. Operating Conditions Table 10. Data Retention and Endurance Table 11. Capacitance Note: Sampled only, not 100% tested, at TA=25°C and a frequency of 33 MHz.
(April, 2008, Version 0.0) 31 AMIC Technology Corp. Table 12. DC Characteristics Table 13. Instruction Times Table 14. AC Measurement Conditions Note: Output Hi-Z is defined as the point where data out is no longer driven.
(April, 2008, Version 0.0) 32 AMIC Technology Corp. Figure 22. AC Measurement I/O Waveform
(April, 2008, Version 0.0) 33 AMIC Technology Corp. Table 15. AC Characteristics
4 Write Protect Setup Time 20 ns
- Value guaranteed by characterization, not 100% tested in production.
- Expressed as a slew-rate.
- Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
(April, 2008, Version 0.0) 36 AMIC Technology Corp. Part Numbering Scheme A25 XX Package Type Blank = DIP8 M = 209 mil SOP 8 N = 300 mil SOP 16 Device Voltage L = 2.7-3.6V Device Version* Blank = The first version Device Type A25 = AMIC Serial Flash Device Density 512 = 512 Kbit (4KB uniform sectors) 010 = 1 Mbit (4KB uniform sectors) 020 = 2 Mbit (4KB uniform sectors) 040 = 4 Mbit (4KB uniform sectors) 080 = 8 Mbit (4KB uniform sectors) 016 = 16 Mbit (4KB uniform sectors) 032 = 32 Mbit (4KB uniform sectors) X Package Material Blank: normal F: PB free X * Optional XXXX Temperature* Blank = 0°C ~ +70°C U = -40°C ~ +85°C
(April, 2008, Version 0.0) 37 AMIC Technology Corp.
Ordering Information
Part No. Speed (MHz) Active Read Current Typ. (mA) Program/Erase Current Typ. (mA) Standby Current Typ. (μA) Package A25L016-F A25L016-UF
8 Pin Pb-Free DIP (300 mil)
8 Pb-Free Pin SOP (209mil)
16 Pb-Free Pin SOP (300mil)
Blank is for commercial operating temperature range: 0°C ~ +70°C -U is for industrial operating temperature range: -40°C ~ +85°C
(April, 2008, Version 0.0) 38 AMIC Technology Corp.
Package Information
P-DIP 8L Outline Dimensions unit: inches/mm Dimensions in inches Dimensions in mm Symbol Min Nom Max Min Nom Max EA 0.345 - 0.385 8.76 - 9.78 Notes: 1. Dimension D and E1 do not include mold flash or protrusions. 2. Dimension B1 does not include dambar protrusion. 3. Tolerance: ±0.010” (0.25mm) unless otherwise specified.
(April, 2008, Version 0.0) 39 AMIC Technology Corp. SOP 8L (209mil) Outline Dimensions unit: mm E e b D A L θ 0.25 GAGE PLANE SEATING PLANE C Dimensions in mm Symbol Min Nom Max A 1.75 1.95 2.16 A1 0.05 0.15 0.25 A2 1.70 1.80 1.91 b 0.35 0.42 0.48 C 0.19 0.20 0.25 D 5.13 5.23 5.33 E 7.70 7.90 8.10 E1 5.18 5.28 5.38 e 1.27 BSC L 0.50 0.65 0.80 θ 0° - 8° Notes: Maximum allowable mold flash is 0.15mm at the package ends and 0.25mm between leads
(April, 2008, Version 0.0) 40 AMIC Technology Corp. SOP 16L (300mil) Outline Dimensions unit: inches/mm E 16 9 A L θ SEATING PLANE H b D D0.10 C 0.02 (0.41) x 45 e C o Dimensions in inch Dimensions in mm Symbol Min Max Min Max A 0.093 0.104 2.36 2.65 A1 0.004 0.012 0.10 0.30 b 0.016 Typ. 0.41 Typ. C 0.008 Typ. 0.20 Typ. D 0.398 0.413 10.10 10.50 E 0.291 0.299 7.39 7.60 e 0.050 Typ. 1.27 Typ. H 0.394 0.419 10.01 10.64 L 0.016 0.050 0.40 1.27 θ 0° 8° 0° 8° Notes: 1. Dimensions “D” does not include mold flash, protrusions or gate burrs. 2. Dimensions “E” does not include interlead flash, or protrusions.