A25L16P_07 AMICC | Alldatasheet
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16 Mbit, Low Voltage, Serial Flash Memory
Preliminary With 85MHz SPI Bus Interface PRELIMINARY (April, 2007, Version 0.6) AMIC Technology Corp. Document Title
16 Mbit, Low Voltage, Serial Flash Memory With 85MHz SPI Bus Interface
Revision History
Rev. No. History Issue Date Remark
0.0 Initial issue March 10, 2006 Preliminary
0.1 Change part no. from A25L160P to A25L16P March 23, 2006
0.2 Change the frequency to 70 MHz March 27, 2006
Add the Fast Read Dual Input-Output Mode
0.3 Add QFN 8L (5 x 6mm) pa ckage type April 20, 2006
0.4 Top or bottom boot block configur ation available December 5, 2006
0.5 Change the frequency to 85 MHz February 6, 2007
Correct the A25LPT memory organization of Table 2-1 Reduce the options of protected area size to all sectors protected and all sect ors unprotected Modify the I CC1 and ICC3 of Table 10 Modify the t W and tBE of Table 11 0.6 Add transient voltage (<20ns) on any pin to ground potential spec. April 24, 2007
Preliminary With 85MHz SPI Bus Interface PRELIMINARY (April, 2007, Version 0.6) 1 AMIC Technology Corp.
FEATURES
16 Mbit of Flash Memory Flexible Sector Architecture (4/4/8/16/32)KB/64x31 KB Bulk Erase (16 Mbit) in 20s (typical) Sector Erase (512 Kbit) in 1s (typical) Page Program (up to 256 Bytes) in 1.5ms (typical) 2.7 to 3.6V Single Supply Voltage SPI Bus Compatible Serial Interface 85MHz Clock Rate (maximum) Fast Read Dual Operation Instruction (3Bh/BBh) Deep Power-down Mode 1µA (typical) Top or Bottom Boot Block Configuration Available Electronic Signature - JEDEC Standard Two-Byte Signature (2015h, Bottom; or 2025, Top) - RES Instruction, One-Byte, Signature (14h) Package Options - 8-pin SOP (209mil), 16-pin SOP, or 8-pin QFN - All Pb-free (Lead-free) products are ROHS complaint GENERAL DESCRIPTION The A25L16P is a 16 Mbit (2M x 8) Serial Flash Memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction. The memory is organized as 32 sectors, each containing 256 pages. Each page is 256 bytes wide. Thus, the whole memory can be viewed as consisting of 8192 pages, or 2,097,152 bytes. The whole memory can be erased using the Bulk Erase instruction, or a sector at a time, using the Sector Erase instruction. Pin Configurations SO8 Connections SO16 Connections QFN8 Connections VCC C DU DO S HOLD VSS 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 A25L16P VCC C DO DIO S W HOLD VSS 1 8 2 7 3 6 4 5 A25L16P DU DU DU DIO DU DU DU DU W Note: DU = Do not Use VCC C DIO DO S W HOLD VSS A25L16P
PRELIMINARY (April, 2007, Version 0.6) 2 AMIC Technology Corp. Block Diagram Control Logic High Voltage Generator I/O Shift Register Address register and Counter
256 Byte
256 Byte (Page Size)
C 000FFh00000h HOLD W S 1FFFFFh Pin Descriptions Pin No. Description C Serial Clock DIO Serial Data Input 1 DO Serial Data Output 2 S Chip Select W Write Protect HOLD Hold VCC Supply Voltage VSS Ground Notes: 1. The DIO is also used as an output pin when the Fast Read Dual Output instruction and the Fast Read Dual Input-Output instruction are executed. 2. The DO is also used as an input pin when the Fast Read Dual Input-Output instruction is executed. Logic Symbol A25L16P DODIO S W HOLD VSS VCC C
PRELIMINARY (April, 2007, Version 0.6) 3 AMIC Technology Corp. SIGNAL DESCRIPTION Serial Data Output (DO). This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C). The DO pin is also used as an input pin when the Fast Read Dual Input-Output Function is executed. Serial Data Input / Output (DIO). This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be programmed. Values are latched on the rising edge of Serial Clock (C). The DIO pin is also used as an output pin when the Fast Read Dual Output function and Fast Read Dual Input-Output function are executed. Serial Clock (C). This input signal provides the timing of the serial interface. Instructions , addresses, or data present at Serial Data Input (DIO) are latched on the rising edge of Serial Clock (C). Data on Seri al Data Output (DO) changes after the falling edge of Serial Clock (C). Chip Select ( S ). When this input signal is High, the device is deselected and Serial Data Output (DO) is at high impedance. Unless an internal Program, Erase or Write Status Register cycle is in progr ess, the device will be in the Standby mode (this is not the Deep Power-down mode). Driving Chip Select ( S) Low enables the device, placing it in the active power mode. After Power-up, a falling edge on Chip Select ( S) is required prior to the start of any instruction. Hold ( HOLD ). The Hold ( HOLD ) signal is used to pause any serial communications with the device without deselecting the device. During the Hold condition, the Serial Data Output (DO) is high impedance, and Serial Data Input (DIO) and Serial Clock (C) are Don’t Care. To start the Hold condition, the device must be selected, with Chip Select ( S) driven Low. Write Protect ( W ). The main purpose of this input signal is to freeze the size of the area of memory that is protected against program or erase instru ctions (as specified by the values in the BP2, BP1 and BP0 bits of the Status Register). SPI MODES These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: – CPOL=0, CPHA=0 – CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C). The difference between the two modes, as shown in Figure 2, is the clock polarity when the bus master is in Stand-by mode and not transferring data: – C remains at 0 for (CPOL=0, CPHA=0) – C remains at 1 for (CPOL=1, CPHA=1)
PRELIMINARY (April, 2007, Version 0.6) 5 AMIC Technology Corp. OPERATING FEATURES Page Programming To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and a Page Program (PP) sequence, which co nsists of four bytes plus data. This is followed by the internal Program cycle (of duration tPP). To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on the same page of memory. Sector Erase and Bulk Erase The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be applied, the bytes of memory need to have been erased to all 1s (FFh). This can be achieved, a sector at a time, using the Sector Erase (SE) instruction, or throughout t he entire memory, using the Bulk Erase (BE) instruction. This st arts an internal Erase cycle (of duration tSE or tBE). The Erase instruction must be preceded by a Write Enable (WREN) instruction. Polling During a Write, Program or Erase Cycle A further improvement in the ti me to Write Status Register (WRSR), Program (PP) or Erase (SE or BE) can be achieved by not waiting for the worst case delay (t W, t PP, t SE, or t BE). The Write In Progress (WIP) bit is provided in the Status Register so that the applicat ion program can monitor its value, polling it to establish when the previous Write cycle, Program cycle or Erase cycle is complete. Active Power, Stand-by Power and Deep Power-Down Modes When Chip Select ( S) is Low, the device is enabled, and in the Active Power mode. When Chip Select ( S) is High, the device is disabled, but could remain in the Active Power mode until all internal cycles have completed (Program, Erase, Write Status Register). The device then goes in to the Stand-by Power mode. The device consumption drops to ICC1. The Deep Power-down mode is entered when the specific instruction (the Enter Deep Power-down Mode (DP) instruction) is executed. The device consumption drops further to ICC2. The device remains in this mode until another specific instruction (the Re lease from Deep Power-down Mode and Read Electronic Signat ure (RES) instruction) is executed. All other instructions are igno red while the device is in the Deep Power-down mode. This can be used as an extra software protection mechanism, when the device is not in active use, to protect the dev ice from inadvertent Write, Program or Erase instructions. Status Register The Status Register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy with a Writ e Status Register, Program or Erase cycle. WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch, BP2, BP1, and BP0 bits. The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase instructions. SRWD bit. The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write Protect ( W ) signal. The Status Register Write Disable (SRWD) bit and Write Protect ( W ) signal allow the device to be put in the Hardware Protected mode. In this mode, the non-volatile bits of the Status Register (S RWD, BP2, BP1, BP0) become read-only bits. Protection Modes The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the A25L16P boasts the following data protection mechanisms: Power-On Reset and an internal timer (t PUW) can provide protection against inadvert ant changes while the power supply is outside the operating specification. Program, Erase and Write Stat us Register instructions are checked that they consist of a number of clock pulses that is a multiple of eigh t, before they are accepted for execution. All instructions that modi fy data must be preceded by a Write Enable (WREN) instruct ion to set the Write Enable Latch (WEL) bit. This bit is re turned to its reset state by the following events: - Power-up - Write Disable (WRDI) instruction completion - Write Status Register (WRSR) instruction completion - Page Program (PP) instruction completion - Sector Erase (SE) instruction completion - Bulk Erase (BE) instruction completion The Write Protect ( W ) signal allows the Block Protect (BP2, BP1, BP0) bits and Status Register Write Disable (SRWD) bit to be protected. This is the Hardware Protected Mode (HPM). In addition to the low powe r consumption feature, the Deep Power-down mode offers extra software protection from inadvertant Write, Pr ogram and Erase instructions, as all instructions are ignored except one particular instruction (the Release from Deep Power-down instruction).
PRELIMINARY (April, 2007, Version 0.6) 6 AMIC Technology Corp. Table 1. Protected Area Sizes Note: 1. The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are 0.
- The sector 31 include sector 31-0, sector 31-1, sector 31-2, sector 31-3 and sector 31-4.
Note: 1. The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are 0.
- The sector 0 include sector 0-0, sector 0-1, sector 0-2, sector 0-3 and sector 0-4.
that is currently in progress. (C) being Low (as shown in Figure 3.). unchanged from the moment of entering the Hold condition. Figure 3. Hold Condition Activation
PRELIMINARY (April, 2007, Version 0.6) 7 AMIC Technology Corp. MEMORY ORGANIZATION The memory is organized as: 2,097,152 bytes (8 bits each) 32 sectors (one (4/4/8/16/32) Kbytes & 64x31 Kbytes each) 8192 pages (256 bytes each). Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector or Bulk Erasable (bits are erased from 0 to 1) but not Page Erasable. Table 2-1. A25L16PT Memory Organization Sector Sector Size (Kbytes) Address Range 31-4 4 1FF 000h 1FFFFFh 31-4 4 1FE000h 1FEFFFh 31-2 8 1FC000h 1FDFFFh 31-1 16 1F8000h 1FBFFFh 31-0 32 1F0000h 1F7FFFh 30 64 1E0000h 1EFFFFh 29 64 1D0000h 1DFFFFh 28 64 1C0000h 1CFFFFh 27 64 1B0000h 1BFFFFh 26 64 1A0000h 1AFFFFh 25 64 190000h 19FFFFh 24 64 180000h 18FFFFh 23 64 170000h 17FFFFh 22 64 160000h 16FFFFh 21 64 150000h 15FFFFh 20 64 140000h 14FFFFh 19 64 130000h 13FFFFh 18 64 120000h 12FFFFh 17 64 110000h 11FFFFh 16 64 100000h 10FFFFh 15 64 F0000h FFFFFh 14 64 E0000h EFFFFh 13 64 D0000h DFFFFh 12 64 C0000h CFFFFh 11 64 B0000h BFFFFh 10 64 A0000h AFFFFh 9 64 90000h 9FFFFh 8 64 80000h 8FFFFh 7 64 70000h 7FFFFh 6 64 60000h 6FFFFh 5 64 50000h 5FFFFh 4 64 40000h 4FFFFh 3 64 30000h 3FFFFh 2 64 20000h 2FFFFh 1 64 10000h 1FFFFh 0 64 00000h 0FFFFh
PRELIMINARY (April, 2007, Version 0.6) 8 AMIC Technology Corp. Table 2-2. A25L16PU Memory Organization Sector Sector Size (Kbytes) Address Range 31 64 1F0000h 1FFFFFh 30 64 1E0000h 1EFFFFh 29 64 1D0000h 1DFFFFh 28 64 1C0000h 1CFFFFh 27 64 1B0000h 1BFFFFh 26 64 1A0000h 1AFFFFh 25 64 190000h 19FFFFh 24 64 180000h 18FFFFh 23 64 170000h 17FFFFh 22 64 160000h 16FFFFh 21 64 150000h 15FFFFh 20 64 140000h 14FFFFh 19 64 130000h 13FFFFh 18 64 120000h 12FFFFh 17 64 110000h 11FFFFh 16 64 100000h 10FFFFh 15 64 F0000h FFFFFh 14 64 E0000h EFFFFh 13 64 D0000h DFFFFh 12 64 C0000h CFFFFh 11 64 B0000h BFFFFh 10 64 A0000h AFFFFh 9 64 90000h 9FFFFh 8 64 80000h 8FFFFh 7 64 70000h 7FFFFh 6 64 60000h 6FFFFh 5 64 50000h 5FFFFh 4 64 40000h 4FFFFh 3 64 30000h 3FFFFh 2 64 20000h 2FFFFh 1 64 10000h 1FFFFh 0-4 32 08000h 0FFFFh 0-3 16 04000h 07FFFh 0-2 8 02000h 03FFFh 0-1 4 01000h 01FFFh 0-0 4 00000h 00FFFh
PRELIMINARY (April, 2007, Version 0.6) 9 AMIC Technology Corp. the device, most significant bit first. being latched on the rising edges of Serial Clock (C). The instruction set is listed in Table 3. address bytes, or by data bytes, or by both or none. after any bit of the data-out sequence is being shifted out. driven Low is an exact multiple of eight. Program cycle or Erase cycle continues unaffected. Table 3. Instruction Set
PRELIMINARY (April, 2007, Version 0.6) 11 AMIC Technology Corp. Table 4. Status Register Format reset to 0 no such cycle is in progress. Program or Erase instruction is accepted. software protected against Pr ogram and Erase instructions. Figure 6. Read Status Register (RDSR) Instruction Sequence and Data-Out Sequence
PRELIMINARY (April, 2007, Version 0.6) 12 AMIC Technology Corp. device sets the Write Enable Latch (WEL). and the data byte on Serial Data Input (DIO). Enable Latch (WEL) is reset. Figure 7. Write Status Register (WRSR) Instruction Sequence
PRELIMINARY (April, 2007, Version 0.6) 13 AMIC Technology Corp. Table 5. Protection Modes Note: 1. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in Table 1. ( W ) is driven High or Low. are also hardware protected against data modification. Status Register Write Disable (SRWD) bit. once entered is to pull Write Protect ( W ) High. (BP2, BP1, BP0) bits of the Status Register, can be used.
PRELIMINARY (April, 2007, Version 0.6) 14 AMIC Technology Corp. The device is first selected by driving Chip Select ( S) Low. being latched-in during the rising edge of Serial Clock (C). sequence to be continued indefinitely. Figure 8. Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence
PRELIMINARY (April, 2007, Version 0.6) 15 AMIC Technology Corp. The device is first selected by driving Chip Select ( S) Low. C, during the falling edge of Serial Clock (C). allowing the read sequence to be continued indefinitely. Figure 9. Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence and Data-Out Sequence Note: Address bits A23 to A21 are Don’t Care.
PRELIMINARY (April, 2007, Version 0.6) 16 AMIC Technology Corp. Figure 10. FAST_READ_DUAL_OUTPUT Instruction Sequence and Data-Out Sequence Note: Address bits A23 to A21 are Don’t Care.
PRELIMINARY (April, 2007, Version 0.6) 17 AMIC Technology Corp. rate of standard SPI devices. Figure 11. FAST_READ_DUAL_INPUT-OUTPUT Instruction Sequence and Data-Out Sequence Note: Address bits A23 to A21 are Don’t Care.
PRELIMINARY (April, 2007, Version 0.6) 18 AMIC Technology Corp. programmed in the memory (changing bits from 1 to 0). device sets the Write Enable Latch (WEL). the entire duration of the sequence. other bytes of the same page. Program (PP) instruction is not executed. self-timed Page Program cycle, and is 0 when it is completed. Write Enable Latch (WEL) bit is reset. Table 2 and Table 1) is not executed. Figure 12. Page Program (PP) Instruction Sequence Note: Address bits A23 to A21 are Don’t Care.
PRELIMINARY (April, 2007, Version 0.6) 19 AMIC Technology Corp. The Sector Erase (SE) instructi on sets all bits to 1 (FFh). device sets the Write Enable Latch (WEL). entire duration of the sequence. cycle is completed, the Write Enable Latch (WEL) bit is reset. Figure 13. Sector Erase (SE) Instruction Sequence Notes: Address bits A23 to A21 are Don’t Care.
PRELIMINARY (April, 2007, Version 0.6) 20 AMIC Technology Corp. The Bulk Erase (BE) instruction sets all bits to 1 (FFh). device sets the Write Enable Latch (WEL). entire duration of the sequence. completed, the Write Enable Latch (WEL) bit is reset. Figure 14. Bulk Erase (BE) Instruction Sequence Notes: Address bits A23 to A21 are Don’t Care.
PRELIMINARY (April, 2007, Version 0.6) 21 AMIC Technology Corp. Program and Erase instructions. as specified in DC Characteristics Table.). ture of the device to be output on Serial Data Output (DO). sequence is shown in Figure 15. having any effects on the cycle that is in progress. Figure 15. Deep Power-down (DP) Instruction Sequence
PRELIMINARY (April, 2007, Version 0.6) 22 AMIC Technology Corp. effect on the cycle that is in progress. The device is first selected by driving Chip Select ( S) Low. Then, the 8-bit instruction code for the instruction is shifted in. Select (S) High at any time during data output. decode and execute instructions. Figure 16. Read Identification (RDID) Data-Out Sequence
PRELIMINARY (April, 2007, Version 0.6) 23 AMIC Technology Corp. no effect on the cycle that is in progress. The instruction sequence is shown in Figure 17. Electronic Signature to be output repeatedly. decode and execute instructions. Figure 17. Release from Deep Power-down and Read Electronic Signature (RES) Instruction Sequence and
3 Dummy Bytes
Note: The value of the 8-bit Electronic Signature, for the A25L16P, is 14h.
PRELIMINARY (April, 2007, Version 0.6) 24 AMIC Technology Corp. Figure 18. Release from Deep Power-down (RES) Instruction Sequence that it can receive, decode and execute instructions.
PRELIMINARY (April, 2007, Version 0.6) 25 AMIC Technology Corp. used to insure safe and proper Power-up and Power-down. during power up, a Power On Reset (POR) circuit is included. disabled, and the device does not respond to any instruction. is not guaranteed if, by this time, V CC is still below V CC(min). These values are specified in Table 6. even if the tPUW delay is not yet fully elapsed. The Write Enable Latch (WEL) bit is reset. disabled and the device does not respond to any instruction. Figure 19. Power-up Timing
PRELIMINARY (April, 2007, Version 0.6) 26 AMIC Technology Corp. Table 6. Power-Up Timing Note: These parameters are characterized only. contains 00h (all Status Register bits are 0).
PRELIMINARY (April, 2007, Version 0.6) 27 AMIC Technology Corp. Transient Voltage (<20ns) on Any Pin to Ground Potential . . . .
- Compliant with JEDEC Std J-STD-020B (for small body,
in the Operating sectio ns of this specification is not implied. conditions, and the DC and AC c haracteristics of the device. Measurement Conditions summari zed in the relevant tables. Table 7. Operating Conditions Table 8. Data Retention and Endurance Table 9. Capacitance Note: Sampled only, not 100% tested, at TA=25°C and a frequency of 33 MHz.
PRELIMINARY (April, 2007, Version 0.6) 28 AMIC Technology Corp. Table 10. DC Characteristics Table 11. Instruction Times Table 12. AC Measurement Conditions Note: Output Hi-Z is defined as the point where data out is no longer driven.
PRELIMINARY (April, 2007, Version 0.6) 29 AMIC Technology Corp. Figure 20. AC Measurement I/O Waveform
PRELIMINARY (April, 2007, Version 0.6) 30 AMIC Technology Corp. Table 13. AC Characteristics
4 Write Protect Setup Time 20 ns
- Value guaranteed by characterization, not 100% tested in production.
- Expressed as a slew-rate.
- Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
PRELIMINARY (April, 2007, Version 0.6) 33 AMIC Technology Corp. Part Numbering Scheme A25 XX X XX X Package M = SOP8 N = SOP16 Q = QFN8 Device Voltage L = 2.7-3.6V Device Version* Device Type A25 = AMIC Serial Flash 05 = 512 Kbit 40 = 4 Mbit 80 = 8 Mbit 16 = 16 Mbit Device Function P = Page Program & Sector Erase Device Density Temperature* X Package Material Blank: normal F: PB free X * Optional
PRELIMINARY (April, 2007, Version 0.6) 34 AMIC Technology Corp.
Ordering Information
Part No. Speed (MHz) Active Read Current Typ. (mA) Program/Erase Current Typ. (mA) Standby Current Typ. (μA) Package A25L16PTM-F A25L16PTM-UF
8 Pb-Free Pin SOP (209mil)
16 Pin Pb-Free SOP
8 Pin Pb-Free QFP
-U is for industrial operating temperature range: -40°C ~ +85°C
PRELIMINARY (April, 2007, Version 0.6) 35 AMIC Technology Corp.
Package Information
SOP 8L (209mil) Outline Dimensions unit: mm E e b D A L θ 0.25 GAGE PLANE SEATING PLANE C Dimensions in mm Symbol Min Nom Max A 1.75 1.95 2.16 A1 0.05 0.15 0.25 A2 1.70 1.80 1.91 b 0.35 0.42 0.48 C 0.19 0.20 0.25 D 5.13 5.23 5.33 E 7.70 7.90 8.10 E1 5.18 5.28 5.38 e 1.27 BSC L 0.50 0.65 0.80 θ 0° - 8° Notes: Maximum allowable mold flash is 0.15mm at the package ends and 0.25mm between leads
PRELIMINARY (April, 2007, Version 0.6) 36 AMIC Technology Corp. SOP 16L (300mil) Outline Dimensions unit: inch E 16 9 A L θ SEATING PLANE H 0.050 typ.0.016 typ. D D0.004max. 0.008 typ. 0.02 x 45 Dimensions in inch Symbol Min Max A 0.093 0.104 A1 0.004 0.012 D 0.398 0.413 E 0.291 0.299 H 0.394 0.419 L 0.016 0.050 θ 0° 8° Notes: 1. Dimensions “D” does not include mold flash, protrusions or gate burrs. 2. Dimensions “E” does not include interlead flash, or protrusions.
PRELIMINARY (April, 2007, Version 0.6) 37 AMIC Technology Corp. QFN 8L (6 X 5 X 0.8mm) Outline Dimensions unit: mm/mil 0.25 C 0.25 C E D e b L A 0.10// C y C Seating Plane Pin1 ID Area 567 14 32 C0.30 Dimensions in mm Dimensions in mil Symbol Min Nom Max Min Nom Max A3 0.203 REF 8.0 REF e 1.270 BSC 50.0 BSC y 0 - 0.080 0 - 3.2 Note: 1. Controlling dimension: millimeters 2. Leadframe thickness is 0.203mm (8mil)