82C55

MSM82C55A-2RS OKI | Alldatasheet

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¡ Semiconductor MSM82C55A-2RS/GS/VJS GENERAL DESCRIPTION The MSM82C55A-2 is a programmable universal I/O interface device which operates as high speed and on low power consumption due to 3 m silicon gate CMOS technology. It is the best fit as an I/O port in a system which employs the 8-bit parallel processing MSM80C85AH CPU. This device has 24-bit I/O pins equivalent to three 8-bit I/O ports and all inputs/outputs are TTL interface compatible.

FEATURES

• High speed and low power consumption due to 3 m silicon gate CMOS technology
• 3 V to 6 V single power supply
• Full static operation
• Programmable 24-bit I/O ports
• Bidirectional bus operation (Port A)
• Bit set/reset function (Port C)
• TTL compatible
• Compatible with 8255A-5
• 40-pin Plastic DIP (DIP40-P-600-2.54): (Product name: MSM82C55A-2RS)
• 44-pin Plastic QFJ (QFJ44-P-S650-1.27): (Product name: MSM82C55A-2VJS)
• 44-pin Plastic QFP (QFP44-P-910-0.80-2K): (Product name: MSM82C55A-2GS-2K) ¡ Semiconductor MSM82C55A-2RS/GS/VJS CMOS PROGRAMMABLE PERIPHERAL INTERFACE E2O0020-27-X3 This version: Jan. 1998 Previous version: Aug. 1996

¡ Semiconductor MSM82C55A-2RS/GS/VJS CIRCUIT CONFIGURATION Group B Port C (Low Order

4 Bits)

(High Order (8) Group B Port B (8) Group A Control Group B Control Data Bus Buffer Read/ Write Control Logic VCC GND D0 - D7 RD WR RESET CS PA0 - PA7 PC4 - PC7 PC0 - PC3 PB0 - PB7 Internal Bus Line

¡ Semiconductor MSM82C55A-2RS/GS/VJS PIN CONFIGURATION (TOP VIEW) RESET D2. NC D CS GND PC7 NC PC6 PC2 PC3 PB0 PB1 PB2 NC PB3 RD PA0 PA1 PA2 PA3 NC PA VCC PC5 PC4 PC0 PC1 PB4 PB5 PB6 PB7 PA5 PA6 PA7 WR 44 pin Plastic QFJ 44 pin Plastic QFP 16 PA PA2 PA1 PA0 RD CS GND PC7 PC6 PC5 PC4 PC0 PC1 PC2 17PC PB0 PB1 PB2 PA4 PA5 PA6 PA7 WR RESET PB7 40 pin Plastic DIP PB6 PB5 PB4 PB3 VCC RESET D2. CS GND PC7 PC6 PC5 NC PC3 PB0 PB1 PB2 VCC PB3 RD PA0 PA1 PA2 PA3 VCC PA4 VCC PB7 PC4 PC0 PC1 PC2 PB4 PB5 PB6 NC PA5 PA6 PA7 WR

¡ Semiconductor MSM82C55A-2RS/GS/VJS ABSOLUTE MAXIMUM RATINGS –55 to +150 MSM82C55A-2RS Supply Voltage VCC –0.5 to +7 V Input Voltage VIN –0.5 to VCC +0.5 V Output Voltage VOUT –0.5 to VCC +0.5 V Storage Temperature TSTG °C Power Dissipation PD 0.7 W Parameter UnitSymbol Ta = 25°C Conditions Rating MSM82C55A-2GS MSM82C55A-2vJS 1.01.0 Ta = 25°C with respect to GND OPERATING RANGE Supply Voltage VCC V Top Range 3 to 6 –40 to 85 Parameter Unit Symbol °COperating Temperature RECOMMENDED OPERATING RANGE DC CHARACTERISTICS Typ. Supply Voltage VCC 5V Top +25 "L" Input Voltage V IL — "H" Input Voltage VIH — Min. 4.5 –40 –0.3 2.2 Max. 5.5 +85 +0.8 VCC + 0.3 Parameter UnitSymbol V V Operating Temperature Typ. Max. "L" Output Voltage VOL 0.4 V "H" Output Voltage VOH Parameter UnitSymbol Min. 4.2 3.7 IOL = 2.5 mA IOH = –40 mA IOH = –2.5 mA Conditions VCC = 4.5 V to 5.5 V Ta = –40°C to +85°C (CL = 0 pF) Input Leak Current ILI 1 mA Output Leak Current ILO 10 mA –10 0 £ VIN £ VCC 0 £ VOUT £ VCC CS ‡ VCC –0.2 V VIH ‡ VCC –0.2 V VIL £ 0.2 V Supply Current (Standby) I CCS mA 8m A I/O Wire Cycle 82C55A-2 ...8 MHzCPU Timing ICC Average Supply Current (Active) 0.1 MSM82C55A-2

¡ Semiconductor MSM82C55A-2RS/GS/VJS AC CHARACTERISTICS Min. Max. Setup Time of Address to the Falling Edge of RD tAR 20 —n s Hold Time of Address to the Rising Edge of RD tRA 0 —n s Parameter UnitSymbol Remarks Setup Time of Address before the Falling Edge of WR tAW 0 —n s Load 150 pF (VCC = 4.5 V to 5.5 V, Ta = –40 to +85°C) MSM82C55A-2 Delay Time from the Falling Edge of RD to the Output of Defined Data tRD — 120 ns Delay Time from the Rising Edge of RD to the Floating of Data Bus tDF 10 75 ns Time from the Rising Edge of RD or WR to the Next Falling Edge of RD or WR tRV 200 —n s RD Pulse Width tRR 100 —n s Hold Time of Address after the Rising Edge of WR tWA 20 —n s WR Pulse Width tWW 150 —n s Setup Time of Bus Data before the Rising Edge of WR tDW 50 —n s Hold Time of Bus Data after the Rising Edge of WR tWD 30 —n s Delay Time from the rising Edge of WR to the Output of Defined Data tWB — 200 ns Setup Time of Port Data before the Falling Edge of RD tIR 20 —n s Hold Time of Port Data after the Rising Edge of RD tHR 10 —n s ACK Pulse Width tAK 100 —n s STB Pulse Width tST 100 —n s Setup Time of Port Data before the rising Edge of STB tPS 20 —n s Hold Time of Port Bus Data after the rising Edge of STB tPH 50 —n s Delay Time from the Falling Edge of ACK to the Output of Defined Data tAD — 150 ns Delay Time from the Rising Edge of ACK to the Floating of Port (Port A in Mode 2) tKD 20 250 ns Delay Time from the Rising Edge of WR to the Falling Edge of OBF tWOB — 150 ns Delay Time from the Falling Edge of ACK to the Rising Edge of OBF tAOB — 150 ns Delay Time from the Falling Edge of STB to the Rising Edge of IBF tSIB — 150 ns Delay Time from the Rising Edge of RD to the Falling Edge of IBF tRIB — 150 ns Delay Time from the the Falling Edge of RD to the Falling Edge of INTR tRIT — 200 ns Delay Time from the Rising Edge of STB to the Rising Edge of INTR tSIT — 150 ns Delay Time from the Rising Edge of ACK to the Rising Edge of INTR tAIT — 150 ns Delay Time from the Falling Edge of WR to the Falling Edge of INTR tWIT — 250 ns Note: Timing measured at V L = 0.8 V and VH = 2.2 V for both inputs and outputs.

¡ Semiconductor MSM82C55A-2RS/GS/VJS TIMING DIAGRAM Basic Input Operation (Mode 0) Basic Output Operation (Mode 0) WR CS, A1, A0 tWW Port Output tDW tWB tAW tWA D7 - D0 tWD RD CS, A1, A0 tRR D7 - D0 tHRtIR tAR tRA tRD tDF Port Input Strobe Input Operation (Mode 1) STB INTR tST RD Port Input tSIB tSIT tRIT tPH tRIB tPS IBF

¡ Semiconductor MSM82C55A-2RS/GS/VJS Strobe Output Operation (Mode 1) WR INTR Port Output tWIT OBF tWOB tWB tAK tAIT tAOB ACK Bidirectional Bus Operation (Mode 2) tWOB tST tSIB tPS tAD tKD tPH tRIB tAOB tAK WR INTR Port A OBF ACK RD IBF STB

¡ Semiconductor MSM82C55A-2RS/GS/VJS OUTPUT CHARACTERISTICS (REFERENCE VALUE) 1 Output "H" Voltage (V OH) vs. Output Current (IOH) Output Current IOH (mA) Output "H" Voltage VOH (V) VCC = 5.0 V Ta = –40 to + 85°C 012345 Output Current IOL (mA) Output "L" Voltage VOL (V) VCC = 5.0 V Ta = –40 to +85°C 2 Output "L" Voltage (V OL) vs. Output Current (IOL) Note: The direction of flowing into the device is taken as positive for the output current.

¡ Semiconductor MSM82C55A-2RS/GS/VJS PIN DESCRIPTION D7 - D0 Item Bidirectional Data Bus Input and Output Pin No. Input/Output Function CS Chip Select Input Input RD Read Input Input A0, A1 Port Select Input (Address) Input PA7 - PA0 Port A Input and Output PC7 - PC0 Port C Input and Output These are three-state 8-bit bidirectional buses used to write and read data upon receipt of the WR and RD signals from CPU and also used when control words and bit set/reset data are transferred from CPU to MSM82C55A-2. RESET Reset Input Input This signal is used to reset the control register and all internal registers when it is in high level. At this time, ports are all made into the input mode (high impedance status). all port latches are cleared to 0. and all ports groups are set to mode 0. When the CS is in low level, data transmission is enabled with CPU. When it is in high level, the data bus is made into the high impedance status where no write nor read operation is performed. Internal registers hold their previous status, however. When RD is in low level, data is transferred from MSM82C55A-2 to CPU. By combination of A 0 and A1, either one is selected from among port A, port B, port C, and control register. These pins are usually connected to low order 2 bits of the address bus. These are universal 8-bit I/O ports. The direction of inputs/ outputs can be determined by writing a control word. Especially, port A can be used as a bidirectional port when it is set to mode 2. These are universal 8-bit I/O ports. The direction of inputs/outputs can be determined by writing a control word as 2 ports with 4 bits each. When port A or port B is used in mode 1 or mode 2 (port A only), they become control pins. Especially, when port C is used as an output port, each bit can set/reset independently. GND – – GND WR Write Input Input When WR is in low level, data or control words are transferred from CPU to MSM82C55A-2. PB7 - PB0 Port B Input and Output These are universal 8-bit I/O ports. The direction of inputs/outputs ports can be determined by writing a control word. VCC –– +5V power supply.

¡ Semiconductor MSM82C55A-2RS/GS/VJS BASIC FUNCTIONAL DESCRIPTION Group A and Group B When setting a mode to a port having 24 bits, set it by dividing it into two groups of 12 bits each. Group A: Port A (8 bits) and high order 4 bits of port C (PC 7~PC4) Group B: Port B (8 bits) and low order 4 bits of port C (PC 3~PC0) Mode 0, 1, 2 There are 3 types of modes to be set by grouping as follows: Mode 0: Basic input operation/output operation (Available for both groups A and B) Mode 1: Strobe input operation/output operation (Available for both groups A and B) Mode 2: Bidirectional bus operation (Available for group A only) When used in mode 1 or mode 2, however, port C has bits to be defined as ports for control signal for operation ports (port A for group A and port B for group B) of their respective groups. Port A, B, C The internal structure of 3 ports is as follows: Port A: One 8-bit data output latch/buffer and one 8-bit data input latch Port B: One 8-bit data input/output latch/buffer and one 8-bit data input buffer Port C: One 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input) Single bit set/reset function for port C When port C is defined as an output port, it is possible to set (to turn to high level) or reset (to turn to low level) any one of 8 bits individually without affecting other bits.

¡ Semiconductor MSM82C55A-2RS/GS/VJS OPERATIONAL DESCRIPTION Control Logic Operations by addresses and control signals, e.g., read and write, etc. are as shown in the table below: Setting of Control Word The control register is composed of 7-bit latch circuit and 1-bit flag as shown below. Definition of input/ output of low order 4 bits of port C. 0 = Output 1 = Input Definition of input/ output of 8 bits of port B. 0 = Output 1 = Input Mode definition of group B. 0 = Mode 0 1 = Mode 1 Definition of input/ output of high order 4 bits of port C. 0 = Output 1 = Input Definition of input/ output of 8 bits of port A. 0 = Output 1 = Input Mode definition of group A. D1D2D3D4D5D6D7 D6 D5 Mode 0 0 Mode 0 0 1 Mode 1 1 ·/CR Mode 2 Control word Identification flag When set to 0, it becomes the control word for bit set/ reset. Group A Control Bits Group B Control Bits Be sure to set 1 for the control word to define a mode and input/output. CS Input 0 0 Port A fi Data Bus Control 1 0 Others 10 WR Operaiton OperationA1 Output RD 00 11 0 10 01 0 00 10 1 10 00 1

• /CR 1·/CR ·/CR ·/CR Port B fi Data Bus Port C fi Data Bus Data Bus fi Port A Data Bus fi Port B Data Bus fi Port C Data Bus fi Control Register Illegal Condition Data bus is in the high impedance status.

¡ Semiconductor MSM82C55A-2RS/GS/VJS Precaution for Mode Selection The output registers for ports A and C are cleared to f each time data is written in the command register and the mode is changed, but the port B state is undefined. Bit Set/Reset Function When port C is defined as output port, it is possible to set (set output to 1) or reset (set output to 0) any one of 8 bits without affecting other bits as shown below. Definition of set/reset for a desired bit. 0 = Reset 1 = Set D1D2D3D4D5D6D7 Control word Identification flag When set to 1, it becomes the control word to define a mode and input/output. Definition of bit wanted to be set or reset. Dont's Care D3 D2Port C 0 0PC0 0 0PC1 0 1PC2 0 1PC3 1 0PC4 1 0PC5 1 1PC6 1 1PC7 Be sure to set to 0 for bit set/reset Interrupt Control Function When the MSM82C55A-2 is used in mode 1 or mode 2, the interrupt signal for the CPU is provided. The interrupt request signal is output from port C. When the internal flip-flop INTE is set beforehand at this time, the desired interrupt request signal is output. When it is reset beforehand, however, the interrupt request signal is not output. The set/reset of the internal flip-flop is made by the bit set/reset operation for port C virtually. Bit set fi INTE is set fi Interrupt allowed Bit reset fi INTE is reset fi Interrupt inhibited Operational Description by Mode 1. Mode 0 (Basic input/output operation) Mode 0 makes the MSM82C55A-2 operate as a basic input port or output port. No control signals such as interrupt request, etc. are required in this mode. All 24 bits can be used as two-8-bit ports and two 4-bit ports. Sixteen combinations are then possible for inputs/ outputs. The inputs are not latched, but the outputs are.

¡ Semiconductor MSM82C55A-2RS/GS/VJS Type Output Output Port A Output Output Output Output Output Output Input Input Input Input Input Input Input Input Output Output High Order 4 Bits of Port C Output Output Input Input Input Input Output Output Output Output Input Input Input Input Output Output Port B Input Input Output Output Input Input Output Output Input Input Output Output Input Input Input Output Control Word Group A Group B Low Order 4 Bits of Port C Output Input Input Output Ouput Input Input Output Output Input Input Output Output Input Notes: When used in mode 0 for both groups A and B 2. Mode 1 (Strobe input/output operation) In mode 1, the strobe, interrupt and other control signals are used when input/output operations are made from a specified port. This mode is available for both groups A and B. In group A at this time, port A is used as the data line and port C as the control signal. Following is a description of the input operation in mode 1. STB (Strobe input) When this signal is low level, the data output from terminal to port is fetched into the internal latch of the port. This can be made independent from the CPU, and the data is not output to the data bus until the RD signal arrives from the CPU. IBF (Input buffer full flag output) This is the response signal for the STB. This signal when turned to high level indicates that data is fetched into the input latch. This signal turns to high level at the falling edge of STB and to low level at the rising edge of RD. INTR (Interrupt request output) This is the interrupt request signal for the CPU of the data fetched into the input latch. It is indicated by high level only when the internal INTE flip-flop is set. This signal turns to high level at the rising edge of the STB (IBF = 1 at this time) and low level at the falling edge of the RD when the INTE is set. INTE A of group A is set when the bit for PC4 is set, while INTE B of group B is set when the bit for PC2 is set. Following is a description of the output operation of mode 1.

¡ Semiconductor MSM82C55A-2RS/GS/VJS OBF (Output buffer full flag output) This signal when turned to low level indicates that data is written to the specified port upon receipt of the WR signal from the CPU. This signal turns to low level at the rising edge of the WR and high level at the falling edge of the ACK. ACK (Acknowledge input) This signal when turned to low level indicates that the terminal has received data. INTR (Interrupt request output) This is the signal used to interrupt the CPU when a terminal receives data from the CPU via the MSM82C55A-5. It indicates the occurrence of the interrupt in high level only when the internal INTE flip-flop is set. This signal turns to high level at the rising edge of the ACK (OBF = 1 at this time) and low level at the falling edge of WR when the INTE B is set. INTE A of group A is set when the bit for PC6 is set, while INTE B of group B is set when the bit for PC2 is set. Mode 1 Input (Group A) PA7 PA0 - INTEA PC4 PC5 STBA IBFA PC3 INTRA RD (Group B) PB7 PB0 - INTEB PC2 PC1 STBB IBFB PC0 INTRB RD Note: Although belonging to group B, PC3 operates as the control signal of group A functionally. Mode 1 Output (Group A) PA7 PA0 - INTEA PC7 PC6 OBFA ACKA PC3 INTRA WR (Group B) PB7 PB0 - INTEB PC1 PC2 OBFB ACKB PC0 INTRB WR

¡ Semiconductor MSM82C55A-2RS/GS/VJS Port C Function Allocation in Mode 1 PC0 PC2 PC3 Combination of Input/Output Group A: Input Group B: Input PC1 Port C Group A: Input Group B: Output Group A: Output Group B: Input Group A: Output Group B: Output INTRB INTRB INTRB INTRB PC4 PC6 PC7 PC5 IBFB OBFB IBFB OBFB STBB ACKB STBB ACKB INTRA INTRA INTRA INTRA STBA STBA I/O I/O IBFA IBFA I/O I/O I/O I/O ACKA ACKA I/O I/O OBFA OBFA Note: I/O is a bit not used as the control signal, but it is available as a port of mode 0. Examples of the relation between the control words and pins when used in mode 1 are shown below: (a) When group A is mode 1 output and group B is mode 1 input.

• /CR111/00101 D7 D6 D5 D4 D3 D2 D1 D0 As all of PC0 - PC3 bits become a control pin in this case, this bit is "Don't Care". Control Word Selection of I/O of PC4 and PC5 when not defined as a control pin. OBFA ACKA INTRA I/O PC7 PC6 PC3 PC4, PC5 PA7 - PA0 RD Group A: Mode 1 Output Group B: Mode 1 Input STBB IBFB INTRB PC2 PC1 PC0 PB7 - PB0 WR 1 = Input 0 = Output

¡ Semiconductor MSM82C55A-2RS/GS/VJS (b) When group A is mode 1 input and group B is mode 1 output.

• /CR011/01101 D7 D6 D5 D4 D3 D2 D1 D0 Selection of I/O of PC6 and PC7 when not defined as a control pin. STBA IBFA INTRA I/O PC4 PC5 PC3 PC6, PC7 PA7 - PA0 Group A: Mode 1 Input Group B: Mode 1 Output OBFB ACKB INTRB PC1 PC2 PC0 PB7 - PB0 RD 1 = Input 0 = Output WR 3. Mode 2 (Strobe bidirectional bus I/O operation) In mode 2, it is possible to transfer data in 2 directions through a single 8-bit port. This operation is akin to a combination between input and output operations. Port C waits for the control signal in this case, too. Mode 2 is available only for group A, however. Next, a description is made on mode 2. OBF (Output buffer full flag output) This signal when turned to low level indicates that data has been written to the internal output latch upon receipt of the WR signal from the CPU. At this time, port A is still in the high impedance status and the data is not yet output to the outside. This signal turns to low level at the rising edge of the WR and high level at the falling edge of the ACK. ACK (Acknowledge input) When a low level signal is input to this pin, the high impedance status of port A is cleared, the buffer is enabled, and the data written to the internal output latch is output to port A. When the input returns to high level, port A is made into the high impedance status. STB (Strobe input) When this signal turns to low level, the data output to the port from the pin is fetched into the internal input latch. The data is output to the data bus upon receipt of the RD signal from the CPU, but it remains in the high impedance status until then. IBF (Input buffer full flag output) This signal when turned to high level indicates that data from the pin has been fetched into the input latch. This signal turns to high level at the falling edge of the STB and low level at the rising edge of the RD.

¡ Semiconductor MSM82C55A-2RS/GS/VJS INTR (Interrupt request output) This signal is used to interrupt the CPU and its operation in the same as in mode 1. There are two INTE flip-flops internally available for input and output to select either interrupt of input or output operation. The INTE1 is used to control the interrupt request for output operation and it can be reset by the bit set for PC6. INTE2 is used to control the interrupt request for the input operation and it can be set by the bit set for PC4. Mode 2 I/O Operation Following is an example of the relation between the control word and the pin when used in mode 2. When input in mode 2 for group A and in mode 1 for group B. PA7 PA0 - INTE1 PC7 PC6 OBFA ACKA RD PC3 INTRA PC4 PC5 STBA IBFA INTE2 WR Port C Function Allocation in Mode 2 PC0 PC2 PC3 PC1 Port C Confirmed to the Group B Mode PC4 PC6 PC7 PC5 INTRA STBA IBFA ACKA OBFA Function

¡ Semiconductor MSM82C55A-2RS/GS/VJS

• /CR11·/CR·/CR·/CR11 D7 D6 D5 D4 D3 D2 D1 D0 As all of 8 bits of port C become control pins in this case, D3 and D0 bits are treated as "Don't Care". No I/O specification is required for mode 2, since it is a bidirectional operation. This bit is therefore treated as "Don't Care". When group A is set to mode 2, this bit is treated as "Don't Care". INTRA OBFA ACKA STBA IBFA PC3 PC7 PC6 PC4 PC5 PA7 - PA0 STBB IBFB INTRB PC2 PC1 PC0 PB7 - PB0 WR RD Group A: Mode 2 Group B: Mode 1 Input

¡ Semiconductor MSM82C55A-2RS/GS/VJS 4. When Group A is Different in Mode from Group B Group A and group B can be used by setting them in different modes each other at the same time. When either group is set to mode 1 or mode 2, it is possible to set the one not defined as a control pin in port C to both input and output as port which operates in mode 0 at the 3rd and 0th bits of the control word. (Mode combinations that define no control bit at port C) When the I/O bit is set to input in this case, it is possible to access data by the normal port C read operation. When set to output, PC 7-PC4 bits can be accessed by the bit set/reset function only. Meanwhile, 3 bits from PC 2 to PC0 can be accessed by normal write operation. The bit set/reset function can be used for all of PC3-PC0 bits. Note that the status of port C varies according to the combination of modes like this. Group A Group B Port C PC7 PC6 PC5 PC4 PC3 PC2 PC1 Mode 1 input Mode 0 Output Mode 0 Mode 0 Mode 1 Input Mode 1 Input Mode 1 Output Mode 1 Output Mode 2 Mode 0 Mode 0 Mode 1 Input Mode 1 Output Mode 1 Input Mode 1 Output Mode 1 Input Mode 1 Output Mode 0 I/O I/O IBF A STBA INTRA I/O I/O PC0 I/O OBFA ACKA I/O I/O INTR A I/O I/O I/O I/O I/O I/O I/O I/O STBB IBFB INTRB I/O I/O I/O I/O I/O ACKB OBFB INTRB I/O I/O IBF A STBA INTRA STBB IBFB INTRB I/O I/O IBF A STBA INTRA ACKB OBFB INTRB OBFA ACKA I/O I/O INTR A STBB IBFB INTRB OBFA ACKA I/O I/O INTR A ACKB OBFB INTRB OBFA ACKA IBFA STBA INTRA I/O I/O I/O Controlled at the 3rd bit (D3) of the Control Word Controlled at the 0th bit (D0) of the Control Word

¡ Semiconductor MSM82C55A-2RS/GS/VJS 6. Reset of MSM82C55A-2 Be sure to keep the RESET signal at power ON in the high level at least for 50 ms. Subsequently, it becomes the input mode at a high level pulse above 500 ns. Note: Comparison of MSM82C55A-5 and MSM82C55A-2 5. Port C Status Read When port C is used for the control signal, that is, in either mode 1 or mode 2, each control signal and bus status signal can be read out by reading the content of port C. The status read out is as follows: Group A Group B Status Read on the Data Bus D7 D6 D5 D4 D3 D2 D1 Mode 1 Input Mode 1 Output Mode 0 Mode 0 Mode 1 Input Mode 1 Input Mode 1 Output Mode 1 Output Mode 2 Mode 0 Mode 0 Mode 1 Input Mode 1 Output Mode 1 Input Mode 1 Output Mode 1 Input Mode 1 Output Mode 0 I/O I/O IBF A INTEA INTRA I/O I/O I/O OBFA INTEA I/O I/O INTR A I/O I/O I/O I/O I/O I/O I/O I/O INTE B IBFB INTRB I/O I/O I/O I/O I/O INTE B OBFB INTRB I/O I/O IBF A INTEA INTRA INTEB IBFB INTRB I/O I/O IBF A INTEA INTRA INTEB OBFB INTRB OBFA INTEA I/O I/O INTR A INTEB IBFB INTRB OBFA INTEA I/O I/O INTR A INTEB OBFB INTRB OBFA INTE1 IBFA INTE2 INTRA I/O I/O I/O Mode 2 Mode 2 Mode 1 Input Mode 1 Output OBFA INTE1 IBFA INTE2 INTRA INTEB IBFB INTRB OBFA INTE1 IBFA INTE2 INTRA INTEB OBFB INTRB MSM82C55A-5 After a write command is executed to the command register, the internal latch is cleared in PORTA PORTC. For instance, 00H is output at the beginning of a write command when the output port is assigned. However, if PORTB is not cleared at this time, PORTB is unstable. In other words, PORTB only outputs ineffective data (unstable value according to the device) during the period from after a write command is executed till the first data is written to PORTB. MSM82C55A-2 After a write command is executed to the command register, the internal latch is cleared in All Ports (PORTA, PORTB, PORTC). 00H is output at the beginning of a write command when the output port is assigned.

¡ Semiconductor MSM82C55A-2RS/GS/VJS NOTICE ON REPLACING LOW-SPEED DEVICES WITH HIGH-SPEED DEVICES The conventional low speed devices are replaced by high-speed devices as shown below. When you want to replace your low speed devices with high-speed devices, read the replacement notice given on the next pages. High-speed device (New) Low-speed device (Old) Remarks M80C85AH M80C85A/M80C85A-2 8bit MPU M80C86A-10 M80C86A/M80C86A-2 16bit MPU M80C88A-10 M80C88A/M80C88A-2 8bit MPU M82C84A-2 M82C84A/M82C84A-5 Clock generator M81C55-5 M81C55 RAM.I/O, timer M82C37B-5 M82C37A/M82C37A-5 DMA controller M82C51A-2 M82C51A USART M82C53-2 M82C53-5 Timer M82C55A-2 M82C55A-5 PPI

¡ Semiconductor MSM82C55A-2RS/GS/VJS Differences between MSM82C55A-5 and MSM82C55A-2 1) Manufacturing Process These devices use a 3 m Si-Gate CMOS process technology. The MSM82C55A-2 is about 7% smaller in chip size than the MSM82C55A-5 as the MSM82C55A- 2 changed its output characteristics. 2) Function The above function has been improved to remove bugs and other logics are not different between the two devices. 3) Electrical Characteristics 3-1) DC Characteristics As shown above, the DC characteristics of the MSM82C55A-2 satisfies the DC characteristics of the MSM82C55A-5. 3-2) AC Characteristics Item MSM82C55A-5 MSM82C55A-2 Internal latch during writing into the command register Only ports A and C are cleared. Port B is not cleared. All ports are cleared. Parameter Symbol MSM82C55A-5 MSM82C55A-2 ''L'' Output Voltage 0.45 V (IOL = +2.5 mA) 0.40 V (IOL = +2.5 mA) 3.7 V (IOH = -2.5 mA) VOL VOH''H'' Output Voltage 2.4 V (IOH = -400 mA) 8 mA maximum (I/O Cycle = 375 ns)ICCAverage Operating Current 5 mA maximum (I/O Cycle = 1 ms) Parameter Symbol MSM82C55A-5 MSM82C55A-2 Address Hold Time for RD Rising 20 ns minimum 0 ns minimumtRA RD Pulse Width 300 ns minimum 100 ns minimumtRR Difined Data Output Delay Time From RD Falling 200 ns maximum 120 ns maximumtRD Data Floating Delay Time From RD Rising 100 ns maximum 75 ns maximumtRF RD/WR Recovery Time 850 ns minimum 200 ns minimumtRV

¡ Semiconductor MSM82C55A-2RS/GS/VJS As shown above, the MSM82C55A-2 satisfies the characteristics of the MSM82C55A-5. Parameter Symbol MSM82C55A-5 MSM82C55A-2 Address Hold Time for WR Rising 30 ns minimum 20 ns minimumtWA WR Pulse Width 300 ns minimum 150 ns minimumtWW Data Setup Time for WR Rising 1000 ns minimum 50 ns minimumtDW Data Hold Time for WR Rising 40 ns minimum 30 ns minimumtWD Defined Data Output Time From WR Rising 350 ns maximum 200 ns maximumtWB Port Data Hold Time for RD Rising 20 ns minimum 10 ns minimumtHR ACK Pulse Width 300 ns minimum 100 ns minimumtAK STB Pulse Width 300 ns minimum 100 ns minimumtST Port Data Hold Time for STB Falling 180 ns minimum 50 ns minimumtPH ACK Falling to Defined Data Output 300 ns maximum 150 ns maximumtAD WR Falling to OBF Falling Delay Time 650 ns maximum 150 ns maximumtWOB ACK Falling to OBF Rising Delay Time 350 ns maximum 150 ns maximumtAOB STB Falling to IBF Rising Delay Time 300 ns maximum 150 ns maximumtSIB RD Rising to IBF Falling Delay Time 300 ns maximum 150 ns maximumtRIB RD Falling to INTR Falling Delay Time 400 ns maximum 200 ns maximumtRIT STB Rising to INTR Rising Delay Time 300 ns maximum 150 ns maximumtSIT ACK Rising to INTR Rising Delay Time 350 ns maximum 150 ns maximumtAIT WR Falling to INTR Falling Delay Time 850 ns minimum 250 ns maximumtWIT

¡ Semiconductor MSM82C55A-2RS/GS/VJS (Unit : mm) PACKAGE DIMENSIONS Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). DIP40-P-600-2.54 Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 6.10 TYP.

¡ Semiconductor MSM82C55A-2RS/GS/VJS (Unit : mm) Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). QFJ44-P-S650-1.27 Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin Cu alloy Solder plating 5 mm or more 2.00 TYP. Mirror finish

¡ Semiconductor MSM82C55A-2RS/GS/VJS (Unit : mm) Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.41 TYP. QFP44-P-910-0.80-2K Mirror finish