82C51A

MSM82C51A-2RS OKI | Alldatasheet

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¡ Semiconductor MSM82C51A-2RS/GS/JS GENERAL DESCRIPTION The MSM82C51A-2 is a USART (Universal Synchronous Asynchronous Receiver Transmitter) for serial data communication. As a peripheral device of a microcomputer system, the MSM82C51A-2 receives parallel data from the CPU and transmits serial data after conversion. This device also receives serial data from the outside and transmits parallel data to the CPU after conversion. The MSM82C51A-2 configures a fully static circuit using silicon gate CMOS technology. Therefore, it operates on extremely low power at 100 mA (max) of standby current by suspending all operations.

FEATURES

• Wide power supply voltage range from 3 V to 6 V
• Wide temperature range from –40 °C to 85°C
• Synchronous communication upto 64 Kbaud
• Asynchronous communication upto 38.4 Kbaud
• Transmitting/receiving operations under double buffered configuration.
• Error detection (parity, overrun and framing)
• 28-pin Plastic DIP (DIP28-P-600-2.54): (Product name: MSM82C51A-2RS)
• 28-pin Plastic QFJ (QFJ28-P-S450-1.27): (Product name: MSM82C51A-2JS)
• 32-pin Plastic SSOP(SSOP32-P-430-1.00-K): (Product name: MSM82C51A-2GS-K) ¡ Semiconductor MSM82C51A-2RS/GS/JS UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER E2O0017-27-X2 This version: Jan. 1998 Previous version: Aug. 1996

¡ Semiconductor MSM82C51A-2RS/GS/JS FUNCTIONAL BLOCK DIAGRAM TXDD7 - D0 RESET CLK C/D RD WR CS DSR DTR CTS RTS Read/Write Control Logic Modem Control Transmit Buffer (P - S) Transmit Control Recieve Buffer (S - P) Recieve Control TXRDY TXE TXC RXD RXRDY RXC SYNDET/BD Data Bus Buffer Internal Bus Line

¡ Semiconductor MSM82C51A-2RS/GS/JS PIN CONFIGURATION (TOP VIEW) VCC RXC DTR RTS DSR RESET CLK TXD TXEMPTY CTS SYNDET/BD TXRDY 28 pin Plastic DIP GND RXD WR CS C/D RD RXRDY TXC 32 pin Plastic SSOP NC GND RXD D2 D1 WR CS NC C/D RD RXRDY VCC RXC TXC NC DTR RTS DSR RESET CLK TXD TXEMPTY NC CTS SYNDET/BD TXRDY RXC DTR RTS DSR RESET CLK TXD D TXC WR CS C/D RD RXRDY TXRDY SYNDET/BD CTS TXEMPTY GND RXD D VCC 28 pin Plastic QFJ

¡ Semiconductor MSM82C51A-2RS/GS/JS FUNCTION Outline The MSM82C51A-2's functional configuration is programed by software. Operation between the MSM82C51A-2 and a CPU is executed by program control. Table 1 shows the operation between a CPU and the device. Data Bus 3-State

1 Data Bus 3-State

Status fi CPU Control Word ‹ CPU

0 Data ‹ CPU

0 Data fi CPU

Table 1 Operation between MSM82C51A and CPU It is necessary to execute a function-setting sequence after resetting the MSM82C51A-2. Fig. 1 shows the function-setting sequence. If the function was set, the device is ready to receive a command, thus enabling the transfer of data by setting a necessary command, reading a status and reading/writing data. Asynchronous External Reset Internal Reset Write Mode Instruction Write First Sync Charactor yes no Single Sync Mode Write Second Sync Charactor yes no End of Mode Setting Fig. 1 Function-setting Sequence (Mode Instruction Sequence)

¡ Semiconductor MSM82C51A-2RS/GS/JS Control Words There are two types of control word. 1. Mode instruction (setting of function) 2. Command (setting of operation) 1) Mode Instruction Mode instruction is used for setting the function of the MSM82C51A-2. Mode instruction will be in “wait for write” at either internal reset or external reset. That is, the writing of a control word after resetting will be recognized as a “mode instruction.” Items set by mode instruction are as follows:

• Synchronous/asynchronous mode
• Stop bit length (asynchronous mode)
• Character length
• Parity bit
• Baud rate factor (asynchronous mode)
• Internal/external synchronization (synchronous mode)
• Number of synchronous characters (Synchronous mode) The bit configuration of mode instruction is shown in Figures 2 and 3. In the case of synchronous mode, it is necessary to write one-or two byte sync characters. If sync characters were written, a function will be set because the writing of sync characters constitutes part of mode instruction. S1 S1 EP PEN L2 L1 B2 B1 D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 0 1 1 Refer to Fig. 3 SYNC 1 ·/CR 16 ·/CR 64 ·/CR Baud Rate Factor 0 1 0 0 0 1 5 bits 6 bits 7 bits Charactor Length 8 bits 0 1 0 1 0 0 1 1 Disable Odd Parity Disable Even Parity Parity Check 0 1 0 0 0 1 Inhabit 1 bit 1.5 bits Stop bit Length 2 bits Fig. 2 Bit Configuration of Mode Instruction (Asynchronous)

¡ Semiconductor MSM82C51A-2RS/GS/JS D7 D6 D5 D4 D3 D2 D1 D0 SCS ESD EP PEN L2 L1 0 0 Charactor Length 0 1 0 0 0 1 5 bits 6 bits 7 bits 8 bits 0 1 0 1 0 0 1 1 Disable Odd Parity Disable Even Parity Parity 0 1 Internal Synchronization External Synchronization Synchronous Mode 0 1

2 Charactors 1 Charactor

Number of Synchronous Charactors Fig. 3 Bit Configuration of Mode Instruction (Synchronous)

¡ Semiconductor MSM82C51A-2RS/GS/JS 2) Command Command is used for setting the operation of the MSM82C51A-2. It is possible to write a command whenever necessary after writing a mode instruction and sync characters. Items to be set by command are as follows:

• Transmit Enable/Disable
• Receive Enable/Disable
• DTR, RTS Output of data.
• Resetting of error flag.
• Sending to break characters
• Internal resetting
• Hunt mode (synchronous mode) The bit configuration of a command is shown in Fig. 4. EH IR RTS ER SBRK RXE DTR TXEN 1… Transmit Enable 0… Disable DTR 1 fi DTR = 0 0 fi DTR = 1 1… Recieve Enable 0… Disable 1… Sent Break Charactor 0… Normal Operation 1… Reset Error Flag 0… Normal Operation RTS 1 fi RTS = 0 0 fi RTS = 1 1… Internal Reset 0… Normal Operation 1… Hunt Mode (Note) 0… Normal Operation Note: Seach mode for synchronous charactors in synchronous mode. Fig. 4 Bit Configuration of Command

¡ Semiconductor MSM82C51A-2RS/GS/JS Status Word It is possible to see the internal status of MSM82C51A-2 by reading a status word. The bit configuration of status word is shown in Fig. 5. Same as terminal. Refer to "Explanation" of Terminals. DSR SYNDET /BD FE OE PE TXEMPTY RXRDY TXRDY Parity Different from TXRDY Terminal. Refer to "Explanation" of TXRDY Terminals. 1… Parity Error 1… Overrun Error 1… Framing Error Note: Shows Terminal DSR 1… DSR = 0 0… DSR = 1 Only asynchronous mode. Stop bit cannot be detected. Fig. 5 Bit Configuration of Status Word Standby Status It is possible to put the MSM82C51A-2 in “standby status” When the following conditions have been satisfied the MSM82C51A-2 is in “standby status.” (1) CS terminal is fixed at Vcc level. (2) Input pins other CS , D0 to D7, RD, WR and C/D are fixed at Vcc or GND level (including SYNDET in external synchronous mode). Note: When all output currents are 0, ICCS specification is applied.

¡ Semiconductor MSM82C51A-2RS/GS/JS Pin Description D0 to D7 (l/O terminal) This is bidirectional data bus which receive control words and transmits data from the CPU and sends status words and received data to CPU. RESET (Input terminal) A “High” on this input forces the MSM82C51A-2 into “reset status.” The device waits for the writing of “mode instruction.” The min. reset width is six clock inputs during the operating status of CLK. CLK (Input terminal) CLK signal is used to generate internal device timing. CLK signal is independent of RXC or TXC. However, the frequency of CLK must be greater than 30 times the RXC and TXC at Synchronous mode and Asynchronous “x1” mode, and must be greater than 5 times at Asynchronous “x16” and “x64” mode. WR (Input terminal) This is the “active low” input terminal which receives a signal for writing transmit data and control words from the CPU into the MSM82C51A-2. RD (Input terminal) This is the “active low” input terminal which receives a signal for reading receive data and status words from the MSM82C51A-2. C/D (Input terminal) This is an input terminal which receives a signal for selecting data or command words and status words when the MSM82C51A-2 is accessed by the CPU. If C/D = low, data will be accessed. If C/D = high, command word or status word will be accessed. CS (Input terminal) This is the “active low” input terminal which selects the MSM82C51A-2 at low level when the CPU accesses. Note: The device won’t be in “standby status”; only setting CS = High. Refer to “Explanation of Standby Status.” TXD (output terminal) This is an output terminal for transmitting data from which serial-converted data is sent out. The device is in “mark status” (high level) after resetting or during a status when transmit is disabled. It is also possible to set the device in “break status” (low level) by a command.

¡ Semiconductor MSM82C51A-2RS/GS/JS TXRDY (output terminal) This is an output terminal which indicates that the MSM82C51A-2 is ready to accept a transmitted data character. But the terminal is always at low level if CTS = high or the device was set in “TX disable status” by a command. Note: TXRDY status word indicates that transmit data character is receivable, regardless of CTS or command. If the CPU writes a data character, TXRDY will be reset by the leading edge or WR signal. TXEMPTY (Output terminal) This is an output terminal which indicates that the MSM82C51A-2 has transmitted all the characters and had no data character. In “synchronous mode,” the terminal is at high level, if transmit data characters are no longer remaining and sync characters are automatically transmitted. If the CPU writes a data character, TXEMPTY will be reset by the leading edge of WR signal. Note : As the transmitter is disabled by setting CTS “High” or command, data written before disable will be sent out. Then TXD and TXEMPTY will be “High”. Even if a data is written after disable, that data is not sent out and TXE will be “High”.After the transmitter is enabled, it sent out. (Refer to Timing Chart of Transmitter Control and Flag Timing) TXC (Input terminal) This is a clock input signal which determines the transfer speed of transmitted data. In “synchronous mode,” the baud rate will be the same as the frequency of TXC. In “asynchronous mode”, it is possible to select the baud rate factor by mode instruction. It can be 1, 1/16 or 1/64 the TXC. The falling edge of TXC sifts the serial data out of the MSM82C51A-2. RXD (input terminal) This is a terminal which receives serial data. RXRDY (Output terminal) This is a terminal which indicates that the MSM82C51A-2 contains a character that is ready to READ. If the CPU reads a data character, RXRDY will be reset by the leading edge of RD signal. Unless the CPU reads a data character before the next one is received completely, the preceding data will be lost. In such a case, an overrun error flag status word will be set. RXC (Input terminal) This is a clock input signal which determines the transfer speed of received data. In “synchronous mode,” the baud rate is the same as the frequency of RXC. In “asynchronous mode,” it is possible to select the baud rate factor by mode instruction. It can be 1, 1/16, 1/64 the RXC.

¡ Semiconductor MSM82C51A-2RS/GS/JS SYNDET/BD (Input or output terminal) This is a terminal whose function changes according to mode. In “internal synchronous mode.” this terminal is at high level, if sync characters are received and synchronized. If a status word is read, the terminal will be reset. In “external synchronous mode, “this is an input terminal. A “High” on this input forces the MSM82C51A-2 to start receiving data characters. In “asynchronous mode,” this is an output terminal which generates “high level”output upon the detection of a “break” character if receiver data contains a “low-level” space between the stop bits of two continuous characters. The terminal will be reset, if RXD is at high level. After Reset is active, the terminal will be output at low level. DSR (Input terminal) This is an input port for MODEM interface. The input status of the terminal can be recognized by the CPU reading status words. DTR (Output terminal) This is an output port for MODEM interface. It is possible to set the status of DTR by a command. CTS (Input terminal) This is an input terminal for MODEM interface which is used for controlling a transmit circuit. The terminal controls data transmission if the device is set in “TX Enable” status by a command. Data is transmitable if the terminal is at low level. RTS (Output terminal) This is an output port for MODEM interface. It is possible to set the status RTS by a command.

¡ Semiconductor MSM82C51A-2RS/GS/JS ABSOLUTE MAXIMUM RATING –55 to +150 MSM82C51A-2RS Power Supply Voltage VCC –0.5 to +7 V Input Voltage VIN –0.5 to VCC +0.5 V Output Voltage VOUT –0.5 to VCC +0.5 V Storage Temperature TSTG °C Power Dissipation PD 0.7 W Parameter Unit Symbol With respect to GND Ta = 25°C ConditionsRating MSM82C51A-2GS MSM82C51A-2JS 0.90.9 OPERATING RANGE Range Power Supply Voltage VCC 3 - 6 V Operating Temperature Top –40 to 85 °C Parameter UnitSymbol RECOMMENDED OPERATING CONDITIONS DC CHARACTERISTICS Typ. Max. "L" Output Voltage VOL — 0.45 V "H" Output Voltage VOH ——V Parameter Unit Symbol Min. 3.7 IOL = 2.5 mA IOH = –2.5 mA Measurement Conditions Input Leak Current ILI —1 0 mA Output Leak Current ILO —1 0 mA –10 –10 0 £ VIN £ VCC 0 £ VOUT £ VCC Operating Supply Current —5 m A— Asynchronous X64 during Transmitting/ Receiving Standby Supply Current — 100 mA ICCO ICCS All Input voltage shall be fixed at VCC or GND level. (VCC = 4.5 to 5.5 V Ta = –40°C to +85°C) Typ. Power Supply Voltage VCC 5V Top +25 "L" Input Voltage V IL — "H" Input Voltage VIH — Min. 4.5 –40 –0.3 2.2 Max. 5.5 +85 +0.8 VCC +0.3 Parameter UnitSymbol V V Operating Temperature

¡ Semiconductor MSM82C51A-2RS/GS/JS AC CHARACTERISTICS CPU Bus Interface Part Max. Address Stable before RD tAR — ns Parameter Unit Symbol Min.

20 Note 2

Address Hold Time for RD tRA — ns RD Pulse Width t RR — ns 130 Note 2 Data Delay from RD tRD 100 ns— — RD to Data Float tDF 75 ns10 — Recovery Time between RD tRVR — tCY Address Stable before WR tAW — ns Note 5 Note 2 Address Hold Time for WR tWA — ns20 Note 2 WR Pulse Width tWW — ns100 — Data Set-up Time for WR tDW — ns Data Hold Time for WR tWD — ns 100 Recovery Time between WR tRVW — tCY6 Note 4 RESET Pulse Width tRESW — tCY6 — (VCC = 4.5 to 5.5 V, Ta = –40 to 85°C)

¡ Semiconductor MSM82C51A-2RS/GS/JS Serial Interface Part Notes: 1. AC characteristics are measured at 150 pF capacity load as an output load based on 0.8 V at low level and 2.2 V at high level for output and 1.5 V for input. 2. Addresses are CS and C/D. 3. f TX or fRX £ 1/(30 Tcy) 1 · Baud fTX or fRX £ 1/(5 Tcy) 16 ·, 64· Baud 4. This recovery time is mode Initialization only. Recovery time between command writes for Asynchronous Mode is 8 t CY and for Synchronous Mode is 18 t CY. Write Data is allowed only when TXRDY = 1. 5. This recovery time is Status read only. Read Data is allowed only when RXRDY = 1. 6. Status update can have a maximum delay of 28 clock periods from event affecting the status. Max. Main Clock Period t CY — ns Parameter Unit Symbol Min.

160 Note 3

Clock Low Tme t f/CR — ns Clock High Time t f/CR tCY –50 ns Clock Rise/Fall Time tr, tf 20 ns— — TXD Delay from Falling Edge of TXC tDTX 1 mS— — Transmitter Clock Frequency fTX 64 kHz fTX 615 kHz DC DC Note 3 fTX 615 kHzDC 1 · Baud 16 · Baud 64 · Baud Transmitter Clock Low Time tTPW — tCY1 · Baud — tTPW — tCY Transmitter Clock High Time tTPD — 15 tCY 16 ·, 64 · Baud 1 · Baud tTPD — tCY316 ·, 64 · Baud — Receiver Clock Frequency fRX 64DC kHz1 · Baud fRX 615 kHz fRX 615 kHz DC DC 16 · Baud 64 · Baud Note 3 Receiver Clock Low Time tRPW — tCY13 — tRPW — tCY2 1 · Baud 16 ·, 64 · Baud — Receiver Clock High Time tRPD — tCY tRPD — tCY 1 · Baud 16 ·, 64 · Baud Time from the Center of Last Bit to the Rise of TXRDY tTXRDY 8 tCY— — Time from the Leading Edge of WR to the Fall of TXRDY tTXRDY CLEAR 400 ns— — Time From the Center of Last Bit to the Rise of RXRDY tRXRDY 26 tCY— — Time from the Leading Edge of RD to the Fall of RXRDY tRXRDY CLEAR 400 ns— — Internal SYNDET Delay Time from Rising Edge of RXC tIS 26 tCY— — MODEM Control Signal Delay Time from Rising Edge of WR tWC — tCY8 — MODEM Control Signal Setup Time for Falling Edge of RD tCR — tCY20 — RXD Setup Time for Rising Edge of RXC (1X Baud) tRXDS — tCY11 — RXD Hold Time for Falling Edge of RXC (1X Baud) tRXDH — tCY17 — SYNDET Setup Time for RXC tES — tCY18 — TXE Delay Time from the Center of Last Bit t TXEMPTY — tCY20 — (VCC = 4.5 to 5.5 V, Ta = –40 to 85°C)

¡ Semiconductor MSM82C51A-2RS/GS/JS TIMING CHART Sytem Clock Input tf tr tf/CR tf/CR tCY CLK Receiver Clock and Data Transmitter Clock and Data tTPW TXC (1 · MODE) tTPD tDTX tDTX TXC (16 · MODE) TXD RXC (1 · Mode) tRPW RXC (16 · Mode) RXD INT Sampling Pulse (RXBAUD Counter starts here) Start bit 8RXC Periods (16·Mode) 16 RXC Periods (16 · Mode) Data bit Data bit tRPD 3tCY 3tCY tf/CR

¡ Semiconductor MSM82C51A-2RS/GS/JS Read Control or Input Port Cycle (CPU ‹ USART) Write Control or Output Port Cycle (CPU fi USART) Read Data Cycle (CPU ‹ USART) tRR tRD tDF Data Out Active tAR tRA tAR tRA tRXRDY Clear Data Float Data Float RD DATA OUT (D. B.) RXRDY CS C/D Write Data Cycle (CPU fi USART) tTXRDY Clear tDW tWD tAW tWA tAW tWA Data StableDon't Care Don't Care WR DATA IN (D. B.) TXRDY CS C/D tWW tCR tRR tRD tAR tRA tAR tRA tDF Data FloatData Out ActiveData Float DSR. CTS DATA OUT (D. B.) RD C/D CS DTR. RTS DATA IN (D. B.) WR C/D CS tWW tWC tAW tWA tAW tWA Data StableDon't Care Don't Care tWDtDW

¡ Semiconductor MSM82C51A-2RS/GS/JS Transmitter Control and Flag Timing (ASYNC Mode) DATA CHAR 1 DATA CHAR 2 DATA CHAR 3 DATA CHAR 4 START BIT STOP BIT Wr TxEn Wr SBRK tTXEMPTY tTXRDY CTS TXEMPTY TXRDY (STATUS BIT) TXRDY (PIN) C/D WR TXD Wr DATA 1 Wr DATA 2 Wr DATA 3 Wr DATA 4 Note: The wave-form chart is based on the case of 7-bit data length + parity bit + 2 stop bit. Transmitter Control and Flag Timing (SYNC Mode) Receiver Control and Flag Timing (ASYNC Mode) Data CHAR 1 Data CHAR 2 Data CHAR 3 Break Data Bit Start Bit Stop Bit Parity Bit RxEn Err Res RxEn tRXRDY DATA CHAR2 Lost Wr RxEn BREAK DETECT FRAMING ERROR (Status Bit) OVERRUN ERROR (Status Bit) RXRDY C/D WR RD RXDATA Wr Error Rd Data Note: The wave-form chart is based on the case of 7 data bit length + parity bit + 2 stop bit. 01234 01234 01234 01234 01234 01234 01234 01234 01 Data CHAR1 Data CHAR2 SYNC CHAR1 SYNC CHAR2 SYNC CHAR3 Data CHAR4 Marking State Spacing State Marking State Data CHAR5 SYNC CHAR ETC PARPARPARPARPARPARPARPAR Wr Commond SBRK Wr Data CHAR5 CTS TXEMPTY TXRDY (StatusBit) TXRDY (Pin) C/D WR TXD Wr Data CHAR1 Marking State Wr Data CHAR2 Wr Data CHAR3 Wr Data CHAR4 Note: The wave-form chart is based on the case of 5 data bit length + parity bit and 2 synchronous charactors.

¡ Semiconductor MSM82C51A-2RS/GS/JS Receiver Control and Flag Timing (SYNC Mode) x x x x x x 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 x x x x x x x 0 1 2 3 4 0 1 x 3 4 SYNDET (Pin) (Note 1) SYNDET (SB) OVERRUN ERROR (SB) RXRDY (PIN) C/D WR RD RXD RXC Don't Care SYNC CHAR 1 SYNC CHAR 2 Data CHAR 1 Data CHAR 2 Data CHAR 3 SYNC CHAR 1 SYNC CHAR 2 Don't Care Data CHAR 1 Data CHAR 2 ETC CHAR ASSY Begins Exit Hunt Mode Set SYNDET Exit Hunt Mode Set SYNDET (Status bit) Set SYNDET (Status bit) CHAR ASSY Begins Wr EH RxEn Rd Data CHAR 1 Rd Status Wr Err Res Rd Data CHAR 3 Rd SYNC CHAR 1 Rd Status Wr EHo Rd Status Data CHAR2 Lost tIS tES (Note 2) Note: PAR PAR PAR PAR PAR PAR PAR PAR PAR PAR 1. Internal Synchronization is based on the case of 5 data bit length + parity bit and 2 synchronous charactor. 2. External Synchronization is based on the case of 5 data bit length + parity bit. Note: 1. Half-bit processing for the start bit When the MSM82C51A-2 is used in the asynchronous mode, some problems are caused in the processing for the start bit whose length is smaller than the 1-data bit length. (See Fig. 1.) 2. Parity flag after a break signal is received (See Fig. 2.) When the MSM82C51A-2 is used in the asynchrous mode, a parity flag may be set when the next normal data is read after a break signal is received. A parity flag is set when the rising edge of the break signal (end of the break signal) is changed between the final data bit and the parity bit, through a RXRDY signal may not be outputted. If this occurs, the parity flag is left set when the next normal dats is received, and the received data seems to be a parity error. Smaller than 7-Receiver Clock Length ·16 Start bit Length Mode Operation The short start bit is ignored. (Normal) Smaller than 31-Receiver Clock Length ·64 8-Receiver Clock Length ·16 The short start bit is ignored. (Normal) Data cannot be received correctly due to a malfunction. 32-Receiver Clock Length ·64 Data cannot be received correctly due to a malfunction. 9 to 16-Receiver Clock Length ·16 The bit is regarded as a start bit. (normal) 33 to 64-Receiver Clock Length ·64 The bit is regarded as a start bit. (normal)

¡ Semiconductor MSM82C51A-2RS/GS/JS Half-bit Processing Timing Chart for the Start bit (Fig. 1) ST D 0 D1 D2 D3 D4 D5 D6 D7 PS P S T D 0 D1 D2 D3 D4 D5 D6 D7 PS PRXD RXRDY ST ST D 0 D1 D2 D3 D4 D5 D6 D7 PS PRXD RXRDY A RXRDY signal is outputted during data reception due to a malfunction. ST ST D 0 D1 D2 D3 D4 D5 D6 D7 PS PRXD RXRDY ST: SP: D 0 - D7: Start bit Stop bit Parity bit Data bits ST ST D 0 D1 D2 D3 D4 D5 D6 D7 PS PRXD RXRDY Normal Operation The Start bit Is Shorter Than a 1/2 Data bit The Start bit Is a 1/2 Data bit (A problem of MSM82C51A-2) The Start bit Is Longer Than a 1/2 Data bit

¡ Semiconductor MSM82C51A-2RS/GS/JS Break Signal Reception Timing and Parity Flag (Fig. 2) ST D0 D7 P SP ST D0 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 PBIT POS. RXD RXRDY ›/CR A parity flag is set, but, no RXRDYsignal is outputted. SP ST D0 D7 P SP ST D0 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 PBIT POS. RXD RXRDY ›/CR No parity flag is set. and no RXRDY signal is outputted. ST D0 D7 P SP ST D0 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 PBIT POS. RXD RXRDY ›/CR A parity flag is set. and a RXRDY signal is out putted. SP Normal Operation Bug Timing Normal Operation SP

¡ Semiconductor MSM82C51A-2RS/GS/JS NOTICE ON REPLACING LOW-SPEED DEVICES WITH HIGH-SPEED DEVICES The conventional low speed devices are replaced by high-speed devices as shown below. When you want to replace your low speed devices with high-speed devices, read the replacement notice given on the next pages. High-speed device (New) Low-speed device (Old) Remarks M80C85AH M80C85A/M80C85A-2 8bit MPU M80C86A-10 M80C86A/M80C86A-2 16bit MPU M80C88A-10 M80C88A/M80C88A-2 8bit MPU M82C84A-2 M82C84A/M82C84A-5 Clock generator M81C55-5 M81C55 RAM.I/O, timer M82C37B-5 M82C37A/M82C37A-5 DMA controller M82C51A-2 M82C51A USART M82C53-2 M82C53-5 Timer M82C55A-2 M82C55A-5 PPI

¡ Semiconductor MSM82C51A-2RS/GS/JS Differences between MSM82C51A and MSM82C51A-2 1) Manufacturing Process These devices use a 3 m Si-Gate CMOS process technology and have the same chip size. 2) Function These devices have the same logics except for changes in AC characteristics listed in (3-2). 3) Electrical Characteristics 3-1) DC Characteristics Although the output voltage characteristics of these devices are identical, but the measurement conditions of the MSM82C51A-2 are more restricted than the MSM82C51A. 3-2) AC Characteristics As shown above, the MSM82C51A-2 satisfies the characteristics of the MSM82C51A. Parameter Symbol MSM82C51A MSM82C51A-2 RD Pulse Width 250 ns minimum 130 ns minimumtRR RD Rising to Data Difinition 200 ns maximum 100 ns maximumtRD RD Rising to Data Float 100 ns maximum 75 ns minimumtRF WR Pulse Width 250 ns minimum 100 ns minimumtWW Data Setup Time for WR Rising 150 ns minimum 100 ns minimumtDW Data Hold Time for WR Rising 20 ns minimum 0 ns minimumtWD Master Clock Period 250 ns minimum 160 ns minimumtCY Clock Low Time 90 ns minimum 50 ns minimum Clock High Time 120 ns minimum tCY-90 ns maximum 70 ns minimum tCY-50 ns maximumtf tf Parameter Symbol MSM82C51A MSM82C51A-2 VOL measurement conditions +2.0 mA +2.5 mA VOH measurement conditions -400 mA -2.5 mA IOL IOH

¡ Semiconductor MSM82C51A-2RS/GS/JS (Unit : mm) PACKAGE DIMENSIONS Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). DIP28-P-600-2.54 Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 4.30 TYP.

¡ Semiconductor MSM82C51A-2RS/GS/JS (Unit : mm) Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). QFJ28-P-S450-1.27 Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin Cu alloy Solder plating 5 mm or more 1.00 TYP. Spherical surface

¡ Semiconductor MSM82C51A-2RS/GS/JS (Unit : mm) Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). SSOP32-P-430-1.00-K Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.60 TYP. Mirror finish

¡ Semiconductor MSM82C51A-2RS/GS/JS 4) Notices on use Note the following when replacing devices as the ASYNC pin is differently treated between the MSM82C84A and the MSM82C84A-5/MSM82C84A-2: Case 1: When only a pullup resistor is externally connected to. The MSM82C84A can be replaced by the MSM82C84A-2. Case 2: When only pulldown resistor is externally connected to. When the pulldown resistor is 8 kiloohms or less, the MSM82C84A can be replaced by the MSM82C84A-2. When the pulldown resistor is greater than 8 kiloohms, use a pulldown resistor of 8 kiloohms or less. Case 3: When an output of the other IC device is connected to the device. The MSM82C84A can be replaced by the MSM82C84A-2 when the IOL pin of the device to drive the ASYNC pin of the MSM82C84A-2 has an allowance of 100 mA or more.