82C37

MSM82C37B-5RS OKI | Alldatasheet

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¡ Semiconductor MSM82C37B-5RS/GS/VJS GENERAL DESCRIPTION The MSM82C37B-5RS/GS/VJS, DMA (Direct Memory Access) controller is capable of high- speed data transfer without CPU intervention and is used as a peripheral device in microcomputer systems. The device features four independent programmable DMA channels. Due to the use of silicon gate CMOS technology, standby current is 10 mA (max.), and power consumption is as low as 10 mA (max.) when a 5 MHz clock is generated. All items of AC characteristics are compatible with intel 8237A-5.

FEATURES

• Maximum operating frequency of 5 MHz (Vcc = 5 V ±10%)
• High-speed operation at very low power consumption due to silicon gate CMOS technology
• Wide operating temperature range from –40 °C to +85°C
• 4-channels independent DMA control
• DMA request masking and programming
• DMA request priority function
• DREQ and DACK input/output logic inversion
• DMA address increment/decrement selection
• Memory-to-Memory Transfers
• Channel extension by cascade connection
• DMA transfer termination by EOP input
• Intel 8237A-5 compatibility
• TTL Compatible
• 40-pin Plastic DIP (DIP40-P-600-2.54): (Product name: MSM82C37B-5RS)
• 44-pin Plastic QFJ (QFJ44-P-S650-1.27): (Product name: MSM82C37B-5VJS)
• 44-pin Plastic QFP (QFP44-P-910-0.80-2K): (Product name: MSM82C37B-5GS-2K) ¡ Semiconductor MSM82C37B-5RS/GS/VJS PROGRAMMABLE DMA CONTROLLER E2O0016-39-81 This version: Aug. 1999 Previous version: Jan. 1998

¡ Semiconductor MSM82C37B-5RS/GS/VJS PIN CONFIGURATION (TOP VIEW) 40 pin Plastic DIP IOR MEMR MEMW READY HLDA ADSTB AEN HRQ CS GND A EOP DB0 DB1 DB2 DB3 DB4 DACK0 DACK1 DB5 DB6 DB7 VCC (+5 V) DREQ0 DREQ1 DREQ2 IOW NC DREQ3 DACK3 DACK2 RESET CLK 44 pin Plastic QFP VCC A NC DB0 READY HLDA ADSTB AEN HRQ NC CS DREQ DREQ2 DREQ1 DREQ0 GND NC DB7 NC MEMW MEMR IOW IOR NC DB DB2 DB3 CLK RESET DACK2 DACK3 11 DB DB DB5 DACK1 DACK0 A EOP NC A DB4 DB0 NC READY HLDA ADSTB AEN HRQ CS DACK DREQ3 DREQ2 DREQ1 DREQ0 GND DB7 NC MEMW MEMR IOW IOR NC A DB DB2 DB3 CLK RESET DACK2 NC V CC DB DB5 DACK1 DACK0 A EOP 44 pin Plastic QFJ

¡ Semiconductor MSM82C37B-5RS/GS/VJS BLOCK DIAGRAM 8 4 IOR IOW MEMR MEMW READY ADSTB AEN CS CLK RESET EOP Timing Control Circuit TC (Terminal Count) Decrementer Temporary Word Count Register (16) HLDA HRQ DREQ0 - 3 DACK0 - 3 Priority Judgment Circuit Mode Register (4 · 16) Command Register (8) Mark Register (4) Request Register (4) Incrementer/Decrementer Temporary Address Register (16)

16 Bit Bus 16 Bit Bus

(4 · 16) Current Word Count Register (4 · 16) Base Address Register (4 · 16) Current Address Register (4 · 16) Internal Data Bus Status Register (8) Temporary Register (8) Input/Output Buffer Output Buffer Input/Output Buffer Command Control Circuit D0 - 1 A4 - A7 A0 - A3 DB0 - DB7 A8 - A15

¡ Semiconductor MSM82C37B-5RS/GS/VJS ABSOLUTE MAXIMUM RATINGS –55 to +150 MSM82C37B-5RS Power Supply Voltage VCC –0.5 to +7 V Input Voltage VIN –0.5 to VCC +0.5 V Output Voltage VOUT –0.5 to VCC +0.5 V Storage Temperature TSTG °C Power Dissipation PD W Parameter UnitSymbol with respect to GND Ta = 25°C Conditions Rating 1.0 MSM82C37B-5GS 0.7 MSM82C37B-5VJS 1.0 RECOMMENDED OPERATING CONDITIONS DC CHARACTERISTICS "L" Output Voltage V OL "H" Output Voltage VOH Parameter Symbol Min. 3.7 –10 IOL = 3.2 mA VCC = 4.5 V to 5.5 V Ta = –40°C to +85°C IOH = –1.0 mA Conditions Input Leak Current I LI Output Leak Current I LO –10 0V £ VIN £ VCC 0V £ VOUT £ VCC Average Power Supply Current during Operations ICC Input frequency

5 MHz, when RESET

VIN = 0 V/VCC, CL = 0 pF Power Supply Current in Standby Mode ICCS — HLDA = 0 V, VIL = 0 V, VIH = VCC Typ. Max. 0.4 Unit V V mA mA mA mA Min. Power Supply Voltage VCC 4.5 V Operating Temperature Top –40 °C "L" Input Voltage VIL –0.5 V "H" Input Voltage TIH 2.2 V Typ. 5.0 +25 Max. 5.5 +85 +0.8 VCC + 0.5 Parameter UnitSymbol

¡ Semiconductor MSM82C37B-5RS/GS/VJS AC CHARACTERISTICS DMA (Master) Mode ItemSymbol Min. Max. Unit Delay Time from CLK Falling Edge up to AEN Leading Edge Comments tAEL (Ta = –40 to +85°C, V CC = 4.5 to 5.5 V) —— 200 ns Delay Time from CLK Rising Edge up to AEN Trailing EdgetAET —— 130 ns Delay Time from CLK Rising Edge up to Address Floating StatustAFAB —— 90 ns Delay Time from CLK Rising Edge up to Read/Write Signal Floating StatustAFC —— 120 ns Delay Time from CLK Rising Edge up to Data Bus Floating StatustAFDB —— 170 ns Address Valid Hold Time to Read Signal Trailing EdgetAHR tCY – 100 — — ns Data Valid Hold Time to ADSTB Trailing EdgetAHS 30 — — ns Address Valid Hold Time to Write Signal Trailing EdgetAHW tCY – 50 — — ns Delay Time from CLK Falling Edge up to Active DACK — (Note 3) 170 ns Delay Time from CLK Rising Edge up to EOP Leading EdgetAK — (Note 5) 170 ns Delay Time from CLK Rising Edge up to EOP Trailing Edge —— 170 ns Time from CLK Rising Edge up to Address ValidtASM —— 170 ns Data Set-up Time to ADSTB Trailing EdgetASS 100 — — ns Clock High-level TimetCH 68 (Note 6) — ns Clock Low-level TimetCL 68 (Note 6) — ns CLK Cycle TimetCY 200 — — ns

¡ Semiconductor MSM82C37B-5RS/GS/VJS ItemSymbol Min. Max. Unit Comments Delay Time from CLK Rising Edge to Read/Write Signal Leading EdgetDCL — (Note 2) 190 ns Delay Time from CLK Rising Edge to Read Signal Trailing EdgetDCTR — (Note 2) 190 ns Delay Time from CLK Rising Edge to Write Signal Trailing EdgetDCTW — (Note 2) 130 ns Delay Time from CLK Rising Edge to HRQ ValidtDQ —— 120 ns EOP Leading Edge Set-up Time to CLK Falling EdgetEPS 40 — — ns EOP Pulse WidthtEPW 220 —— ns Delay Time from CLK Rising Edge to Address ValidtFAAB —— 170 ns Time from CLK Rising Edge up to Active Read/Write SignaltFAC —— 150 ns Delay Time from CLK Rising Edge to Data ValidtFADB —— 200 ns HLDA Valid Set-up Time to CLK Rising EdgetHS 75 — — ns Input Data Hold Time to MEMR Trailing EdgetIDH 0— — ns Input Data Set-up to MEMR Trailing EdgetIDS 170 — — ns Output Data Hold Time to MEMW Trailing EdgetODH tODV 10 — — ns Time from Output Data Valid to MEMW Trailing Edge 125 — — ns DREQ Set-up Time to CLK Falling EdgetQS 0 (Note 3) — ns READY Hold Time to CLK Falling EdgetRH 20 — — ns READY Set-up Time to CLK Falling EdgetRS 60 — — ns Delay Time from CLK Rising Edge to ADSTB Leading EdgetSTL —— 130 ns Delay Time from CLK Rising Edge to ADSTB Trailing EdgetSTT —— 90 ns DMA (Master) Mode (continued)

¡ Semiconductor MSM82C37B-5RS/GS/VJS Slave Mode ItemSymbol Min. Max. Unit Time from Address Valid or CS Leading Edge to IOR Leading Edge Comments tAR (Ta = –40 to +85°C, V CC = 4.5 to 5.5 V) 50 — — ns Address Valid Set-up Time to IOW Trailing EdgetAW 130 — — ns CS Leading Edge Set-up Time to IOW trailing edgetCW 130 — — ns Data Valid Set-up Time to IOW Trailing EdgetDW 130 — — ns Address or CS Hold Time to IOR Trailing EdgetRA 0— — ns Data Access Time to IOR Leading EdgetRDE —— 140 ns Delay Time to Data Floating Status from IOR Trailing EdgetRDF 0— 70 ns Supply Power Leading Edge Set-up time to RESET Trailing EdgetRSTD 500 — — ns Time to First Active IOR or IOW from RESET Trailing EdgetRSTS 2tCY —— ns RESET Pulse WidthtRSTW 300 — — ns IOR Pulse WidthtRW 200 — — ns Address Hold Time to IOW Trailing EdgetWA 20 — — ns CS Trailing Edge Hold Time to IOW Trailing EdgetWC 20 — — ns Data Hold Time to IOW Trailing EdgetWD 30 — — ns IOW Pulse WidthtWWS 160 — — ns Notes: 1. Output load capacitance of 150 (pF). 2. IOW and MEMW pulse widths of tCY – 100 (ns) for normal writing, and 2tCY – 100 (ns) for extended writing. IOR and MEMR pulse widths of 2tCY – 50 (ns) for normal timing, and tCY – 50 (ns) for compressed timing. 3. DREQ and DACK signal active level can be set to either low or high. In the timing chart, the DREQ signal has been set to active-high, and the DACK signal to active- low. 4. When the CPU executes continuous read or write in programming mode, the interval during which the read or write pulse becomes active must be set to at least 400 ns. 5. EOP is an open drain output. The value given is obtained when a 2.2 k W pull-up resistance is connected to V CC. 6. Rise time and fall time are less than 10 ns. 7. Waveform measurement points for both input and output signals are 2.2 V for HIGH and 0.8 V for LOW, unless otherwise noted.

¡ Semiconductor MSM82C37B-5RS/GS/VJS TIMING CHART Reset Timing Slave Mode Write Timing VCC tRSTD tRSTW RESET IOR, IOW tRSTS CS Input Valid Address Input Valid Data tWC tWA tWD IOW A0 - A3 DB0 - DB7 tCW tWWS tAW tDW CS A0 - A3 tRW tRDE tRDF tRAtAR IOR DB0 - DB7 Input Valid Address Output Valid Data Slave Mode Read Timing

¡ Semiconductor MSM82C37B-5RS/GS/VJS DMA Transfer Timing SI SI S 0 S0 S1 S2 S3 S4 S2 S3 S4 SI SI CLK DREQ HRQ HLDA AEN ADSTB DB0 - DB7 A0 - A7 DACK IOR, MEMR IOW, MEMW Internal EOP (Output) External EOP (Input) tQS tDQ tHS tAEL tSTL tSTT tQS tDQ tAET tCL tCH tCY tASS tAHS tAFDBtFAAB tAHW tASM tAHR tAK tAFAB tAK tFAC tDCL tDCTR tAFC tDCL tDCTW tAK tAK tEPS tEPW tFADB (Extended Write) A0 - A7 A8 - A15 A0 - A7

¡ Semiconductor MSM82C37B-5RS/GS/VJS Memory to Memory Transfer Timing tSTL tSTT tSTL tSTT tFAAB tFADB tFAC tFAC tEPS tEPW tEPW tEPS tDCL tAFDB tAHS tIDS tDCTR tIDH tFADB tAK tAK tDCL tDCTW tAFC tAFC tODV tODH tAFDB tAFABtASM tAHS CLK ADSTB DB0 - DB7 A0 - A7 MEMW MEMR Internal EOP (Output) External EOP (Input) Valid Address A0 - 7 Valid Address A0 - 7 Data InputA8 - A15 A8 - A15 Data Output S0 S11 S12 S13 S14 S21 S22 S23 S24 SI tDCL tDCL tDCL tDCTR tDCTW tRH tRH tRStRS (Extended Write) CLK IOR, MEMR IOW, MEMW READY S2 S3 SW SW S4 Ready Timing

¡ Semiconductor MSM82C37B-5RS/GS/VJS Compressed Transfer Timing tASM tASM tDCL tDCTR tDCL tDCTR tDCTW tDCL tDCTW tRS tRStRH tRH tAK tAK tEPS tEPW Valid Address S2 S4 S2 S4 CLK A0 - A7 IOR, MEMR IOW, MEMW Internal EOP (Output) External EOP (Input) READY

¡ Semiconductor MSM82C37B-5RS/GS/VJS PIN FUNCTIONS PowerVCC Symbol Pin Name Input/Output Function +5 V power supply GroundGND — Ground (0 V) connection. ClockCLK Input Control of MSM82C37B-5 internal operations and data transfer speed. Chip SelectCS Input CS is active-low input signal used for the CPU to select the MSM82C37B-5 as an I/O device in an idle cycle. Hold AcknowledgeHLDA Input HLDA is active-high input signal used to indicate that system bus control has been released when a hold request is recieved by the CPU. ResetRESET Input RESET is active-high asynchrounous input signal used to clear command, status, request, temporary registers, and first/last F/F, and to set mask register. The MSM82C37B-5 enters an idle cycle following a RESET. ReadyREADY Input The read or write pulse width can be extended to accomodate slow access memories and I/O devices when this input is switched to low level. Note this input must not change within the prescribed set-up/hold time. I/O ReadIOR Input/Output IOR is active-low bidirectional three-state signal used as an input control signal for CPU reading of MSM82C37B-5 internal registers during idle cycles, and as an output control signal for reading I/O device transfer data in writing transfers during active cycles. I/O WriteIOW Input/Output IOW is active-low bidirectional three-state signal used as an input control signal for CPU writing of MSM82C37B-5 internal registers during idle cycles, and as an output control signal for writing I/O device transfer data in writing transfers during active cycles. DMA Request 0 - 3 Channels DREQ 0 - DREQ3 Input DREQ is asynchronous DMA transfer request input signals. Although these pins are switched to active-high by reset, they can be programmed to become active-low. DMA requests are received in accordance with a prescribed order of priority. DREQ must be held until DACK becomes active. Data Bus 0 - 7DB 0 - DB7 Input/Output DB is bidirectional three-state signals connected to the system data bus, and which is used as an input/output of MSM82C37B-5 internal registers during idle cycles, and as an output of the eight higher order bits of transfer addresses during active cycles. Also used as input and output of transfer data during memory- memory transfers.

¡ Semiconductor MSM82C37B-5RS/GS/VJS Symbol Pin Name Input/Output Function End of ProcessEOP Input/Output EOP is active-low bidirectional three-state signal. Unlike other pins, this pin is an N-channel open drain. During DMA operations, a low-level output pulse is obtained from this pin if the channel word count changes from 0000H to FFFFH. And DMA transfers can be terminated by pulling the EOP input to low level. Both of these actions are called terminal count (TC). Hold RequestHRQ Output HRQ is active-high signal used as an output of hold request to the CPU for system data bus control purposes. After HRQ has become active, at least one clock cycle is required before HLDA becomes active. Address EnableAEN Output AEN is active-high ouput signal used to indicate that output signals sent from the MSM82C37B-5 to the system are valid. And in addition to enabling external latch to hold the eight higher order bits of the transfer address, this signal is also used to disable other system bus buffers. DMA Acknowledge 0 - 3 Channels DACK 0 - DACK3 Output DACK is output signals used to indicate that DMA transfer to peripheral devices has been permitted. (Available in each channel.) Although these pins are switched to active-low when reset, they can be programmed to become active-high. Address 0 - 3 A0 - A3 Input/Output A0 - A3 is bidirectional three-state signals used as input signals for specifying the MSM82C37B-5 internal register to be accessed by the CPU during idle cycles, and as an output the four lower order bits of the transfer address during active cycles. Address 4 - 7A 4 - A7 Output A4 - A7 is three-state signals used as an output the four higher order bits of the transfer address during active cycles. Note that there is no DACK output signal during memory-memory transfers. When internal or external EOP is generated, the MSM82C37B-5 terminates the transfer and resets the DMA request. When the EOP pin is not used, it is necessary to hold the pin at high level by pull-up resistor to prevent the input of an EOP by error. Also note that the EOP function cannot be satisfied in cascade mode. Memory ReadMEMR Output MEMR is active-low three-state output signal used as a control signal in reading data from memory during read transfers and memory-memory transfers. Memory WriteMEMW Output MEMW is active-low three-state output signal used as a control signal in writing data into memory during write transfers and memory-memory transfers. Address StrobeADSTB Output ADSTB is active-high signal used to strobe the eight higher order bits of the transfer address by external latch. PIN FUNCTIONS (continued)

¡ Semiconductor MSM82C37B-5RS/GS/VJS Internal/ external DMA Request RESET SI Y HLDA Y Memory-Memory Transfer External EOP N Compressed Timing N VerifyY READY Y Internal/ External EOP N Single Transfer N HLDA Y Demand Transfer N Carry or Borrow Y N N Y N EOP F/F Setting N SWN Y N External DMA Request Y Y Y S11 S12 External EOP N READY EOP F/F Setting SWN S13 Y S14 S21 S22 External EOP N READY EOP F/F Setting SWN S23 S24 Y Internal/ External EOP N HLDAY Y Note: Y … Yes (Active) N … No (Inactive) Y Y Y Y NN N Figure 1 DMA Operation State Transition Diagram

¡ Semiconductor MSM82C37B-5RS/GS/VJS OUTLINE OF FUNCTIONS The MSM82C37B-5 consists of five blocks = three logic sections, an internal register section, and a counter section. The logic sections include a timing control block where the internal timing and external control signals are generated, a command control block where each instruction from the CPU is decoded, and a priority decision block where the order of DMA channel priority is determined. The purpose of the internal register section is to hold internal states and instructions from the CPU, while the counter section computes addresses and word counts. DESCRIPTION OF OPERATIONS The MSM82C37B-5 operates in two cycles (called the idle and active cycles) which are divided into independent states. Each state is commenced by a clock falling edge and continues for a single clock cycle. The transition from one state to the next in DMA operations is outlined in Figure 1. Idle Cycle The idle cycle is entered from the Sl state when there is no valid DMA request on any MSM82C37B-5 channel. During this cycle, DREQ and CS inputs are monitored during each cycle. When a valid DMA request is then received, an active cycle is commenced. And if the HLDA and CS inputs are at low level, a programming state is started with MSM82C37B-5 reading or writing executed by IOR or IOW. Programming details are described later. Active Cycle If a DMA request is received in an unmasked channel while the MSM82C37B-5 is in idle cycle, or if a software DREQ is generated, the HRQ is changed to high level to commence an active cycle. The initial state of an active cycle is the S 0 state which is repeated until the HLDA input from the CPU is changed to high level. (But because of internal operational reasons, a minimum of one clock cycle is required for the HLDA is be changed to high level by the CPU after the HRQ has become high level. That is, the S 0 state must be repeated at least twice.) After the HLDA has been changed to high level, the S 0 state proceeds to operational states S1 thru S4 during I/O-memory transfers, or to operational states S 11 thru S 14 and S 21 thru S 24 during memory-memory transfers. If the memory or I/O device cannot be accessed within the normal timing, an SW state (wait state) can be inserted by a READY input to extend the timing.

¡ Semiconductor MSM82C37B-5RS/GS/VJS DESCRIPTION OF TRANSFER TYPES MSM82C37B-5 transfers between an I/O and memory devices, or transfers between memory devices. The three types of transfers between I/O and memory devices are read, write, and verify. I/O-Memory Transfers The operational states during an I/O-memory transfer are S 1, S2, S3, and S4. In the S1 state, an AEN output is changed to high level to indicate that the control signal from the MSM82C37B-5 is valid. The eight lower order bits of the transfer address are obtained from A 0 thru A7, and the eight higher order bits are obtained from DB0 thru DB7. The ADSTB output is changed to high level at this time to set the eight higher order bits in an external address latch, and the DACK output is made active for the channel where the DMA request is acknowledged. Where there is no change in the eight higher bit transfer address during demand and block mode transfers, however, the S 1 state is omitted. In the S2 state, the IOR or MEMR output is changed to low level. In the S 3 state, IOW or MEMW is changed to low level. Where compressed timing is used, however, the S3 state is omitted. The S2 and S3 states are I/O or memory input/output timing control states. In the S4 state, IOR, IOW, MEMR, and MEMW are changed to high level, and the word count register is decremented by 1 while the address register is incremented (or decremented) by 1. This completes the DMA transfer of one word. Note that in I/O-memory transfers, data is transferred directly without being taken in by the MSM82C37B-5. The differences in the three types of I/O-memory transfers are indicated below. Read Transfer Data is transferd from memory to the I/O device by changing MEMR and lOW to low level. MEMW and IOR are kept at high level during this time. Write Transfer Data is transferred from the I/O device to memory by changing MEMW and IOR to low level. MEMR and IOW are kept at high level during this time. Note that writing and reading in these write and read transfers are with respect to the memory. Verify Transfer Although verify transfers involve the same operations as write and read transfers (such as transfer address generation and EOP input responses),they are in fact pseudo transfers where all I/O and memory reading/writing control signals are kept inactive. READY inputs are disregarded in verify transfers.

¡ Semiconductor MSM82C37B-5RS/GS/VJS Memory-memory Transfer Memory-memory transfers are used to transfer data blocks from one memory area to another. Memory-memory transfers require a total of eight states to complete a single transfer four states 11 thru S14) for reading from memory, and four states (S21 thru S24) for writing into memory. These states are similar to I/O-memory transfer states, and are distinguished by using two-digit numbers. In memory-memory transfers, channel 0 is used for reading data from the source area, and channel 1 is used for writing data into the destination area. During the initial four states, data specified by the channel 0 address is read from the memory when MEMR is made active, and is taken in the MSM82C37B-5 temporary register. Then during the latter four states, the data in the temporary register is written in the address specified by channel 1. This completes the transfer of one byte of data. With channel 0 and channel 1 addresses subsequently incremented (or decremented) by 1, and channel 0, 1 word count decremented by 1, this operation is repeated. The transfer is terminated when the word count reaches FFFF(H) from 0000(H), or when an EOP input is applied from an external source. Note that there is no DACK output signal during this transfer. The following preparations in programming are requiring to enable memory-memory transfers to be started. Command Register Setting Memory-memory transfers are enabled by setting bit 0. Channel 0 address can be held for all transfers by setting bit 1. This setting can be used to enable 1-word contents of the source area to be written into the entire destination area. Mode Register Setting The transfer type destination is disregarded in channels 0 and 1. Memory-memory transfers are always executed in block transfer mode. Request Register Setting Memory-memory transfers are started by setting the channel 0 request bit. Mask Register Setting Mask bits for all channels are set to prevent selection of any other channel apart from channel Word Count Register Setting The channel 1 word count is validated, while the channel 0 word count is disregarded. In order to autoinitialize both channels, it is necessary to write the same values into both word count registers.

¡ Semiconductor MSM82C37B-5RS/GS/VJS DESCRIPTION OF OPERATION MODES Single Transfer Mode In single transfer mode, only one word is transferred, and the addresses are incremented (or decremented) by 1 while the word count is decremented by 1. The HRQ is then changed to low level to return the bus control to the CPU. If DREQ remains active after completion of a transfer, the HRQ is changed to low level. After the HLDA is changed to low level by the CPU, and then changes the HRQ back to high level to commence a fresh DMA cycle. For this reason, a machine cycle can be inserted between DMA cycles by the CPU. Block Transfer Mode Once a DMA transfer is started in block mode, the transfer is continued until terminal count (TC) status is reached. If DREQ remains active until DACK becomes active, the DMA transfer is continued even if DREQ becomes inactive. Demand Transfer Mode The DMA transfer is continued in demand transfer mode until DREQ is no longer active, or until TC status is reached. During a DMA transfer, intermediate address and word count values are held in the current address and current word count registers. Consequently, if the DMA transfer is suspended as a result of DREQ becoming inactive before TC status is reached, and the DREQ for that channel is then made active again, the suspended DMA transfer is resumed.

¡ Semiconductor MSM82C37B-5RS/GS/VJS Cascade Transfer Mode When DMA transfers involving more than four channels are required, connecting a multiple number of MSM82C37A-5 devices in a cascade connection (see Figure 2 ) enables a simple system extension. This mode is set by setting the first stage MSM82C37B-5 channel to cascade mode. The DREQ and DACK lines for the first stage MSM82C37B-5 channel set to cascade mode are connected to the HRQ and HLDA lines of the respective MSM82C37B-5 devices in the second stage. The first stage MSM82C37B-5 DACK signal must be set to active-high, and the DREQ signal to active-low. Since the first stage MSM82C37B-5 is only used functionally in determining the order of priority of each channel when cascade mode is set, only DREQ and DACK are used–all other inputs are disregarded. And since the system may be hung up if the DMA transfer is activated by software DREQ, do not set a software DREQ for channels where cascade mode has been set. In addition to the dual stage cascade connection shown in Figure 2, triple stage cascade connections are possible with the second stage also set to cascade mode. CPU HRQ DREQ DACK HLDA DREQ DACK HRQ HLDA DREQ 0 - 3 DACK 0 - 3 I/O I/O HRQ HLDA DREQ 0 - 3 DACK 0 - 3 Stage 1 MSM82C37B-5 Stage 2 MSM82C37B-5 Figure 2 MSM82C37B-5 Cascade Connection System Autoinitialize Mode Setting bit 4 of the mode register enables autoinitialization of that channel. Following TC generation, autoinitialize involves writing of the base address and the base word count register values in the respective current address and current word count registers. The same values as in the current registers are written in the base registers by the CPU, and are not changed during DMA transfers. When a channel has been set to autoinitialize, that channel may be used in a second transfer without involving the CPU and without the mask bit being reset after the TC generation. Priority Modes The MSM82C37B-5 makes use of two priority decision modes, and acknowledges the DMA channel of highest priority among the DMA requesting channels.

¡ Semiconductor MSM82C37B-5RS/GS/VJS Fixed Priority Mode In fixed priority mode, channel 0 has the highest priority, followed by channels 1, 2, and 3 in that order. Rotating Priority Mode In rotating priority mode, the order of priority is changed so that the channel where the current DMA transfer has been completed is given lowest priority. This is to prevent any one channel from monopolizing the system. The fixed priority is regained immediately after resetting. Service Terminated Channel — CH0 Priority Mode Fixed CH1Order of Priority for Next DMA CH2 CH3 Highest Lowest CH1 CH2 Rotating CH3 CH0 CH1 CH3 CH0 CH1 CH2 CH3 CH2 CH3 CH0 CH1 CH2 CH0 CH1 CH2 CH3 CH0 Table 1 MSM82C37B-5 Priority Decision Modes Compressed Timing Setting the MSM82C37B-5 to compressed timing mode enables the S3 state used in extension of the read pulse access time to be omitted (if permitted by system structure) for two or three clock cycle DMA transfers. If the S 3 state is omitted, the read pulse width becomes the same as the write pulse width with the address updated in S2 and the read or write operation executed in S4. This mode is disregarded if the transfer is a memory-memory transfer, transfer. Extended Writing When this mode is set, the IOW or MEMW signal which normally appears during the S3 state is obtained during the S 2 state, thereby extending the write pulse width. The purpose of this extended write pulse is to enable the system to accomodate memories and I/O devices where the access time is slower. Although the pulse width can also be extended by using READY, that involves the insertion of a SW state to increase the number of states.

¡ Semiconductor MSM82C37B-5RS/GS/VJS DESCRIPTION OF INTERNAL REGISTERS Current Address Register Each channel is equipped with a 16-bit long current address register where the transfer address is held during DMA transfers. The register value is incremented (or decremented) in each DMA cycle. Although this register is 16 bits long, the CPU is accessed by the MSM82C37B-5 eight bits at a time, therefore necessitating two successive 8-bit (lower and higher order bits) reading or writing operations using internal first/last flip-flops. When autoinitialize has been set, the register is automatically initialized to the original value after TC. Current Word Count Register Each channel is also equipped with a 16 bit-long current word count register where the transfer count is held during DMA transfers. The register value is decremented in each DMA cycle. When the word count value reaches FFFF(H) from 0000(H), a TC is generated. Therefore, a word count value which is one less than the actual number of transfers must be set. Since this register is also 16 bits long, it is accessed by first/last flip-flops control in the same way as the address register. And if autoinitialize has been set, the register is automatically initialized to the original value after TC. Base Address Register and Base Word Count Register Each channel is equipped with a 16-bit long base address register and base word count register where the initial value of each current register is held. The same values are written in each base register and the current register by the CPU. The contents of the current register can be made ready by the CPU, but the content of the base register cannot be read.

¡ Semiconductor MSM82C37B-5RS/GS/VJS Command Register This 8-bit write-only register prescribes DMA operations for all MSM82C37B-5 channels. An outline of all bits is given in Figure 3. When the controller is disabled by setting D B2, there is no HRQ output even if DMA request is active. DREQ and DACK signals may be active high or active low by setting D B 6 and DB7. DB7 0: Memory-Memory Transfer Disabled 1: Memory-Memory Transfer Enabled DB6 DB5 DB4 DB3 DB2 DB1 DB0 0: Channel 0 Address Hold Disabled 1: Channel 0 Address Hold Enabled 0: Controller Enabled 1: Controller Disabled 0: Normal Timing 1: Compressed Timing 0: Fixed Priority 1: Rotating Priority 0: Normal Write Pulse Width 1: Extended Write Pulse Width 0: DREQ Sense Active "H" 1: DREQ Sense Active "L" 0: DACK Sense Active "L" 1: DACK Sense Active "H" (Invalid when DB0 = "0") (Invalid when DB0 = "1") Figure 3 Command Register

¡ Semiconductor MSM82C37B-5RS/GS/VJS Mask Register This register is used in disabling and enabling of DMA transfers in each channel. Each channel includes a corresponding mask bit in the mask register, and each bit is set when the TC is reached if not in autoinitialize mode. This mask register can be set in two different ways. The method for setting/resetting the register for each channel is outlined in Figure 6(a), while the method for setting/resetting the register for all channels at once is outlined in Figure 6(b). DB7 00: Channel 0 Selected 01: Channel 1 Selected 10: Channel 2 Selected 11: Channel 3 Selected DB6 DB5 DB4 DB3 DB2 DB1 DB0 0: Mask Bit Cleared 1: Mask Bit Set Not Used (a) Single Mask Register (Setting/Resetting for Each Channel) DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Not Used (b) All Mask Register (Setting/Resetting of All Channels at Once) 0: Channel 0 Mask Bit Cleared 1: Channel 0 Mask Bit Set 0: Channel 1 Mask Bit Cleared 1: Channel 1 Mask Bit Set 0: Channel 2 Mask Bit Cleared 1: Channel 2 Mask Bit Set 0: Channel 3 Mask Bit Cleared 1: Channel 3 Mask Bit Set Figure 6 Mask Register

¡ Semiconductor MSM82C37B-5RS/GS/VJS Clear First/Last Flip-Flop 16-bit address and word count registers are read or written in two consecutive operations involving eight bits each (higher and lower order bits) under data bus port control. The fact that the lower order bits are accessed first by the MSM82C37B-5, followed by accessing of the higher order bits, is discerned by the internal first/last flip-flop. This command resets the first/last flip-flop with the eight lower order bits being accessed immediately after execution. Master Clear The same operation as when the hardware RESET input is applied. Thus command clears the contents of the command, status (four lower order bits), request, and temporary registers, also clears the first/last flip-flop, and sets the mask register. This command is followed by an idle cycle. Clear Mask Register When this command is executed, the mask bits for all channels are cleared to enable reception of DMA transfers.

¡ Semiconductor MSM82C37B-5RS/GS/VJS PROGRAMMING The MSM82C37B-5 is switched to programming status when the HLDA input and CS are both at low level. In this state, IOR is changed to low level with IOW held at high level to enable reading by the CPU, or else IOW is changed to low level while IOR is held at high level to enable writing by the CPU. A list of command codes for reading from the MSM82C37B-5 is given in Table 2, and a list of command codes for writing in the MSM82C37B-5 is given Table 3. Note: If a DMA transfer request is received from an I/O device during MSM82C37B- 5 programming, that DMA transfer may be commenced to prevent proper programming. To prevent this interference, the DMA channel must be masked, or the controller disabled by the command register, or the system set to as to prevent DREQ becoming active during the programming. CS IOR A3 Read Out Data Other Combinations Internal First/Last Flip/Flop

• /CR
• /CR
• /CR Channel 0 Channel 1 Channel 2 Channel 3 Status Register Temporary Register Output Data Invalid Current Address Register Current Word Count Register Current Address Register Current Word Count Register Current Address Register Current Word Count Register Current Word Count Register Current Address Register

8 Lower Order Bits

8 Higher Order Bits

Table 2 List of MSM82C37B-5 Read Commands

¡ Semiconductor MSM82C37B-5RS/GS/VJS CS IOW A3 Written Data Internal First/Last Flip-Flop Channel 0 Channel 1 Channel 2 Channel 3 Command Register Request Register Single Mask Register Mode Register Clear First/Last Flip-Flop (Software Command) Master Clear (Software Command) Clear Mask Register (Software Command) All Mask Register Current and Base Address Registers Current and Base Word Count Registers Current and Base Address Registers Current and Base Word Count Registers Current and Base Address Registers Current and Base Word Count Registers Current and Base Word Count Registers Current and Base Address Registers Table 3 List of MSM82C37B-5 Write Commands

¡ Semiconductor MSM82C37B-5RS/GS/VJS NOTICE ON REPLACING LOW-SPEED DEVICES WITH HIGH-SPEED DEVICES The conventional low speed devices are replaced by high-speed devices as shown below. When you want to replace your low speed devices with high-speed devices, read the replacement notice given on the next pages. High-speed device (New) Low-speed device (Old) Remarks M80C85AH M80C85A/M80C85A-2 8-bit MPU M80C86A-10 M80C86A/M80C86A-2 16-bit MPU M80C88A-10 M80C88A/M80C88A-2 8-bit MPU M82C84A-2 M82C84A/M82C84A-5 Clock generator M81C55-5 M81C55 RAM, I/O, timer M82C37B-5 M82C37A/M82C37A-5 DMA controller M82C51A-2 M82C51A USART M82C53-2 M82C53-5 Timer M82C55A-2 M82C55A-5 PPI

¡ Semiconductor MSM82C37B-5RS/GS/VJS Differences between MSM82C37A-5 and MSM82C37B-5 1) Manufacturing Process These devices use a 3 m Si-CMOS process technology and have the same chip size. 2) Function These devices have the same logics except for changes in AC characteristics listed in (3-2). 3) Electrical Characteristics 3-1) DC Characteristics These devices have the same DC characteristics. 3-2) AC Characteristics As shown above, the MSM82C37A-5 cannot satisfy the clock low time of 68 ns (at automatic initialization). On the other hand, the MSM82C37B-5 can satisfy the clock low time of 68 ns in any operation status. As for the other characteristics, both the MSM82C37A-5 and the MSM82C37B-5 are identical. 4) Package The MSM82C37A-5 employed a PLCC package having OKI's original pin layout, which is not compatible to AMD's PLCC products which has been commercialized before OKI's products. To meet overseas customers needs, OKI has developed AMD-compatible PLCC productsMSM82C37B-VJS. The OKI's DIP and FLAT package are identical to those of AMD. Parameter Symbol MSM82C37A-5 MSM82C37B-5 100 ns minimum 68 ns minimumtCL Clock Low Time (Other than the above) tCL 68 ns minimum 68 ns minimum Clock Low Time (at automatic initialization)

¡ Semiconductor MSM82C37B-5RS/GS/VJS (Unit : mm) PACKAGE DIMENSIONS DIP40-P-600-2.54 Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 6.10 TYP.

¡ Semiconductor MSM82C37B-5RS/GS/VJS (Unit : mm) Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). QFJ44-P-S650-1.27 Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin Cu alloy Solder plating 5 mm or more 2.00 TYP. Mirror finish

¡ Semiconductor MSM82C37B-5RS/GS/VJS (Unit : mm) Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.41 TYP. QFP44-P-910-0.80-2K Mirror finish

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