82C288-10

82C288 AMD | Alldatasheet

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FS DISTINCTIVE CHARACTERISTICS 8 ® Provides commands and control for local and sys: ® Control drivers with 16 mA lot. and three-state tom bus command drivers with 32 mA lo. © Offers wide flexibility in system configurations © Single +5 V supply © Flexible command timing * Low power CMOS operation: © Optional Multious* compatible timing —locop = 26 mA Maximum GENERAL DESCRIPTION The 826288 Bus Controller is a 20-pin CMOS component and I/O devices. The data bus is controlled with separate for use in iAPX 286 microsystems. The bus controller data enable and direction control signals. Provides command and contro! outputs with flexible timing ‘Two modes of of . peration are possible via a strapping option: options. Separate command outputs are used for memory a tius-compatible bus cycles and high-speed bus cycles. BLOCK DIAGRAM THREE-STATE COMMAND status OUTPUTS ST] status |_| i 5H] oecoven Commano Fre TORE wild eet befowe LY AWTE STATE LK Sureorg, CONTROL INPUTS url CEN/AEN: 1 t OTA CONTROL l CONTROL CENL |] INPUT outpuT |] DEN cuoLY—p Loaic Logie Pye Aue a MCE MB ‘80004001 “mentees orn

3.272 Issue Date: Apeit 1987

conncoTion pinanam Logic SYMBOL 8 Top View 2 DIPs READY MCE cK ALE! q D vec Pia eu C] Ds Z> awe Ms sq 1D wis owe oMoLY wee C] Donk me ae O 1 ew en en RK CEN/I we C] 1) cenaen DEN Mi ewow C] D cen ova ome C] D wm so02600 are | Dre GND = System Ground: 0 V Voc = Supply Power: +5 V ono CJ D ewe coo0s623 Note: Pin 1 is marked for orientation. 3-273

3 Commodity Products

AMD commodity products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: A. Temperature Range C. Device Number D. Speed Option a2 - Le D. SPEED OPTION =e= 8 MHz -10= 10 Miz ©. DEVICE NUMBER/DESCRIPTION 820268 GMOS Bus Controller for PX 286 Processors B. PACKAGE TYPE P= 20-Pin Plastic DIP (PD 020) = 20° Coramic DIP (CD 020) ‘A. TEMPERATURE RANGE Blank = Commercial (0 to + 70°C) Valid Combinations [___vaua Combinations + Valid Combinations list configurations planned to be Nal Combinations supported in volume for this device. Consult the local AMD [oe =~ eee sales office to confirm availability of specific valid [s2cze810_ Combinations, to check on newly released valid combinations, and to obtain additional data on AMD's standard military grade products. 3-274

READY Ready (Input, Active LOW) MWIC = Memory Write Command (Output, Active 3 READY is an active- LOW input that indicates the end of the Low) current bus cycle. The 62284 drives READY LOW during MWTC is an active LOW-command output that instructs a RESET to force the 82C288 into the Idle state. Multibus memory device to read the data on the data bus. The MB mode requires at least one wait state to allow the command and CMDLY inputs control when this output becomes ‘outputs to become active. Setup and hold times must be active. READY controls when it becomes inactive. met for proper operation. GND System Ground CLK System Clock (Input) ‘System Ground: 0 V. CLK provides the basic timing control for the 826268. Its 0 Wie Command frequency is twice the processor's internal clock frequency. owe th mmand (Output, Active LOW) The fall is it i TOWT is an active-LOW command output that instructs an I/ 6 falling edge of this input signal establishes when inputs © devios tc reed the dole on the dita bus, The MB and are sampled and command and control outputs change. lovice to 1 fon the data bus. CMDLY inputs control when this output becomes active. as oe Cycle Status input, Active Low Je and READY controls when it becomes inactive. ‘and Si are active-LOW inputs that start a bus cycle and,

170 Read Command

along with M/TO, define the type of bus cycle. (See Table 1 TORE mmand (Output, Active LOW) for iAPX 286 bus cycle status definitions.) A bus cycle is TORT is an active-LOW command output that instructs an started when either ST or 50 is sampled LOW at the falling W/O device to place data onto the data bus. The MB and ‘edge of CLK. These inputs have internal pull-up resistors to ey inputs control when this output becomes active. hold them HIGH when not being driven. Setup and hold controls when it becomes inactive. times must be met for proper operation. INTA _ Interrupt Acknowledge (Output, Active LOW) MCE Master Cascade Enable (Output, Active HIGH) INTA is an active-LOW contro! output that tells an MCE signals that a cascade address from a master 8259A interrupting device that its interrupt request is being Interrupt Controller may be placed onto the CPU address acknowledged. The MB and CMOLY inputs control when bus for latching by the address latches under ALE control. this output becomes active. READY controls when it ‘The CPU's address bus may then be used to broadcast the becomes inactive. cascade address to slave interrupt controllers so only one = CENL_-_— Common Enable Latched (Input, Active HIGH) of them will respond to the interrupt acknowledge cycle. CENL is a select signal which enables the bus controller to This controle output is ban Mile is or ae sg respond to the current bus cycle being initiated. CENL is an interrupt acknowledge cycles and is not af any active-HIGH input latched internally at the end of each ts ‘control input. Using MCE to enable cascade address drivers ‘cycle. CENL is used to select the appropriate bus controller oa eda or woe save the cascade address on the for each bus cycle in a system where the CPU has more ing than one bus it can use. This input may be connected to ALE Address Latch Enable (Output, Active HIGH) Voc to select this 820288 for all transfers. No control inputs ALE is an active-HIGH output that controls the address affect CENL. Setup and hold times must be met for proper latches used to hold an address stable during a bus cycle. ‘operation. in is not issued fort the halt bus cycle and is not affected. ~~ CEN/AEN Common Enable/Address Enable (Input, ‘any control inpt Active HIGH/Active LOW) MB Multibus Mode Select (Input, Active HIGH) CEN/KEN controls the command and DEN outputs of the (input ) MB determines the timing of the command and contro! See a Reid tn input may be asynchronous Me aed outputs. When HIGH, the bus controller operates with times are given to assure a guar Multibus-compatible timings. When LOW, the bus controller response to synchronous inputs. This input may be optimizes the command and control output timing for short connected to Voc or GND. bus cycles. The function of the CEN/AEN input pin is When MB is HIGH, this pin has the AEN function. AEN is an selected by this pin, MB is intended to be a strapping option x vs and not dynamically changed; it may be connected to Voc active-LOW input which indicates that the CPU has been or GND. ' granted use of a shared bus and the bus controller - command outputs may exit three-state OFF and become CMDLY Command Delay (Input, Active HIGH) inactive (HIGH). AEN HIGH indicates that the CPU does not CMDLY is an active-HIGH input that allows the delaying of a have control of the shared bus and forces the command command start. if sampled HIGH, the command output is outputs into three-state OFF and DEN inactive (LOW). AEN not activated and CMDLY is again sampled at the next CLK would normally be controlled by an 82289 bus arbiter which cycle. When sampled LOW, the selected command is activates AEN when that arbiter owns the bus to which the ‘enabled. If READY is detected LOW before the command bus controller is attached. el noconnandwes ae soup ed Rol tne ei When MB is LOW, this pin has the CEN function. CEN is an even if no command was issued. Setup af imes musi is LOW, this pin be satisfied for proper operation. This input may be unlatched active-HIGH input which allows the bus controller connected to GND if no delays are required before starting a to activate its command and DEN outputs. With MB LOW, ‘command. This input has no effect on contro! outputs. (CEN LOW forces the command and DEN outputs inactive WRDC Memory Head Command (Output, Active but does not tristate them. Low) DEN Data Enable (Output, Active HIGH) MRDC is an active-LOW contro! output that instructs the DEN determines when data transceivers connected to the memory device to place data onto the data bus. The MB local data bus should be enabled. DEN is an active-HIGH and CMDLY inputs control when this output becomes control. DEN is delayed for write cycles in the Multibus active. READY controls when it becomes inactive. mode. 3-275

8 Active LOW) Active LOW)

read bus cycle. DEN is always inactive when DT/R changes for proper operation. Fi is not affected by any of the control inputs. ine sale ev. TABLE 1. IAPX 286 BUS CYCLE STATUS enable input (CENL). An address decoder can determine 1 0 | 0 | Halt or shutdown external bus arbiter such as the 62289. FUNCTIONAL DESCRIPTION enabling other drivers onto the same bus. ~ and thereby drive the 62C288 status inputs. command. bus master’s internal clock. Figure 1. CLK Relationship to the Processor Clock and Bus T-States Idle (Tp, Status (Ts), and Command (Tc). Each bus state is between masters, the bus remains in the 7} state. internal CPU processor clock phases.

Multibus timing is used. in Multibus mode, the 820288 delays Tore sert the appropriate command output for the bus cycle. ‘encoded in the M/IO, 51, and 56 inputs. Different command READ WU CYCLE. bus cycle is started via Si and 50. Figure 5. Idle-Write-Idle Bus Cycles with MB=0

inputs of the bus controllers select which bus controller is to into three-state OFF (see Figure 10). The LOW-to-HIGH 8 perform the bus cycle. An address decoder determines which transition of AEN should only occur during T; or Ts bus states. bus to use for each bus cycle. The 82C288 connected to the __ 3 shared Multibus must be selected by CENL and be given Tho HIGH-to-.0W transition of AEN signals that the bus access to the Multibus by AEN before it will begin a Multibus controller may now drive the shared bus command signals. operation Since a bus cycle may be active or be in the process of starting, AEN can become active during any T-state. AEN CENL must be sampled HIGH at the end of the Ts bus state LOW immediately allows DEN to go to the appropriate state. (S00 Switching Waveforms) to enable the bus controller 0 Three CLK edges later, the command outputs will go active activate its command and control outputs. If sampled LOW. —_(g9@ Switching Waveforms). The Multibus requires this delay the commands and DEN will not go active and DT/A will for the address and data to be valid on the bus before the remain HIGH, The bus controller will ignore the CMDLY, CEN, commands become active. and READY inputs until another bus cycle is started via ST and ‘SO. Since an address decoder is commonly used to identity When MB = 0, CEN/AEN becomes CEN. CEN is an asynchro- which bus is required for each bus cycle, CENL is latched to nous input which immediately affects the command and DEN avoid the need for latching its input. outputs. When CEN makes a HIGH-to-LOW transition, the The CENL input can affect the DEN control output. When _ofMimands and DEN are immediately forced inactive. When MB ~0, DEN normally becomes active during Phase 2 of Tsin CEN makes a LOW-to-HIGH transition, the commands and write bus cycles. This transition occurs before CENL is OEN outputs immediately go to the appropriate state (soo sampled. If CENL is sampled LOW, the DEN output will be Switcing Aneel eA DY must st poco ae forced LOW during To as shown in the timing waveforms, {ornate ¢ A AN ar When MB = 1, CEN/AEN becomes AEN. AEN controls when the bus controller command outputs enter and exit three-state Some memory or 1/0 systems may require more address or OFF. AEN is intended to be driven by a bus arbiter, like the write data set-up time to command active than provided by the 82289, which assures only one bus controller is driving the basic command output timing. To provide flexible command shared bus at any time. When AEN makes a LOW-to-HIGH timing, the CMDLY input can delay the activation of command ‘transition, the command outputs immediately enter three-state outputs. The CMDLY input must be sampled LOW to activate ‘OFF and DEN is forced inactive. An inactive DEN should force the command outputs. CMDLY does not affect the control the local data transceivers connected to the shared data bus outputs ALE, MCE, DEN, and DT/A. 9-281

Figure 10. System Use of AEN and CENL impled 1H, the ‘output is not activ , . aoe, we ro earior than shown in Figures 7 and 8. via the general cases. Special cases are shown when needed. Command to be issued. In this case no commands are issued . same manner as if a command had been issued. particular mode, first look for a special case in the waveforms. the same or related function in another mode.

ABSOLUTE MAXIMUM RATINGS OPERATING RANGES 8 iting ranges define those limits between which the Stresses above those listed under ABSOLUTE MAXIMUM P23 RATINGS may cause permanent dovice failure. Functionality “unctonalty of the device is guaranteed. at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. DC CHARACTERISTICS over operating ranges unless otherwise specified Ser ae | ome [ml [| [vic [rot LOW Votago es Pe [vin | np HIGH Vottge 2 oes POV | [Wc [eux inet Low votage Ps Te [_Vinc | CLK nowt HIGH Votage | 8 oo TV | Output LOW Voltage = 32 mA (Note 1) v vou Gernmand Quota E283 MA Nee M Output HIGH Vonage =-5 mA (Noto 1) 24 v von Senet Supe RICE tate 2 | 28 y [te input Current (88, ST_and M/IG inputs) [easy os ma [tw | Input Leakage Guront (AN Other inpuis) | VS VSVoo [fsa [to | Output Leakage Curent | A VS Vour<Voo Tf s10 ua Pe fewer EE eh Be Sen" ewe | [Ta CAPACITANCE (Ta = 25°C, Voc = GND =0 V, Vin=+5 V or GND) [Gerke [CLK input Capacitance Tent Mee Teor [ci _| Input Capactance Tem Mer [Go| Output Capacitance eee 20 or Notes: 1. Command Outputs are INTA, IORC, IOWC, WDC, WAC. 2. Controt Outputs are DT/R, DEN, ALE and MCE. SWITCHING TEST CIRCUIT KEY TO SWITCHING WAVEFORMS waveron—wwursouTPuTS DEVICE ouTPuT | aust WILL BE er Baker a wees “ye003670 ONT CARE, CHANGING, cere Ha seer Se: neat S000070 See Secton © fr Thermal Characteristics floraion 3-283

$ [ SWITCHING CHARACTERISTICS over operating ranges unless otherwise specified 8 Switching timings are referenced to 0.8 V and 2.0 V points of signals g as illustrated in data sheet waveforms, unless otherwise noted. parameter ren |.0202808 (2 wha) [6207660 (10 min i ee A SO a A [~s[aKtowtme | tts soe ees [4 [oKnrsetm | Stove sev Pt Te | [6 [oxraitm | evo [Te Te | [6 | MiG and Staus Seuptime | Te Pt [7] MiB end Status Hod time | Pt ne [6 [cen sewptime TC a [9 [orn wodtime TT [10 | READY Soup time] | es [oa [READY Hog Time ase [2 [ewory soup time Pe [13 | owolyHos time] Te [14 [AEN Soup Time | Notes) ToT Os | [35 AENHoid Time | Notes) TT [16 | "ALE, MCE Active Delay vom CK | (Note a) Ts TPs ens [17 | ALE, MGE inactive Dotay trom GK [Noto ay) PTs Tene [18 | DEN wi) inactive wom GENL [Note a) Pas an [18 | OVA LOW trom cx Noto a) Ps es [20 | DEN (Read) Active tom oT | Note a) Ts Tas Ps as | [21 | DEN (Read) Inactive Delay tom UK [Note a) Peas sane [22 | D/A HIGH trom DEN Inactive | owe a) Ts Ts Ts ons [23 | DEN Wite) Active Delay from GLK [Nowe a) [TPs | [24 | DEN (Wrte) inactive Delay from CLK [Note a) fsa [25] DEN inactive trom GEN Note yas [26 | DEN Aatve fom Gen | Note gy ge Le [meng me (when CEN = LOW) [26 | DEN Ave tom AEN | Mote) TT Te [20 [CHO Active Delay trom cK | Notes) Ts Ts Tasos [30 | CWO inactve Delay tom cx | Notes) Ts Tas Ts ao [31 | CWD inactive trom CEN | Notes) Pas as [32 | CMD Active wom CEN Notes) Ps Pas ns [_33__| OWD inactive Enable tromAEN | Notes) TT ars [34 | CWO Float Delay rom AEN | Noto) PT | [35 | MBSouptime | Ts [se [we nos tine Pe [ar [conned rack Gate tem we [ ews dP Cd | [se [Gonrand Foat toe ton ma=F_ | tow f | « || «| | [se [060 mace tone owe | [40 | DEN mace romws tL | Mowe) TT Te ‘4, Control output load: C, = 160 pF. 5. Command output load: C, = 300 pF. 6. Float condition occurs when output curent is less than ILo in magnitude. 3-284

'WF022480, AC Drive and Measurement Points — CLK input 4aov sav wey cux pur tov tov ous ‘texTur- WHOLO: UV IRN WOBROOOSRR OOOH ep coccoe Seen ONG Oe “ahatecanateeet Bence Si, Cacecooaterecen INPUT BERKS ‘Ss Borers: er ean LR POLOLOS easy toetar , AEEEEEEE REE eta Nese Raeateeeteerornennnnnnt te aed ence NS see SRK KK KK IK OUTPUT KRSM KS Sh resesecocereneeonenoneneintan Pm ony pearatetetatatecetatetetetatstatenatatate CA wroz2460 AC Setup, Hold, and Delay Time Measurement — General 3-285

§ SWITCHING WAVEFORMS (Cont'd.) © © ® TA AoAanr ox / we \\| J 5 . = OEN se 3)I@s)

SWITCHING WAVEFORMS (Cont'd.) 8 as _ © © eT Cor | Read Cycle Characteristics with MB =0 and cnet t— | |e emo WY AL | WLLL _ | 7° | [4 we FEBY WA) MMANKAS VILL 1) (Om) Write Cycle Characteristics With MB=0 AND CEN=1 ‘vo

t SWITCHING WAVEFORMS (Cont'd.) (co) [| | oT. os CEN Characteristics with MB =0 me +s + fee e | FO-1=1© AEN Characteristics with MB =1 _ Note 1: uN is an asynchronous input. AEN setup and hold time is specified to guarantee the response

SWITCHING WAVEFORMS (Cont'd.) 8 1% [te 1 te 1 te 1% 1 “ ae = wa ae ©) ® FLoaTINa @ ® ie = $ ae ® @ Ld ' * 1 hid ! pi 4 vs ' wa \\ / \\ ue $$$ (O) @-- > (6) omn ee > -@ en O71. =o Ss a ts i Te i a Te i ~ mpeceeee wean ” © +-® us wre --—_RoeTwa 8 @__ nome iO) ® on (OF wroz2470 MB Characteristics with AEN/CEN = HIGH Notes: 1, MB is an asynchronous input. MB setup and hold times specified to guarantee the response ‘shown in the waveforms. 2. If the setup time, tgs, is met two clock cycles will occur before CMD becomes active after the falling edge of MB. 3.289