8255A AMD | Alldatasheet

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Programmable Peripheral Interface iAPX86 Family MILITARY INFORMATION ra DISTINCTIVE CHARACTERISTICS © | © SMD/DESC qualified © 24 programmable I/O pins © Direct bit set/reset capability easing control application @ Completely TTL-compatible interface ‘© Fully compatible with the iAPX86 microprocessor family ‘© Reduces system package count © Improved timing characteristics © Improved DC driving capability GENERAL DESCRIPTION The 8255A is a general-purpose, programmable I/O device programmed to have eight lines of input or output. Of the designed for use with iAPX Family microprocessors. Ithas remaining four pins, three are used for handshaking and 24 1/0 pins which may be individually programmed in two _interrupt control signals. The third mode of operation (Mode groups of twelve, and used in three major modes of 2) is a bidirectional bus mode which uses eight lines for a ‘operation. In the first mode, each group of twelve 1/O pins __ bidirectional bus, and five lines, borrowing one from the may be programmed in sets of four and eight to be input or other group, for handshaking. output. In Mode 1, the second mode, each group may be BLOCK DIAGRAM =i-: OIL ‘SUPPLIES = Ko rere. ba BLORECTIONAL BUS Data “ 3 ‘enour KK) Pees Sues x Oo md ~1 WR—o} can ” n were congue “ o nN oMTRoL contnot KY ve KO, nor a] a—_I ‘810003600 ‘07912 8 70 3:54 Issue Dato: November_ 1967

Top View > patie pp, pa 2 39 Pas Pa Cys Pa Pao 37 Ppa, ws * WA acs 35 [J Reser ono C47 4 Fo, ace 2A, a Clo 2fo, pe, CJ 10 af; Pe in Ax Pcs C2 nf, pc, 13 28 Fo, Py C14 27 Eo, ec, C15 25 Vee PczC 6 25) PB; pe 47 24 Pa, PB (18 (23 |) PBs PB, 19 22 [2 PB, pe, Cl20 21F) PB; cD005401 Note: Pin 1 is marked for orientation. MILITARY ORDERING INFORMATION Standard Military Drawing (SMD)/DESC Products AMD Products for Aerospace and Defense applications are available in several packages and operating ranges. Standard Miltary Drawing (SMD)/DESC products are fully compliant with MIL-STD-883C requirements. The order number (Valid Combination) for SMD/DESC products is formed by a combination of: a. Military Drawing Part Number b. Device Type ¢. Case Outline d. Lead Finish 4 1 x L 4. LEAD FINISH X= Any Lead Finish Acceptable ¢. CASE OUTLINE = 40-Fin Ceramic DIP (CO 040) 'b. MILITARY DEVICE TYPE 01 = 2.5 MHz (8255A) 02 = 3.3 MHz (8255A-5) ‘&, MILITARY DRAWING NO./DESCRIPTION 5962-87570 Programmable Peripheral Intertace Valid Combinations Valid Combinations list configurations planned to be ‘supported in volume for this device. Consult the local AMD combinations or to check for newly released valid combinations. Group A Tests Group A tests consist of Subgroups 3-55,

8 MILITARY ORDERING INFORMATION (Cont'd.)

3 APL Products

AMD products for Aerospace and Defense applications are available in several packages and operating ranges. APL (Approved Products List) products are fully compliant with MIL-STD-883C requirements. The order number (Valid Combination) for APL products is formed by a combination of: a. Device Number b. Speed Option (if applicable) ¢. Device Class d. Package Type e. Lead Finish ~ l Q — LEAD FINISH A= Hot Solder Dip 4. PACKAGE TYPE Q = 40-Pin Ceramic DIP (CD 040) ©. DEVICE CLASS 7B = Cass 8 b. SPEED OPTION Blank = 2.5 MHz ~5=3.3 MHz ‘8. DEVICE NUMBER/DESCRIPTION 8255A Programmable Peripheral interface Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations or to check for newly released valid Valid Combinations combinations. Lezssas | Group A tests consist of Subgroups 2.56

ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Fy All Signal Voltages Supply Voltage (VCC) -o....ssccscecesesecseeee SV 10% Stresses above those listed under ABSOLUTE MAXIMUM —— unctionality of the device is guaranteed. RATINGS may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute ‘maximum ratings for extended periods may affect device reliability. DC CHARACTERISTICS over operating range (for SMD/DESC and APL Products, Group A, Subgroups 1, 2, 3 are tested unless otherwise noted) Parameter Description Test Conditions | vat [ pt tow Votage "Veena vd 0 os | net [wut igh vatage eres 0a ae | vous) [ oupt tow Votage Gata Bos) Figg =25 WA Vog=S8V | ug [08 | You eR) | Outnit Low Vettge (Perpheral Por) [Tou= 1.7 mA, Voo=55V a ga fy pf oes Ouiput High Voltage (Data Bus) | 1on==400 HA voo= esti Mer Wage Ty | _VordPER)[ Outpa High Vottage (Panpheral Pom)_| ion = 200qgd Bbc = i pes cerry 20 Parameter Parameter Symbol Description Test Conditions Typ. [__cwtt [input Capactance fie=t we a |__Gvott_ [V0 Capacitance | Unnneasured pine viued GND |_| | as | “Guaranteed by design; not tested. tGroup A, Subgroups 9, 10, 11 only are tested. tTNot included in Group A tests. Notes: 1. Available on any 8 pins from Port B and C. 2. loc test conditions: the supply current is measured with loaded outputs while running AC pattems, SWITCHING TEST CIRCUIT Ton098s0 ‘This test circuit is the dynamic load of a Teradyne J941, SWITCHING TEST WAVEFORM Py 0 res ) ioe. ous wro06951 AC testing: Inputs are driven at 2.4 V for a logic "1" and 0.45 V for a logic "0." Timing measurements are made at 2.0 V for a logic "1" and 0.8 V for a logic "0." See Sacton 6 of the MOS Mirsprocessors and Peipherls Data Book (Order #090674) for Thormal Charactrstes riormaton as?

s B & | SWITCHING CHARACTERISTICS over operating range (for SMD/DESC and APL Products, Group A, Subgroups 9, 10, 11 are tested unless otherwise noted) (Note 1) [Re [+ [un | Assess Sane bore AD ——SCSC~dT 9 [sd] [2 Ina | Aarne Stato ator nea Sit of de | | [2 [wn | PEAD Pe wm SSSC*d | ef [4 fio | ate vats Fon EAD eT aw ||| [7s for | te Flow ater READ Note 3) | so] 0] 100 | [6 Jay | Time Berwoen READS andorwrrres [| eso || eso PTs | [wr a [eva Adress See Ato wate Sw Re Lt [2 Powe [wre pose wang aco fe] [Ro Tow [oot vate wo ware ey [00 [is fwo [bata vena at write Qe [omentwmes st CSCSCSS—CY [2 [we Wa=T oom nee aif om id | A,” [Jon _| Peter ata ater AO, EW fo fe | | [ie fixe Ao re wR Ye a00 | [ie fst | st aso wan QQ NG [sco [500 fe | [ir les | Pw. oats Goggle ga Side |e [ie fen | Por Oats Qt 0 te |e] [ie [uo Ack Ne om || [a0 uo Ack=1 SM Fee Woes «|| eo | | a | | [at fwoe | WA=t we O8r=a wen «tS aso oso | (22 [nos | AGK=0 6 OBF=1 woe) aso | sf Cas foe | ste=o r=1 awe) —*YSe|| a [es [ia RO-Ow NTA=0 Wow) ——*YSSamo|ato | [26 tor [ ste=ttomma=timorey fT 00 J 00 Ts [er [wn | Ack=ttowtR=1 moet) PT aso Paso os [22 [wr wr=ttowntr-ooioy Pf aso Jasons 2 Perea ‘of Reset pulse must be at least 50 ys during or after power on. Subsequent Reset pulse can be 500 ns 3. a float timing parameters tor and tkp are tested Logic 0 to float only.