80535 AMD | Alldatasheet
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8-Bit Single-Chip Microcontroller DISTINCTIVE CHARACTERISTICS & a ~ @ 8Kx8 ROM (60515 only) © Upward-compatible with 8051 a © 256x8 RAM © 16-bit Watchdog Timer gs © Six 8-bit ports; 48 1/0 lines © VPD provides standby current for 40 bytes of RAM 8 © Three 16-bit Timer/Event Counters, © Boolean processor a © Reload, capture, compare capabilities on Timer 2 © 256 bit-addressable locations © Full-Duplex Serial Port © Most instructions execute in 1 ys © Twelve Interrupt Sources; four priority levels © 64K bytes Program Memory space @ B-bit A/D Converter © 64K bytes Data Memory space GENERAL DESCRIPTION The 80515/80535 is a stand-alone, high-performance, —_ performance. With on-board A/D Converter and Watchdog ‘single-chip microcontroller based on the 8051 architecture. Timer, the 80515 is ideal for motor control applications > While maintaining all the 8051 operating characteristics, the ranging from automotive engines to vending machines. The 80515/80535 incorporates several enhancements which 80535 is identical to the 80515 except that it lacks the on- significantly increase design flexibility and overall system chip ROM. 5 BLOCK DIAGRAM a mth se ‘pke TCT .) ~ H [se] H L_| = : ! x. ' KK KD a i Le k= a : <a ' | Lswon Kk ; wy my == [Le kK H ‘ oot | i Ise 0 KO ts KEE roms =e fre ; 180007660 ng a 70
1 Issue Date: February 1909
CONNECTION DIAGRAM | Top View | sy PEER ER Se we edd ase PEE EG SESE SPREE SSC Er tcc eee nononAnoononnnonn Da DR eT eH eT rata wl rastt rats 2s [7 Paro pos] os 26 Psat, rel” 237) P32 arte ap pmo ma 2) peom ave [] 50 20] No aos ct) ean poo [| 82 wh rorC] ss 7D Ms roo] eh roo] sf 5 roa] 5 ub 6 vost] 57 13[ 7 ros] 2 Veco port] Waser ere . sof} RESET CODD oOUOOUUUUUUUG ss Bets eee PRieRER SIE PSP TEE €0011150 Note: Pin 1 is marked for orientation. LOGIC SYMBOL ey Yoo Yss porto oer pont: oor TAL, ponte wth oor vPo PORTS: vee oor pont 4 mio or “AREF goers Yaano a Ae meet PER 118003120 BS
ORDERING INFORMATION
‘AMD commodity products are available in several packages and operating ranges. The order number (Valid Combination) is formed bya combination of: a. Temperature Range b. Package Type ¢. Device Number — N 20515. ~ __¢. pevice_ NuMBER/DESCRIPTION 80515 (ROM Version) £80535 (ROM-Iess Version) BBit Single-Chp Microcontroliers —— b. PACKAGE TYPE N= 68-Pin Plastic Leaded Chip Carnor (PL 068) ‘a. TEMPERATURE RANGE Blank = Commercial (0 to +70°C) Valid Combinations | Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations, to check on newly released valid combinations, and to obtain additional data on AMD's standard military grade products.
PIN DESCRIPTION | Port 0 Port 0 (Input/Output; Open Drain) HIGH by the internal pullups and — while in this state — can Port 0 is an open-drain bidirectional I/O port. Port 0 pins that be used as inputs. As inputs, Port 3 pins externally being have "1's written to them float, and in that state can bo pulled LOW will source current (li.) because of the pullups. used as high-impedance inputs. Port 3 also serves the functions of various special features Port 0 is also the multiplexed LOW-order address and data as listed below: bus during accesses to external Program and Data Memory. in this. application it uses strong internal pullups. when [Pon [| Symbor_| _Aternate Function | emitting "1”'s. Port 0 can sink/source eight LS TTL inputs. P30 [AXD Soral input port Port 0 also outputs the code bytes during program p31 \\TxO Serial output port verification in the 80515. External pullups are required p32 |INTO External interrupt © input, during program verification timer 0 gate control Port 1 Port 1 (Input/Output) P33 |INTT External interrupt 1 input, Port 1 is an 8-bit bidirectional |/O port with internal pultups. jtimer 1 gate control Port 1 output buffers can sink/source four LS TTL inputs. P3.4 |TO ‘Timer 0 external counter input Port 1 pins that have '"1"'s written to them are pulled HIGH P35 |T1 ‘Timer 1 external counter input by the internal pullups and — when in this state — can be p36 |WR External Data Memory write used as inputs. As inputs, Port 1 pins that are externally strobe being pulled LOW will source current (Ii_ on the data sheet) P37 |RD External Data Memory read because of the internal pullups. Port 1 also receives the strobe LOW-order address bytes during program verification pon 4 Port 4 (input/Output) Port 1 aiso serves the functions of various special features Port 4 is an B-bit quasi-bidirectional 1/O port, Port 4 can as listed below: sink/source four LS-TTL loads. Port 5 is an &-bit quasi-bidirectional /O port. Port § can 1.0 |INTS/CCO [External interrupt 3 input, sink/source four LS-TTL loads. comeare © output, capture 0 call put Active LO 0, 7 level on this pin for the duration of two machine Prt |INTA/CC1 |Extemal interupt 4 Wp cycles while the oscillator is running resets the 80515. A compare 1 output, capture 1 faput ‘small internal pullup resistor permits power-on reset using pi.2 |INTS/CC2 External interrupt 5 input, only a capacitor connected to Vs. compare 2 output, capture 2 ALE Address Latch Enable (Output; Active HIGH) input ‘Address Latch Enable output pulse for latching the LOW p13 |INT6/CC3 | External interrupt 6 input, byte of the address during accesses to external memory. compare 3 output, capture 3 In normal operation ALE is emitted at a constant rate of 1/6 input the oscillator frequency, allowing use for external-timing or p14 |INT2 External interrupt 2 input clocking purposes. Note, however, that one ALE pulse is P15 |T2EX Timer 2 external reload trigger skipped during each access to external Data Memory. input ss P1.6 |CLKOUT {System clock output PSEN__ Program Store Enable (Input: Active LOW) pi7 |t2 Timer 2 external counter input 'PSEN is the read strobe to External Program Memory. When the 80515 is executing code from External Program Port 2. Port 2 (Input/Output) Memory, PSEN is activated twice each machine cycle — Port 2 is an 8-bit bidirectional 1/0 port with internal pullups. except that two PSEN activations are skipped during eact The Port 2 output buffers can sink/source four LS TTL access to External Data Memory. PSEN is not activated inputs, Port 2 pins having ''1"'s written to them are pulled during fetches from Internal Program Memory. HIGH by the internal pullups and — while in this state — can EA External Access Enabie (Input; Active LOW) be used as inputs. As inputs, Port 2 pins externally being EA must be externally held LOW to enable the device to pulled LOW will source current (Iy_) because of the internal fetch code from external Program Memory locations 0000H pullups. to 1FFFH. If EA is held HIGH, the device executes from
7 Internal Program Memory unless the program counter
Pon 2 ere Soar ea fer ea comes 10 contains an address greater than 1FFFH. For the 80535, EA External Data Memory that use 16-bit addresses (MOVX @ must be LOW DPTA). in this application it uses strong internal pullups —-XTALs Crystal (npul) when emitting “1's. During accesses to External Data Input to the inverting oscillator amplifier. When an external Memory that use 8-bit addresses (MOVX @ Ri), Port 2 emits oscillator is used, XTAL; should be grounded. the contents of the P2 Special Function register. XTAL2 Crystal (Output) Port 2 also receives the HiGH-order address bits during ‘Output of the inverting oscillator amplifier. XTAL2 is also the ROM verification. input for the oscillator signal when using an external Port 3 Port 3 (Input/Output) osclator Port 3 is an 8-bit bidirectional I/O port with internal pullups. Voc Power Supply The Port 3 output buffers can sink/source four LS TTL ‘Supply voltage during normal operations. inputs. Port 3 pins that have'"1""s written to them are pulled Vg Circult Ground
ree: i J ie] Esse = ot i eS! eo eg
TABLE 1. SPECIAL FUNCTION REGISTERS
82 DPL Data Pointer, LOW Byte 00000000
87 PCON Power Control Register OXXXXXXX_
89 TMOD Timer Mode Register 00000000
99 SBUF Serial Port Buffer Register Indeterminate
The SFRs marked with an asterisk (*) are both bit and byte-addressable. Figure 1 illustrates the memory address spaces of the 80515. bidirectional 1/0 port, while Ports 1 through 5 are quasi- 1724 of the oscillator frequency). ‘source current when externally pulled LOW. Port 0 will float 4 . useful in many applications for timing and counting. The input measurements.
2 Timer 2 register, low-byte register 2
ccLe Compare/capture register 2, low-byte ‘a one (1) must first be written into the appropriate bit latches. For brevity, the double-byte compare/reload/capture register latches depends on the compare modes established. is called the CRC register, the three double-byte compare/ sii ner op * . Figure 3 shows a block diagram of the timer 2 circuit. Figure 3. Block Diagram of Timer/Counter 2
the oscillator frequency. A 2:1 prescaler offers the possibility frequency to the timer. special function register T2CON (see Figure 4). If T2PS is procedure. This will facilitate pulse width measurements.
1210 T200N0
ecm | T2CON2 | Compare Mode Bit, When set, compare mode 1 is selected. T2CM = 0 selects compare mode 0. interrupt 2 to be negative-transition active. 19FR T2CON.6 | External interrupt 3 Falling/Rising Edge Flag. ‘extemal interrupt 3 to be negative-transition active. © tor the counter operation of timer 2. Figure 4. Timer 2 Control Register T2CON (0C8H)
1 PLINTg CC
Figure 6. Functional Diagram of Port Latches P1.0 to P1.3 in Compare Mode 0 __ | stored compare value. Figure 7 shows a functional diagram of write the modified value back to this “eft” latch. function, the “port latch” consists of two separate latches. Figure 7. Functional Diagram of Port Latches P1.0 to P1.3 in Compare Mode 1
16817 COMPARATOR
Figure 8. Functional Diagram of Timer 2 in Compare Mode Using CRC Register Figure 9. Functional Diagram of Timer 2 in Compare Mode Using CC Register 1
u Capture interrupt request flags 1EX3 to IEX6. if the interrupts are enabled, an external capture signal will cause the CPU to Each of the three compare/capture registers and the CRC register can be used to latch the current 16-bit value in the __Yeetor to the appropriate interrupt service routine Tn re nd ee i ones re In mode 1, a capture occurs in response to a MOV instruction 2 latching of the timer 2 contents 10 a dedicated capture the low-order byte of a capture register. The “wrte-to- arate See we onanting tine ois” signal (eq. “write to CRCL") is used to intiate a oncorde node the dedicated 16-bit capt oto ings _caplure. The value written to the dedicated capture register is One ne ea ane eae nae a \\telavant for tes function, The timer 2 contents wil be latched rete provided vv allow the software to rea i into the appropriate capture register in the cycle following the Contents “on the fy. MOV instruction. In this mode no interrupt request will be In mode 0, the external event causing a capture is: gonerated — {or OC rogistors 1 o 3: a positve Wransition at pins C3 19 In both capture modes the valve latched in the machine cycle of CC registers 1 to 3; in w hich the capture occurs will be the actual contents of — for the CRC register: a positive or negative transition, timer 2 in that machine cycle depending on the status of bit ISFR in SFR T2CON, at pin CO. I bit ISFR is cleared, a capture occurs in response to. Figures 10-1 and 10-2 show functional diagrams of the a negative transition, if bit ISFR is set in response to a capture function of timer 2. Figure 10-1 illustrates the opera- itive transition at pin P1.0/INT3/CCo. tion for the CRC register, while Figure 10-2 shows the posit pi 3 ig In this mode, the appropriate Port 1 pin is used as input, and OPeration applying to the compare/caplure register 1. This the port latch must Be programmed to contain a one (1). The OPeFation is the same for CC register 1 as well as for the OC ae rer innate coroied uae SBPB in every machine cyclo. f29st6"S 2 and 3. Substitute the symbols for the correspond. eee en esc a TOW (HGH tormputGGO,iritie _R9SghalS and names of CC registers 2 and 3 in Figure 10-2 programmed to be negative-transition-active) in one cycle and HIGH (LOW) in the next cycle, a transition is recognized. The The, WO capture modes can be. established indwidvally for timer 2 contents are lcd to te ‘appropriai eapure cet captue rar by bs in SFR CEN (compare/caphre register during S9P1 in the cycle following the one in which the Snape teaisien. wih 2 bits or cach capture register, That oad dented means, other than for the compare modes, it is possible to solect mode 0 for one capture register and mode 1 for another In mode 0, a transition on the external capture inputs CC to _register simultaneously. The bit positions and functions of CCS will also cause setting of the corresponding external CEN are listed in Figure 11. - TIMER 2 input Re er
2 THe Inter
mocK P= [| REQUEST ‘WRITE TO RCL | woes | WooE 0 ‘Tacon 6 PLOIINTs 0p C= = EXTERNAL INTERRUPT 3 REQUEST 78001230 re 10-1. Functional Diagram of Timer 2 in Capture Mode Using CRC Register ag
to clear the watchdog timer at least every 65,532 ys, an frequency. the software error was due to hardware-related problems, This first), and a stop bit (1). The baud rate is variable. watchdog timer is disabled and cleared to 0000H. The counter either 1/32 or 1/64 of the oscillator frequency. the watchdog timer was implemented to minimize the chance mode 3 is variable. watchdog from overflowing, it must be cleared periodically. srtornal_baud rate generator. modes: programmable reference voltages. Figure 12. A/D Converter Block Diagram
13, is used to select one of the eight analog input channels to conversion is in progress or not. Mxt ADCON.1 ‘Analog Input Channel Selection (see Table 4). ‘ADM =, the converter stops atter one conversion.
- ‘ADCON.5 Reserved (must be 0).
the serial port is taken from the internal baud rate generator. Figure 13. A/D Converter Control Register ADCON (OD8H) TABLE 4. SELECTION OF THE ANALOG INPUT of 1 V difference is required between the internal reference | ~ C) 1 1 |Analog Input 3 ANS y zy, + DAPR(O — 3) wv, _y, . conversion has been started. ADDAT can be read and written _—_‘taken as_an unsigned decimal integer. The SFR DAPR is provided for programming the internal . (Varner — VaGNo) by 4 bits each in register DAPR. Bits 0103 Figure 14. shows special function register DAPR.
{shown in Table 5) can be adjusted via the special function register DAPR. Figure 14. D/A Converter Program Register DAPR (ODAH) VOLTAGES the conversion time is 15 ys for 12-MHz oscillator frequency. rules listed above (IVaRer at least four steps higher than Started in the following machine cycle. same machine cycle that the “‘write-to-DAPR" operation ’#l0g value. ‘occurs. If the value written to DAPR is 00H, meaning that no Figures 15-1 and 15-2 illustrate these applications.
bit ISFR in register T2CON. The flag that actually generates the pins. Figure 16 shows the special function register IRCON. vectored to. this location is occupied by register IEN1.
7 OC7H 0CEH —OCSH OCAH-OCBH_-OCZH_-—OCIH_-«OCOH ADDRESS
of @ conversion. Must be cleared by software. Figure 16. Interrupt Request Control Register IRCON (0COH)
request is serviced fist. If requests from two interrupt sources ‘@S0V@ Simultaneous requests within the same prionty level. the polling sequence, as follows: interrupt structure.
113 Pos TE1/IEXS
Figure 18. Interrupt Priority Registers IPO (OASH) and IP1 (0B9H)
Figure 19. Priority Level Structure
Figure 20. Interrupt Request Sources
cycle. If one of the flags was in a set condition at of interrupt Is vectored 10. registers IENO, IEN1, IPO, or IP1. new. Figure 21. Interrupt Response Timing Diagram
I {External Interrupts Of equal or higher priority level is already in progress, the additional wait time obviously depends on the nature of the The external interrupts 0 and 1 can be programmed to be other interrupt's service routine. If the instruction in progress is level-activated or negative transition-activated by setting of aot in its final cycle, the additional wait time cannot be more Clearing bit ITO or IT1, respectively, in register TCON. IfITx=0 than three cycles, since the longest instructions (MUL and | (= 0or1), external interrupt x is triggered by a detected LOW jy) are only four cycles long; and, if the instruction in | atthe INT, pin. 11Tx = 1. external interrupt xis negative edge- progress is RET! or an access to registers IENO, IENT., IPO, or triggered. In this mode, if successive samples of the INTx pin jp, the additional wait time cannot be more than five cycles (a show a HIGH in one cycle and a LOW in the next cycle, maximum of one more cycle to complete the instruction in interrupt request flag IEx in TCON is set. Flag bit IEx then progress, plus four cycles to complete the next instruction if | requests the interrupt the instruction is MUL or DIV), _ If the external interrupt 0 or 1 is level-activated, the external Thus, in a single interrupt system, the rasponse time is always source has to hold the request active until the requested more than three cycles and less than nine cycles. interrupt is actually generated. Then it has to de-activate the request before the interrupt service routine is completed, or RAM Backup Power Supply ise another intorupt wal be generated ‘The power-down mode in the 80515 allows reduction of Voc The external interrupts 2 and 3 can be programmed to be _to zero while saving 40 bytes of the on-chip RAM through a | negative or positive transition-activated by setting or clearing backup supply connected to the Vpp pin. In the following, the bit I2FR or ISFR in register T2CON. If IKFR=0 (x=2 oF 3), terms Voc and Vpp are used to specify the voltages on pin ‘external interrupt x is negative transition-activated. If kFR= 1, Voc and pin Vpp, respectively. external interrupt x is triggered by a positive transition. {Veg > Veo. the 40 bytes are supplied from Voc. Veo may ‘The external interrupts 4, 5, and 6 are activated by a posttive then be LOW. If Vcc < Vp, the current for the 40 bytes is transition. The external timer 2 reload trigger interrupt request drawn from Vpp. The addresses of these backup-powered flag EXF2 will be activated by a negative transition at pin RAM locations range from 88 to 127 (58H to 7FH). The current P1.5/T2EX, but only if bit EXEN2 is set. drawn from the backup power supply is typically 1 mA, Max. Since the external interupt pins (INT to INTe) are samples ° ™ ‘once each machine cycle, an input HIGH or LOW should hold To utilize this feature, the user's system — upon detecting that fo at least 12 oscillator periods to ensure sampling, If the 4 Power failure is imminent — would interrupt the processor in external interrupt is transition-activated, the external source some manner to transfer relevant data to the 40 bytes in on- has to hold the request pin LOW (HIGH for INT2 and INTs, it chip RAM and enable the backup power supply to the Vpp pin. they are programmed to be negative transition-active) for at Then a reset should be accomplished before Voc falls below least one cycle, and then hold it HIGH (LOW) for at least one _its operating limit. When power returns, a power-on reset cycle to ensure that the transition is recognized so that the should be accomplished, and the backup supply needs to stay Corresponding interrupt request flag will bo set. The external on long enough to resume normal operation. Figure 22 ~ interrupt request flags will automatically be cleared by the CPU _ illustrates the timing on a power failure. when the servi ine is called. hen the sence routing Is called System Clock Output Response Time For peripheral devices requiring a system clock, the 80515 It an external interrupt is recognized, its corresponding request provides a clock output signal derived from the oscillator flag is set at SSP2 in every machine cycle. The value is not frequency as an alternate output function on pin P1.6/CLKOUT. If actually polled by the circuitry until the next machine cycie. If bit CLK is set (bit 6 of special function register ADCON), & the request is active and conditions are right for it to be clock signal with 1/12 the oscillator frequency is gated to pin acknowledged, @ hardware subroutine call to the requested ——_—P1.6/CLKOUT. To use this function the Port 1 pin must first be service routine will be the next instruction to be executed. The programmed to a one (1), IMtorupt request and the beginning of executing the frst respect to signal ALE and the internal states. The system clock is HIGH during SP1 and S3P2 of every machine cycle instruction of the service routine. Figure 21 shows interrupt response timings. and LOW during all other states. Thus, the duty cycle of the clock signal is 1:6. Also shown is the timing with respect to an A longer response time would result i the request is blocked external data memory access. The system clock coincides by one of the three previously listed conditions. If an interrupt with the last state (S3) in which an FD or WA signal is active. a
Figure 24. On-Chip Oscillator Circuitry
i ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Voltage on Any Pin Temperature (TA)....oossesesssereeeessseeeeeens0 1 +70°C Stresses above those listed under ABSOLUTE MAXIMUM Operating ranges define those limits between which the RATINGS may cause permanent device failure. Functionality functionality of the device is guaranteed. at or above these limits is not implied. Exposure to absolute ‘maximum ratings for extended periods may affect device DC CHARACTERISTICS over operating range unless otherwise specified Parameter Parameter Test Symbol Description Conditions [Wie eros Cs fo Input HIGH Voltage vw (Except RESET and XTAL2) Voc +08 v XTAL = V. | [a faeeteome me Rare [ae aa LOW Gael w REGET for Resst —[vu=oasv |_| a | a _| [is Pipi estas Gort Fon 8 EK ovevwcves | [= [ok | Power Supply Current All Outputs loc 80515/80595 Disconnected 210 ma [ise | Powerdown cure veo [co [eanestance ovo Guide te PCr _ a
SWITCHING CHARACTERISTICS over operating range unless otherwise specified (CL for Port 0, ALE, | and PSEN outputs = 100 pF; Cy for all other outputs = 80 pF) Symbol Description ee aa [octet | [Toni [ALE pase wade | cw’ [ [ravi [asin Soup AE Ps] TRC | - [TuaKi [Ades now Aw Ewe] |u| — Tun [aewrenSSC*dSC aw | [rei [PSN pose wan SSCs iP rs || SO [rex Tirwt svoten vows ane EW OT [rex | np scion Pout Ate EEN | ue |_| [reat [aoaens rears CP mT | [rain [5 paso wan Sie | [rcv [Roto va daw SSS me recs | [rox |onaroaawmo SPP | [rane |onaron aro CP reco || [roy [ate w vendo rence | [raw —[asiess wR RBC me [CP || [wns [WR ROHGH ARGH [a | | racw | vaaso | mw | [row [oaa vais WR Vanstone fp rac [| | [Towra Seip bore Wm ce || [wor Oa row ae WR Cm uc |e [mia [Adios osiane RPT damage to Port 0 drivers.
i SWITCHING WAVEFORMS as yun | = {| ravi TPLAZ wag oo am) {oe} fom Fe) a? a ce Program Memory Read Cycle “ J RN a ws oH} {a Data Memory Read Cycle
SWITCHING WAVEFORMS (Cont'd.) Tween} | | ne | | ya, — $+ 1r wr02s970 Data Memory Write Cycle c T 1 ra. ate 1212Mie TF im 21 xray ° b 281 raLy c Te T4LS04 © =300F 210 pF Crystal Oscar Mode Diving rom Extemal Source 1000880 Recommended Oscillator Circuits
i EXTERNAL CLOCK DRIVE Parameter Parameter Symbol Description wTCuce | Oscitator Frequency] eT [tonox | igh time Ps LOW Time a Rise Time ee ee reno Fat time 20s oav: 22 ee OF cl wr025900 External Clock Drive Waveform SERIAL PORT TIMING — SHIFT REGISTER MODE (Load Capacitance = 80 pF) Prue parameter [seme ove. | varati Oncor Symbol Description [ win. [wax [win [Mex | Serial Port Clock Cycle Time es a - Ouiput Data Setup to Clock Rising Edge | 700 | [rorcicu-saa[ ns Output Data Hold After Giock Fising Edge [60 [| arcuct-1i7 [ns Input Data Hold Ater Glock Rising Edge [0 | [9 | ns | Glock Rising Edge to Input Data vaid || 700 Tf sorcuci- 133] ns _| AC Testing Yoo 88 TB Veg oe Mion 01 v Nou 01 Yow —{ ne nermoee 02 vgg 08 Ponts wF02s400 weo2s10 FOR TIMING PURPOSES, A PORT BIW iS NO LONGER FLOATING WHEN dc PUTS DURING TESTH 1 Voc , He AN Ons V TOR A LOSE “OF THING MEASUREMENTS ARE MADE | | 100 0¥ CHANGE FROM LOAD OCCURS IT BEGINS TO FLOAT WHEN AT Vin MIN. FORA LOGIC "1" AND Vi, MAX. FOR A LOGIC "0. ou #20 mA owen Input/Output Waveform Float Waveform Fo
1/TCLCL = 1.2 MHz to 12 MHz Parameter Parameter Symbol Description a SR CLKOUT HIGH Tine [oer rocco [isis eixour tow Times} re] erence fs CAKOUT LOW to ALE HIGH [me [me rata [racine [es] — sux nue ——rusn. pots Tush ——o cuour | OWA ——— Progam Memory Recess at Mary Acco wr025430 System Clock Timing A/D Converter Characteristics (Vcc = 5 V +10%; Vss = 0 V; Varner = Voc *5%; VaGnp = Vss *0.2 V; Ta=0 to +70°C) Parameter Test Description Conditions Traiog pt Votage [| vacnor02 | Vavervoe |v | A a To Conversion Time for WVaner = VAREF q5 1cv {Including Sample Time) and IVaGNO = VAGNO for (Vaner # VaREF and IVaGNo = VAGND or 22 TCY for IVaner = VAREF and _IVAGNo * VAGND for IWaner # VaRer and IVaGNO # VAGND 20 TOY us Vaner = Voc VaGno = Vss _ Input Source I ‘Notes: 1. The internal resistance of the analog source must be less than 10 kQ to assure full loading of the sample capacitance during sample time 2. The internal resistance of the analog reference voltage source must be less than 1 ki. 3. Typical values are 25 pF.
i PHYSICAL DIMENSIONS* PL 068 } # | A ae (mz 4 b IP ~ q p ee ™ kT q p+ = q Pt Ph = | er
4 Saar
q ; Fr q 2 = = s = - PO scene ~ *For reference only. 7 a
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