80286

80286 AMD | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 62

Technical content

ADVANCED MICRO DEVICES 26— D Ml 0257525 0034427 S mm AND

80286 Advanced

High-Performance Microprocessor with Micro Memory Management and Protection Devices TT . DISTINCTIVE CHARACTERISTICS ™ High-performance processor (up to 13.3 times @ High bandwidth bus interface JAPX 86 when using the 16 MHz 80286) (16 megabyte/sec) ™ Large address space —16 megabytes physical ™ Range of clock rates —1 gigabyte virtual memory per task —8 MHz 80286-8 ™ Integrated memory management, four-level —10 MHz 80286-10 memory protection and support for virtual 12 MHz 80286-12 memory and operating systems 16 MHz 80286-16 ™ Two IAPX 86 upward-compatible Operating modes ~iAPX 86 real address mode ~Protected virtual address mode T_T GENERAL DESCRIPTION ‘The 80286 is an advanced, high-performance micropro- —_ tasks, A 16-MHz 80286 provides up to 13.3 times greater cessor with specially optimized capabilities for multiple throughput than the standard 5-MHz 8086, The 80286 in- user and multi-tasking systems. The 80286 has built-in cludes memory management Capabilities that map up to memory protection that supports operating system and 2*bytes (one gigabyte) of virtual address. space pertask task isolation as well as program and data Privacy within into 2* bytes (16 megabytes) of physical memory. —_— o_o BLOCK DIAGRAM "Causa porto = === [Address Unit (auy i | | wottione Fy» tito | netics Bocaeas > PERCR

1 Segment Interface eH READY, HOLD

| /SE\\ _— Sxconi > Hage gone checker Data Transceivers Dy Law ! it Se oven cau) | r —--—~-. EN Lee Seen ad Decoded | snucton I cuK Sa ae | OT Leecucoumen FRET] ene re) now’ | | Teusy INTR’ ERROR 03552-1 Poblcaions O3552 Rev. F _Amaodmen

ADVANCED MICRO DEVICES 26E D M@ 0257525 0034428 7 MAND GENERAL DESCRIPTION (continued) The 80286 Is upward-compatible with iAPX 86 and 88 The 80286 provides special operations to support the software. Using |APX 86 real address mode, the 80286 _ efficient implementation and execution of operating sys- Is object-code compatible with existing IAPX 86, 88 —_ tems. For example, one instruction can end execution software. of one task, save its state, switch to a new task, load its : f 4 In protected virtual address mode, the 80286 is source- Se ee at wrenony Syston My mown code compatible with IAPX 86, 88 software and May a seqment-not-present exception and restartable require upgrading to use virtual addresses supported by —_ingtructions the 80286's integrated memory management and pro- : . tection mechanism. Both modes operate at full 80286 performance and execute a superset of the IAPX 86 and 88 instructions. Related AMD Products [rie | onersin | 4 | SSSSSSSSSSSSSSSSSSSSSSSSSSSsSSSS 80286 1-67

ADVANCED MICRO DEVICES 28E D Mm 0257525 0034429 9 mm AMD _28E DM 0257525 0034429 9 mm A CONNECTION DIAGRAMS T-N9-1 9-15 Component Pad Views—As viewed from tee PC Board Views—As viewed from the underside of component on the PC Board component side of the PC Board a a] §2 4 WEEEEEE EEE MEE BEARS Age [i D5] Ves Vesa) Ga] An ra] Geo, ©, Bl . | Ea tao. OB ra] . im) Galo, D, faa] Ca} fa) Ga] O, 0, G3 : [ tal ould | rae qo amass oh han tao, oad are Soa al to” By ys te fA ilo. Eee ale a Ge. Ea Ce Bre belo} fed lb fel fe) Fd afd Eo Ff] ESialelzlslelelel ae ls lela la AA Ll i eee) a L Pin No. 1 Mark Pin No. 1 vont There are no electrical connections on the 09550-2 bottom of this package os60-8 PGA | @8@06000666 |! fos "ar en Sar eo es Yar a0 61 © ©9G©8000000} 04 30 0 0 %12 44 S45 48 50 50 S52 ie ® @@! 32 39 5 Hom) 2) e| 28 *29 “ea a8 1@® (2) e ta 5 “ae oe ® e| *2 "2s ws 4

19299008 COOO® tra 10 M18 Me te M0 80% 4 fe Mag

XO ©0900000 | a i Pin No. 1 Mark 03552-4 03552-5 Pins pointing away from viewer Pins pointing toward viewer Sn 1-68 80286

ADVANCED MICRO DEVICES 286 D m™ 0257525 0034430 S mm AMD T-49-17-15 . PGA (continued) Bottom View (oO ORO OROMORORO) " PPO DODOOOOO;|” (oxo) lOROR . tomo} © O}8 (OO) © O|7 (ORO) QoO}6 toto) ©o|5 foo) © oO|4 tomo} eo/3 ®VDODOOOOO8O}2 (ORO MOMOMOROROMORO) 1 HG EDCBA 03852-6 PIN DESIGNATIONS (Sorted by pin number) Pin Pin Pin Pin Pin Pin No. Name No. Name No. Name

1 BHE 24 Ar 47 Ors

2 NC 25 As 48 De

3 Ne 26 As 49 Dis

5 So 28 As 51 Dis

6 PEACK 29 RESET 52 CAP.

7 Aas 30 Veo 53 ERROR

8 Azz 31 CLK 54 BUSY

9 Vos 32 A 55 NC

10 Aat 33 A 58 NC

1 Azo 34 Ao 57 INTR

12 Ais 35 Vso 58 NC

13 Ave 36 Do 59 NMI

14 Av 37 De 60 Vss

17 Au 40 De 63 ifxov

18 Ais 41 Dio 64 HOLD

19 Av 42 Ds 65 HLO,

20 An 43 Du 66 CONTR

22 As 45 De 68 LOCK

23 As 46 Ds

: -80286 1-69 , |

ADVANCED MICRO DEVICES 26E D MM 0257525 0034431, 7 mm AMD Ea ES T~49-17. . ORDERING INFORMATION 49-17-15 Commodity Products AMD standard products are available in several packages and operating ranges. The ordering number (Valid Combination) is formed by a combination of: a. Temperature Range b. Package Type ©. Device Number d. Speed Option (if applicable) @. Optional Processing R 80286 46 Le 4. SPEED OPTION

1616 MHz

712=125 MHz -10=10 MHz = 8=8 MHz ©. DEVICE NUMBER/DESCRIPTION High-Performance Microprocessor b. PACKAGE TYPE R= 68-Pin Caramic Leadless Chip Cartier (CA2068) A= 68-Pin Grid Array (CGX068) N= 68-Pin Plastic Leaded Chip Carrier a, TEMPERATURE RANGE (PLo6e) Blank = Commercial (To = 0 10 +85° C) Valid Combinations 0286-8 80286-10 80286-12 80286-8 80286-10 80286-12 80286-16 Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device, Consult “The PLCC package Is not a valid ordering part number for the the local AMD salas office to confirm availabilty of 80286. The PLCC package is valid for the 80L286 part number. See fpecifi valid combinations, to check on newly re- the 80.286 data sheet (order #08511D) for ordering information and leased combinations, and to obtain additional DC and AC parametrics, data on AMD's standard military grade products. SSS 1-70 80286

ADVANCED MICRO DEVICES 26— D m@ 0257525 0034432 9 mm AND PIN DESCRIPTION J-49-17-15 CLK eT System Clock (Input; Active HIGH) 80286 Bus Cycle Status Definition System Clock provides the fundamentaltimingfor80286 Gop) SOS systems. Itis divided by two inside the 80286togenerate INTA M10 51 SO Bus Cycle Status Definition can be synchronized to an external clock generator by gow) $ 8 ° interrupt acknowledge 40-1 oserve' ‘LOW-to-HIGH transition on the RESET input. Hy 0 1 O Reserved De-Dis 0 0 4 1 None; not a status cycle . Data Bus (Input/Output; Active HIGH) ° 139 Momnory densa? shutdown Data Bus inputs data during memory, I/O, and interrupt =o. 1 1 0 Memory data write acknowledge read cycles; outputs data during memory 0 4 1 1 None; not a status cycle and 1/0 write cycles. The data bus is active HIGH and = 1(HIGH) 0 0 0 reseed floats to three-state OFF during bus hold acknowledge. } H ° } to trad ; 1 0 1 1 None; nota status cycle Aas-Ao 1 1 0 0 Resorved “ Address Bus (Output; Active HIGH) 1 19 1 Memory instruction read Address Bus outputs physical memory and /O port ad-} ese dresses. Ao is LOW when data is to be transferred on! 111 None; not a status cycle pins Dro, AzsAve are LOW during /O transfers. The address bus is active HIGH andfloatstothree-state OFF aig i hol ledge. during bus hold acknowledge. Memory/iO Select (Output) BHE Memory/IO Select distinguishes memory access from Em Bus High Enable (Output; Active LOW) VO access. If HIGH during Ts, a memory cycle or a Bus High Enable indicates transfer of dataonthe upper _halt/shutdown cycle is in progress. If LOW, an V/O cycle byte of the data bus Dis, Eight-bit orlented devices _or an Interrupt acknowledge cycle Is in progress. M/O- assigned to the upper byte of the data bus would nor- floats to three-state OFF during bus hold acknowledge. mally use BHE to condition chip select functions. BHE is a active LOW and floats to three-state OFF during bus hold COD/INTA acknowl- Code/Interrupt Acknowledge (Output) edge. Code/Interrupt Acknowledge distinguishes instruction sss), <== fetch cycles frcom memory data read cycles. Also distin- BHE and A, i guishes interrupt acknowledge cycles from I/O cycles. WE OA and A, Encodings CODIINTA floats to three-state OFF during bus hold ac- Value Value Function knowledge. O_O Word transfer hallo LOCK 0 1 Byte transfer on upper half of data bus (D,54) . 1 0 Byte transfor on lower half of data bus (D,,) BUS Lock (Output; Active LOW) 1 1 Reserved Bus Lock indicates that other system bus masters are not _ 10 gain control of the system bus following the current : = bus cycle. The LOCK signal may be activated explicitly Si, SO by the “LOCK” instruction prefix or automatically by Bus Cycle Status (Output; Active LOW) Bus Cycle — 80286 hardware during memory XCHG instructions, in- Status indicates initiation of a bus cycle and, along with —_terrupt acknowledge, or descriptor table access. LOCK. M/0 and COD/INTA, defines the type of bus cycle. The _ is active LOW and floats to three-state OFF during hold bus is in a Ts state whenever one or both are LOW. 51 —_ acknowledge. and SO are active LOW and float to three-state OFF during bus hold acknowledge. SSS 80286 7

ADVANCED MICRO DEVICES es D M™ 0257525 0034433 0 mm AMD PIN DESCRIPTION (continued) T~49-17~15 . . READY PEREQ, PEACK *. Bus Ready (Input; Active LOW) Processor Extension Operand Request and Bus Ready terminates a bus cycle. Bus cycles are ex- Acknowledge (Input/Output) tended without limit until terminated by READY LOW. Processor Extension Operand Request and Acknowl- READY is.an active LOW synchronous input requiring — edge extended the memory management and protection set-up and hold times relative to the systemclockbe met capabilities of the 80286 to processor extensions. The for correct operation. READY is ignored during bus hold PEREQ input requests the 80286 to perform a data oper- acknowledge. and transter for a processor extension. The PEACK out- : put signals the processor extension when the requested HOLD, HLDA operand is being transferred. PEREQ Is active HIGH and Bus Hold Request and Hold Acknowledge. may be asynchronous to the system clock. PEACK Is (Input/Output; Active HIGH) active LOW. Bus Hold Request and Hold Acknowledge control owner- ship of the 80286 local bus. The HOLD input allows BUSY, ERROR another local bus master to request control of the local + Processor Extension Busy and Error bus. When control is granted, the 80286 will float its bus __(Input/Input, Active Low) drivers to three-state OFF and then active HLDA, thus Processor Extension Busy and Error indicate the operat- entering the bus hold acknowledge condition. The local —_ing condition of a Processor extension to the 80286, An bus will remain granted to the requesting master until active BUSY. input stops 80286 program execution on HOLD becomes inactive which results in the 80286 de- — WAIT and some ESC instructions until BUSY becomes activating HLDA and regaining contro! of the local bus. inactive (HIGH). The 80286 may be interrupted while This terminates the bus hold acknowledge condition. waiting tee to become inactive. An active ERROR HOLD may be asynchronous to the systemclock. These input causes the 80286 to performa processor extension signals are active HIGH. interrupt when executing WAIT or some ESC instruc- INTR tions. These inputs are active LOW and may be asyn- Interrupt Request (Input; Active HIGH) Chronous to the system clock, Interrupt Request requests the 80286 to suspenditscur- RESET rent program execution and service a pending external System Reset (Input; Active HIGH) Fequest. Interrupt requests are masked whenever the system Reset clears the internal logic of the 80286 and interrupt enable bit in the flag word is cleared. When the \\s active HIGH. The 80286 may be reinitialized at any 80286 responds to an interrupt request, it performs two time with a LOW-to-HIGH transition on RESET which interrupt acknowledge bus cycles to read an 8-bit inter- remains active for more than 16 system clock cycles. rupt vector that identifies the source of the interrupt. To During RESET active, the output pins of the 80286 enter assure program interruption, INTR must remain active jhe state shown below: until the first interrupt acknowledge cycle is completed. INTR is sampled at the beginning of each processor cycle and must be active HIGH at least two processor 80286 Pin State During Reset cycles before the current instruction ends in order to. G——————_ SS Dating Reset interrupt before the next instruction, INTR Is level sensi- Tay RSET tre, acta HIGH, and may be asynchronous to the sys o{Low) MIG, CODANTA LOA Three-state OFF Dys-D, NMI a Non-maskable Interrupt Request (Input; Active HIGH) Operation of the 80286 begins after a HIGH-to-LOW Non-maskable Interrupt Request interrupts the 80286 _ transition on RESET. The HIGH-to-LOW transition of with an internally supplied vector value of 2. No interrupt RESET must be synchronous to the system clock. Ap- acknowledge cycles are performed. The interruptenable _ proximately 50 system clock cycles are required by the bit in the 80286 flag word does not affect this input. The 80286 for internal initializations before the first bus cycle NMI input is active HIGH, may be asynchronous to the __t0 fetch code from the power-on execution address Is ‘system clock, and Is edge triggered after internal syn- performed. chronization. For proper recognition, the input must have been previously LOW for at least four system clock cy- cles and remain HIGH for at least four system clock cycles. ee 4-72 80286

ADVANCED MICRO DEVICES 26— D m@ 0257525 0034434 2 mm AND PIN DESCRIPTION (continued) T-49-17-15 ALOW-to-HIGH transition of RESET synchronoustothe CAP system clock will begin a new processorcycle atthenext — Substrate Filter Capacitor (Input; Active High) HIGH-o-LOW transition of the system clock. The LOW- 4 9.947 uF +20% 12 V capacitor must be connected to-HIGH transition of RESET may be asynchronous 10 between this pin and ground, This capacitor fiters the the system clock; however, in this case it cannot be output of the internal substrate bias generator. A maxi- predetermined which phase of the processor clock will mum DC leakage current of 1 1A is allowed through the occur duringthe next systemperiod. SynchronousLOW- capacitor. to-HIGH transitions of RESET are only required for sys- . - tems where the processor clock mustbe phase synchro- —_For correct operation of the 80286, the substrate bias . nous to another clock. generator must charge this capacitor to its operating voltage. The capacitor charge-up time is 5 milliseconds Vss (max.) after Voc and CLK reach their specified AC and ‘System Ground (Input; Active HIGH) DC parameters. RESET may be appliedto prevent spuri- System Ground: 0 volts. ous activity by the CPU during this time. After this time, the 80286 processor clock canbe phase synchronized to Veo another clock by pulsing RESET LOW synchronous to System Power (Input; Active HIGH) the system clock. System Power: +5 volt power supply. 80286 1-73

The 80286 Is an advanced, high-performance micropro- tn 8086, 8088, and 80186 CPUs. 7 ters used to contain arithmetic and logical operands. . mode and potted ital aedvese moos fohmeaes Four of these (AX, BX, CX, and DX) canbe used eltherin . In IAPX 86 real address mode programs use real ad- . - . The following pages describe first, the base 80286 archi. PeCific registers used for operand address calculations.

80286 Base Architecture Pointer, which contains the offset address of the next

The IAPX 86, 88, 186, and 286 CPU family allcontainthe sequential Instruction to be executed.

15 C) MswW Machine Status Word

Figure 1. Register Set

ADVANCED MICRO DEVICES 26€ D mm 0257525 GO3443b & mm AND . Figure 2. Status and Control Register Bit Functions

16-bit register. The function of the flag bits is given in _ ures 3-9. Table 1. ‘An 80286 Instruction can reference’ zero, one, or two Table 1. Flags Word Bit Functions operands where an operand rasides In a register, inthe instruction itself, or in memory. Zero-operand instruc- . tions (@¢.9., NOP and HLT) aré usually one byte long.

4 AF Set on carry-from of borrow-to the low-or- ory to Reg

WW OF — Overflow Flag—Set if result is atoo-large tions are provided by a special class of string instructions. nation operand; cleared otherwise at the end of this document.

8 TF Single Step Flag—Once set, a single step *

9 IF Interrupt-Enable Flag—When set, mask-

10 OF Direction Flag—Causes string instruc-

ADVANCED MICRO DEVICES 26— D M@ 0257525 OO34440 8 mm AND . Table 2. Segment Register Selection Rules Addressing Modes T-49~-17-15 displacements are sign extended to 16-bit values. r . instruction as an 8- or 16-bit displacement element. Process of the contents of a base register and an index register. Figure 11. Segmented Memory Helps Structure Software

ADVANCED MICRO DEVICES 26— D M@@ 0257525 OO3444) T Mm AND . Data Types BCD: Abyte (unpacked) representation of the The 80286 directly supports the following data types: decimal dighs 0-8, T-49-17-15 Integer: A signed binary numeric value con- Packed BCD: Sanita, Knackec) Fepresentation of two igits 0-9 storing one digit in tained In an 8-bit byte or a 16-bit word. each nibble of the byte. All operations assume a two's comple- * ment representation. Signed 32- and —_ Floating Point: A signed 32-, 64-, or 80-bit real number 64-bit integers are supported using the representation. (Floating point oper- 80287 Numeric Data Processor. ands are supported using the iAPX 287 Ordinal: ‘Anunsigned binary numeric value con- Numerio Processor configuration.) tained in an 8-bit byte or 16-bit word. Figure 12 graphically represents the data types sup- . Pointer: A 32-bit quantity, composed of a seg- Ported by the 60286. ment selector component and an offset /O Space Garg nent Each components a 16-0 He 10 space consists of 64K 8-bit oF 32K 16-bit ports. . VO instructions address the I/O space with either an8-bit String: A contiguous sequence of bytes or port address, specifled in the instruction, or a 16-bit port words. A string may contain from 1 byte address in the DX register. Eight-bit port addresses are to 64K bytes. Zero extended such that Ats~As are LOW. I/O port ad- sca: A byte representation of alphanumeric %28888 OOF(H) through OOFF(H) are reserved. and control characters using the ASCII standard of character representation. Ss . Interrupts An interrupt transfers execution to anew program loca- (discussed in the System Interface section) identifies the tion. The old program address (CS:IP) and machine source of the interrupt. State (Flags) are saved on the stack to allow resumption sare inooupied program, interrupts fall eelion Further maskable interupts are disabled while servicing classes: hardware initiated, INT instructions, and in- aninterrupt by resetting the IF but as part of the response struction exceptions. Hardware Initiated interrupts occur '© an Interrupt Se orci ‘The saved flag word will In response to an external input and are classified as _‘"etlect the enable status of the processor prior to the non-maskable or maskable. Programs may cause an Interrupt. Until the flag word is restored to the flag regis- interrupt with an INT instruction. instruction exceptions ter, the interrupt flag will be zero unless specifically set. ‘occur when an unusual condition, which prevents further The interrupt return instruction includes restoring the flag instruction processing, Is detected while attempting to 0rd, thereby restoring the original status of IF. execute an instruction. The return address from an ex- -Maskal ‘errupt Rt NMI ception will always point at the instruction causing the NO?-Maskable Interrupt lequest (NMI) exception and include any leading instruction prefixes. | A non-maskable interrupt input (NMI) is also provided. . NMI has higher priority than INTR. A typical use of NMI Atable containing up to 256 pointers defines the proper —_ would be to activate a power failure routine. The activa- interrupt service routine for each interrupt. Interrupts tion of this input causes an interrupt with an internally 0-31, some of which are used or instruction exceptions, supplied vector value of 2. No external interrupt acknowl- are reserved. For each interrupt, an 8-bit vector must be edge sequence is performed. supplied to the 80286 which identifies the appropriate " table entry. Exceptions supply the interrupt vector inter- _ While executing the NMI servicing procedure, the 80286 nally. INT instructions contain or Imply the vector and _Will not service further NMI requests, INTR requests, or allow access to all 256 interrupts. Maskable hardware- the processor extension segment overrun interrupt until initiated Interrupts supply the 8-bit vector to the CPU —_an interrupt return (IRET) instruction Is executed or the Guring an interrupt acknowledge bus sequence. Non- — CPU is reset. If NMI occurs while currently servicing an maskable hardware interrupts use a predefined inter- NMI, its presence will be saved for servicing after execut- nally supplied vector. ing the first IRET instruction. IF is cleared at the begin- ning of an NMI interrupt to inhibit INTR interrupts, Maskable Interrupt (INTR) Single Step Interrupt The 80286 provides a maskable hardware interrupt re- 9 P P quest pin, INTR. Software enables this input by setting The 80286 has an intemal Interrupt that allows programs. the interrupt flag bit (IF) In the flag word. All 224 user-de- _{ execute one instruction af atime. Itis called the single fined Interrupt sources can share this input, yet they can _step interrupt and is controlled by the single step flag bit retain separate interrupt handlers. An 8-bit vector read (TF) in the flag word. Once this bit is set, an internal by the CPU during the interrupt acknowledge sequence _Single step interrupt will occur after the next Instruction SSS 1-80 80286

ADVANCED MICRO DEVICES 28 D mm 0257525 0034442 1 mm AMD siaed F ° T-49-17-15 7 ot na Sign Bit! . ‘an Magnitude Le Unsigned [7 1, Byte Magnitude . “4 a signed Petree ° . 4 ‘SB Sign Bit ‘Magnitude . Signed 3 42 P co ° ‘ot (eer pouble sign bt J LMS an Bt Magnitude Quad Word* vio TLMSE Sign Bit Magnitude * wt o, Unsigned MSB. Magnitude Binary nN + gy 0 Coded see (BCD) BCr BCD BCD Digit N Digit 1 Digit 0 ‘N “4, 0 Asc ASci —_ASon Character, Character, Character, N 4g, 0 Packed vee BCD Most Significant Digit Least Significant Digit

3 N wor O

Byte/Word N Byte/Word 1 Byte/Word 0 s 2 “ 0 ce Selector Offset o 8 7 6 5 Floating Point* ign Bit Sign Bit Exponent Magnitude Figure 12, 60266 Supported Data Typos *Supported by iAPX 286/287 Numeric Data Procassor Configuration o9652-11 SSS 80286 1-81

Table 4. Interrupt Processing Order Table 5. 80286 Initlal Register State after RESET

1 INT instruction or exception Instruction pointer FFFO(H)

4 Processor extension segment overrun Extra segment 0000(H

Next instruction to be single stepped. IAPX 86 real address mode. When simultaneous interrupt requests occur, they are TS, EM, and MP is shown in Table 7. cannot be cleared except by RESET. 80286 to terminate all execution and local bus activity. exception (number 7). in real address mode with the instruction at physical processor extension. The machine status word (MSW) records when a task belongs to the current task.

Table 7. Recommended MSW Encodings For Processor Extension Control T~49-17-15 processor extension context may belong to another task. . described in the 80286 Base Architecture section. address and a 16-bit offset.

Table 8. Real Address Mode Addressing Interrupts tions and Interrupts which indicate an addressing error. down can occur under two conditions: . fore attempting to execute the failing instruction (except include the interrupt vector. section on protected mode initialization tor a discussion around the stack segment when SP is not even. Struction is used to load the 24-bit Interrupt table base . preparation for the protected mode. associated Instructions.

integrity in muttl-processor systems. As in real address mode, protected mode uses 32-bit memory cycle and cause an exception or interrupt. use of this segment will cause a not-present exception. usage profiling, a necessity for virtual memory systems. Figure 15. Protected Mode Memory Addressing 1) for a segment containing a stack. The limit field for a

ADVANCED MICRO DEVICES e6E D M® 0257525 GO3444? O me AND Access Rights Byte Definition T-49-17-15 ., Bit oe Position Name Function TT és oo 7 Present (P) P= 1 Segment is mapped into physical memory. : P=0 No mapping to physical memory exists; base and limit are not used. Segment privilege attribute used in privilege tests. .

65 Descriptor Privilege eer

Level (DPL) 4 ‘Segment Descriptor (S) $=1 Code or Data segment descriptor : S=0 __Non-segment descriptor :

3 Executable (E) E=0 Data segment descriptor type Is:

2 Expansion Direction ED.=0 Grow up segment, offsets must be slimit. . (eo) ED=1 Grow down segment, offsets must be > limit. Data . . 1 ‘Writable (W) W=0 Data segment may not be written into. Segment Ws1 Data segment may be written Into. pe Field 3 Executable (E) E=1 Code Segment Descriptor type is: Definition 2 Conforming (C) C1 Code sagment may only be executed when CPL>DPL. Code 1 Readable (R) R=0 Code segment may not be read. Segment R=1 Code segment may be read, 0 ‘Accessed (A) A=0 Segment has not bean accessed. A= 1 Segment selector has been loaded into segmont register or Used by selector test instructions. Figure 16, Code and Data Segment Descriptors data segment descriptor is interpreted differently de- Figure 17 gives the formats for the special system data Pending on the ED bit (see Figure 16), segment descriptors. The descriptors contain a 24-bit base address of the segment and a 16-bit limit. The Accode segment (S = 1, E = 1) Hird be execute-only or access byte defines the type of descriptor, its state and execute/read as determined by the Readable (R) bit. Privilege level, The descriptor contents are valid and the Code segments may never be written Into and execute- segment is in physical memory if P= 1. if P=, the seg- only code segments (R = 0) may not be read. A code mentis not valid. The DPL field is oly used in Task Stara segment may also have an attribute called Conforming — Seqment descriptors and indicates the privilege level at (C). A conforming code segment may be shared by pro- which the descriptor may be used (see Privilege). Since grams that execute at different privilege levels. The ODPL the Local Descriptor Table descriptor may only be used reg eng coda segment detines the range of priv. by'a special privileged instruction, the DPL {eld fe wat {ege levels atwhich the segment may be executed (refer 2.4 Bit 4 of the asose byte is 0 to indicate that it is a to privilege discussion). ‘system control descriptor. The Type field specifies the System Segment Descriptors descriptor type as indicated in Figure 17. (S =0, Type 1-3) In addition to code and data segment descriptors, the protected mode 80286 defines system segment descrip- tors. These descriptors define special system data seg- ments which contain a table of descriptors (Local Descriptor Table Descriptor) or segments which contain the execution state of a task (Task State Segment Descriptor). oo SSS 1-86 80286 , |

0 a entry point. Task gates may only refer to a task state . ‘segment. Since task gates invoke a task switch, the des- . iT iF 3 to the stack of the called routine when a control transfer . changes privilege levels. The Word Count field is not . *Must bo sot to 0 for compatiblity with IAPX 386, used by any other gate descriptor.

2 Local Deseriptor Table Daseriptor “| Destination Selector oa “

3 Busy Task State Segment

1 Descriptor contents are valid " oT ° 03552-17

Figure 17. System Segment Format $ cinteropt Geis (S =0, Type = 4-7) 1 -Descriptor Contents are valid. control the entry point of the destination. Call gates are—=§ >.

The access byte format Is the same for all gate descrip- and selector Privilege (RPL), as shown in Figure-19. Level and specifies when this descriptor may be used by (refer to privilege discussion). Asegment descriptor cache register Is assigned to each . descriptors are automatically loaded (cached) intoaseg- §=£.—————___ OM . Figure 20. Descriptor Cache Registers

ADVANCED MICRO DEVICES 26€ D m@ 0257525 BOSW4s0 0 Hy . it The protected mode 80286 has a third descriptor table, . One table, called the Global Descriptor Table (GDT), —_ 23), used to define up to 256 interrupts. it may contain . contains descriptors available to all tasks. The otherta- —_ only task gates, interrupt gates and trap gates. The IDT . The LGDT and LLDT instructions loadthe base and limit reserved interrupts. Figure 21. Local and Global Descriptor Table Definitions 03552-19

‘8 e7 ° esaso-on 200088 to data and is considered the least trusted level. *Must be set to 0 for compatibility with IAPX 386, Descriptor Privilege T-49-17-15 . Figure 22. Global Descriptor Table and Interrupt Descriptor privilege is specified by the Descriptor Privi- Figure 23. Interrupt Descriptor Table Definition tor with RPL =0 imposes no additional restriction on its ments at privilege Level 3 regardless of the task’s CPL. Privilege APL Is generally used to verify that pointer parameters.

9 Passed to a more trusted procedure are not allowed to

which controls the use of privileged instructions and ac- _pointer testing Instructions). Privilege levels provide protection within a task. (Tasks cou .

ADVANCED MICRO DEVICES 26E D m™@ 0257525 O0344S2 4 mm AMD Descriptor Access and Privilege Control Transfer T-49~17-15 Validation Four types of control transfer can occur when a selector is loaded Into CS by a control transfer operation (see Determining the ability of a task to access a segment Table 9). Each transfer type can only occur if the opera- Involves the type of segment to be accessed, the instruc- _ tion which loaded the selector references the correct tion used, the type of descriptorusedandCPL,RPL,and descriptor type. Any violation of these descriptor usage DPL. The two basic types of segment accesses arecon- _rules (¢.g., JMP through a call gate or RET to a Task trol transfer (selectors loaded into CS) and data (selec- State Segment) will cause exception 13, {ors loaded into OS, ES, or 85). The ability to reference a descriptor tor control transfer is Data Segment Access also subject to rules of privilege. A CALL or JUMP in- . Instructions that load selectors into DS and ES must _Struction may only reference a code segment descriptor refer to adata segment descriptor or readable code seg- _ With DPL equal tothe task CPL or aconforming segment ment descriptor. The CPL of the task and the RPL of the with DPL of equal or greater privilege than CPL. The RPL selector must be the same as or more privileged (numeri- of the selector used to reference the code descriptor cally equal to or lower than) than the descriptor DPL. In ust have as much privilege as CPL. general, a task can only access data segments at the = RET and IRET instructions may only reference code same or less privileged levels than the CPL or RPL segment descriptors with descriptor privilege equal to or (whichever is numerically higher) to prevent a program —_ fags privileged than the task CPL. The selector loaded from accessing data it cannot be trusted to use. into CS is the return address from the stack. After the ‘An exception to the rule Is a readable conforming code “turn, the selector RPL is the task’s new CPL. If CPL gegen This type of code segment can be read from changes, the old stack pointer is popped after the return any privilege level. address. Ifthe privilage checks fail (@.g., DPL is numerically less Whena JMP or CALL references a Task State Segment than the maximum of CPL and RPL) or anincorrect type @8Criptor, the descriptor DPL must be the same or less of descriptor is reterenced (@.9., gate descriptor or exe- privileged than the task's CPL. Reference to a valid Task cute only code segment), exception 13 occurs. i the State Segment degcriptor causes a task switch (see segment is not present, exception 11 is generated, Task Switch Operation). Reference to a Task State Seg- ment descriptor at a more privileged level than the task's Instructions that load selectors Into SS must refertodata. CPL generates exception 13. segment descriptors for writable data segments. The descriptor privilage (DPL) and RPL must equal CPL. When an instruction or interrupt references a gate de- All other descriptor types or privilege level violation wilt Sriptor, the gate OPL must have the same or less privi- cause exception 13. A not-present fault causes excep- _[@0e than the task CPL. If DPL Is at a more privileged tion 12, fevel than CPL, exception 13 occurs. If the destination Table 9, Descriptor Types Used for Control Transfer Descriptor Descriptor Control Transter Types Operation Types Referenced Table Intersegment within the same privilege level UMP, CALL, RET, IRET* Cade Segment G@DTLOT Intersegment to the same or higher privilage level CALL Call Gate GDTLDT Interrupt within task may change CPL Interrupt Instruction, Trap or Interrupt (oT Exception, External Gate Interrupt Intersegment to a lower privilege level (changes task CPL)} RET, IRET* Code Segment G@DTLOT Task Switch CALL, JMP Task State Segment GOT CALL, JMP Task Gate GDTLDT RET Interrupt Instruction, Task Gate (oT Exception, External Interry “NT (Nested Task bit of flag word) =0 “NT (Nested Task bit of flag word) = 1 mA aL ss 80286 1-91

ADVANCED MICRO DEVICES 26E D m™@ 0257525 0034453 & mm AMD selector contained in the gate references a code seg- — interrupts within the task or calls that may change ment dascriptor, the code segment descriptor DPL must privilege levels can only transfer control through a be the same or more privileged than the task CPL. If not, gate at the same or a less privileged level than CPL Exception 13 is issued. After the contro! transfer, the to a code segment at the same or more privileged code segment descriptor DPL is the task’s new CPL. If level than CPL. T-49-17-15 the destination selector in the gate references a task coro o — return instructions that don’t switch tasks can only {oe Tank Sutich operat 4s automatically performed return control to a code segment at the same orless . privilegedlevel. — - The privilege rules on control transfer require: —_ task switch can be performed by a call, a jump oran interrupt which references either a task gate or task — JMP or CALL direct to a code segment (code . Segment descriptor) can only be to a conforming ‘state segment at the same or less privileged level. ‘segment with DPL of equal or greater privilege than CPL or a non-conforming segment at the same privilege level. Privilege Level Changes Any control transfer that changes CPL within the task —_ exception related to the stack ‘segment causes excep- causes a change of stacks as part of the operation. Initial —_ tion 12. values of SS:SP for privilege favels 0, 1, and2 are kept in . the task state segment (refer to Task Switch Operation), The IRET and POPF instructions do not perform some of During a JMP or CALL control transfer, the new stack __their defined functions if CPL is not of sufficient privilege pointer Is loaded Into the SS and SP registers and the (numerically small enough). Precisely, these are: Previous stack pointer is pushed onto the new stack. ‘© The IF bit is not changed if CPL>IOPL. ‘When returning to the original privilege level, its stackis * The IOPL field of the flag word is not changed if restored as part of the RET or {RET instruction operation. CPL>0. For subroutine calls that pass parameters on the stack No exceptions or other indication are given when these and cross privilege levels, a tixed number of words, a8 conditions ‘occur. ‘specified in the gate, are copied from the previous stack to the current stack. The intersegment RET instruction Table 10. Segment Register Load Checks with a stack adjustment value will correctly restore the eon pt ‘ception previous stack pointer upon return. Error Description Nurber Protection Descriptor table limit exceeded 13 structions that affect the CPU execution state (e.g., HLT) Segment descriptor not present 11or12 and code or data segments from improperusage. These 95> are a mechanisms are grouped under the term "protection" __Ptivlegerulesvlolated 13 and have three forms: Invalid descriptor/segment type segment register load: « Restricted usage of segments (9.9., no write allowed — Read only data segment load to SS - to read-only data segments). The only segments — Special control descriptor load to DS, available for use are defined by descriptors in the ES. ss Es 13 Local Descriptor Table (LDT) and Global Descriptor «Execute only segment load to DS, ES, Table (GOT). — Data segment load to CS * Restricted access to segments via the rules of — Read/Execute code segment load privilege and descriptor usage. to 8s * Privileged instructions or operations that may only be executed at certain privilege levels as determined by the CPL and 1/0 Privilege Level (IOPL). The (OPL Is defined by bits 14 and 13 of the flag word. . These checks are performed for all instructions and can be split into three categories: segment load checks (Ta- ble 10), operand reference checks (Table 11), and privi- leged instruction checks (Table 12). Any violation of the tules shown will result in an exception. A not-present -.s SSS 1-92 80286

Table 11. Operand Reference Checks Special Operations T-49-17-15 ce Exception Task Switch Operation . . — — sbyexecuting an inter-segment JMP or CALL instruction . descriptor in the GDT of LDT. An INT n Instruction, ex- . Table 12. Privileged Instruction Checks switch operation by selecting atask gate descriptorinthe . LIDT, LLOT, LGDT, LTR, LMSW, must be > 0028(H). ‘The 80286 detects several types of exceptions andinter- _ 'aded with a new selector. Table 13. Protected Mode Exceptions

10 Invalid task state segmant Yes Yes Yes

12 Stack segment overrun or segment not present Yes Yest Yes

13 Gonaral protection Yes No Yos

1. When a PUSHA or POPA Instruction attempts to wrap around the stack segment, the machine state after the exception

saved SP being either 0000(H), 0001(H), FFFE(H), or FFFF(H).

1. All these checks are performed for all instructions and can be split into three categories: Segment Load Checks (Table

ADVANCED MICRO DEVICES 26— D M@@ 0257525 OO344SS T mm AND NT bit of the new task is set by CALL or INT initiatedtask The task state segment Is marked busy by changing the switches. An Interrupt that does not cause atask switch —_descriptor type field from Type 1 to Type 3. Use of a will clear NT, NT may also be set or cleared by POPF or —_selector that references a busy task state segment IRET instructions. causes Exception 13. SSS “49-17-15 lable Task St . a ‘cease cae i ‘Switch Operation. caaipinieamnenen |

1 Fosmnaame | TO a

a on | re ask Switch, tte FL 4 tLe TT 13 1 to. —4 a A Byte a} Ofset [ossatecm ——__—*iao-) [P| Descinton a | [1] Bete andi Flare Vaid. | | -esséour fm |? Baretta” | | esseocoe a a [se te | carom ee a ee | a State Segment] [cx do [reves dis [ssmens ~~] a e | es Stacks [ermar do | rane P e 03552-23 Figure 25, Task State Segment and TSS Registers eee 1-94 80286

use of a processor extension after a task switch by caus- . an ESC or WAIT Instruction if TS=1 and a processor CS thereafter. The initial CS:IP value of FFOO:FFFO. Pointer Testing Instructions without changing CS. selactor or segment will cause an exception, real address mode. Table 14. Pointer Test Instructions protected mode state assumed by software, execute a Selector bythe salactorcanbewritten. 796 Standard MULTIBUS®. Bealster, the dascriptor access rights signals.

ADVANCED MICRO DEVICES 28— D m@ 0257525 0034457 3 mm AND : T-49-17-15 : can provide the timing and electrical power drive levels —_essor clock is composed of two system clock cycles required for most system bus interfaces including the — named phase 1 and phase 2. The 82284 clock generator MULTIBUS, output (PCLK) identifies the next phase of the processor clock, (See Figure 26.) Physical Memory and 1/O Interface Sixtypes of bus operations are supported: memory read, addressed in protected mode. One megabyte can be mum rate of one word per two processor clock cycles, addressed in real address mode. Memory is accessible . " as bytes or words. Words consist of any two consecutive The 80286 bus has three basio States: dle (Ti), send . bytes addressed with the least significant byte stored in status (Ts), and perform command (To), The 80286 CPU the lowest address, also has a fourth local bus state called hold (Th). Th : indicates that the 80286 has surrendered control of the Byte transfers occur on either half of the 16-bit local data bus. Even bytes are accessed over Dz-o while odd bytes bene {0 another bus master In response to a HOLD are transferred over Dis, Even-addressed words are * transferred over Dis in one bus cycle, while odd-ad- —_ Each bus state is one Processor clock long. Figure 27 dressed words require two bus operations. The first shows the four 80286 local bus states and allowed tran- transfers data on Dis, andthe secondtransfersdataon sitions. 7-0, Both byte data transfers occur automatically, trans- Parent to software. Bus States Two bus signals, Ao and BHE, control transfers overthe The idle (T) state Indicates that no data transfers are in lower and Upper halves of the data bus. Even address _PrOGress or requested. The et active state, Ts, is sig- byte transfers are indicated by Ao LOW and BHEHIGH. _alled by either status line St or $0 going LOW also Odd address byte transfers are indicated by Ao HIGH —_entifying phase 1 of the processor clock. During Ts, the and BHE LOW. Both Ao and BHE are LOW for even °Mimand encoding, the address, and data (for a write .ddress word 1 ransters. operation) are available on the 80286 output pins. The a 0 * 82C288 bus controller decodes the status signals and The VO address space contains 64K addresses in both generates MULTIBUS-compatible read/write command modes. The VO space is accessible as either bytes or and local transceiver control signals. words, as is memory. Byte-wide peripheral devices may be attached to either the upper or lower byte of the data Monroy ore doren remand, Toe bus coos bus. Byte-wide /O devices attached to the upper data di spol luring Tc, either transferring read data to the CPU or byte (Diss) are accessed with odd VO addresses. accepting write data. Te states may be repeated as often Devices on the lower data byte are accessed with even as necessary to assure sufficient time for the memory or VO addresses. An interrupt controller such as the 8259A, VO device to respond. The READY signal determines must be connected to the lower data byte (Dr-o) for pond. lgnal de proper ratum of the interrupt vector. whether Tc Is repeated. A repeated Te state is called a . wait state. Bus Operation During hold (Ts), the 80286 will float all address, data, The 80286 uses a double-frequency system clock (CLK —_and status output pins, enabling another bus master to input) to control bus timing, All signals on the local bus —_use the local bus. The 80286 HOLD input signal is used are measured relative to the systemCLK input. The CPU _to place the 80286 into the Th state, The 80266 HLDA divides the system clock by 2 to produce the Internal —_ output signal indicates that the CPU has entered Th. processor clock, which determines bus state. Each proc- SSMS ‘One Processor Clock Cycle: One Bus T State- “Phase 1 Phase 2 of Procossor-—ele— of Processor . Glock Cycle Clock Cycle ox \\ NN ‘One System (7 Clock Cyclo —| ru_\\f OC CS 03852-24 Figure 26, System and Processor Clock Relationships a SSS 1-96 80286 . |

ADVANCED MICRO DEVICES 26€ D m™@ 0257525 0034459 7 Mm AND Bus Control Signals Command slay lows an {rerease of sadrese or write . lata set-up time to system bus command active for any The 820288 bus controller provides control signals: ad- bus operation by delaying when the system bus com- dress latch enable (ALE), Read/Write commands, data mand becomes active. Command delay is controllad by transmivrecelve (DT/R)< and data enable (DEN) that the gacaea CMDLY input. After Te, te bus controller control the address latches, data transceivers, write en- samples CMDLY at each failing adge of CLK. If CMDLY able, and output enable for memory and VO systems. ig HIGH, the 82288 will not activate the command sig- The Address Latch Enable (ALE) output determines nal. When CMDLY is LOW, the 82C28 will activate the when the address may be latched. ALE provides atleast command signal. After the command becomes active, ‘one system CLK period of address hold time from the _the CMOLY input Is not sampled, T-49-17-15 ‘end of the previous bus operation until the address for When a command is delayed, the available response . the next bus operation appears at the latch outputs. This time from command active to return read data or accept adress hold time Is required to support MULTIBUS and writg data is less. To customize system bus timing, an common memory systems. address decoder can determine which bus operations The data bus transcelvers are controlled by 82C288 out- require delaying the command. The CMDLY input does Puls Data Enable (DEN) and Data TranemtiRocahig not affect the timing of ALE, DEN, or DT/R. (DT/R). DEN enables the data transceivers while DT/ controls transceiver direction. DEN and OT/Rare timed — [OU"e delaying ine teadeornanaed ont oytios act to prevent bus contention between the bus master, data cycla N~1 and no delay for cycle N, and example 2 bus transceivers, and system data bus transceivers. shows delaying the read command one system CLK for Command Timing Controls cycle N—1 and one system CLK delay for cycle N. ‘Two system timing customization options, commandex- Bus Cycle Termination tension and command delay, are provided onthe 80266 a, maximum transfer rates, the 80286 bus alternates focal bus. between the status and command states. The bus status Command extension allows additional time for externai_ Signals become inactive after Ts so that they may devices to respond to a command and is analogous to the coupioten ot ane of the next bus operation after troltnedurationat arabe ae cieemaljoaiecancon- ition of Te exists onthe 80280 ocal bus. The bos rol juratton of any bus operation such that the opera- a tlon is only as long as necessary. The READY input sig- Master and bus controller enter Te directly after Ts and nal can extend any bus operation for as long as gontinue executing Te cycles until terminated by necessary. . oe SSSSSSSSSSSSSSSSSSSSsSSSSSSsssFsFesesssssSSSeF 1-98 80286

ADVANCED MICRO DEVICES 2s— D mm@ 0257525 0034460 3 mm AND sad oye T-49-17-15 . Read Cyde N=1 lee fe a i-— Tr re i +—— T. —s $2 ran road | at ml ot ria Tn Proe Aerts al Adée NY DK ange PKS OF ae aw agai Vat . Cy] a Li ¥ a Le Ke py VA e \\__\\_\\ Eo . . a OS ee 03562-27 Figure 29, CMDLY Controls and Leading Edge of the Command READY Operation ning of each Tc cycle by 82284 Synchronization logic. The current bus master and 82C288 bus controller terml- Vane botore bioalecstan kb hates nate eachbus operation simultaneously toachleve max — Controller. mum bus bandwidth. Both are informed in advance by ~ READY active which identifies the last To cycle of the © ARDYorARDYEN must be HIGH at the end of Ts. ARDY Current bus operation. The bus masterandbus controller © cannot be used to terminate bus cycle with no wait must see the same sense of the READY signal, thereby _ status. . requiring READY be synchronous to the system clock. Each ready input of the 82284 has an enable pin Synchronous Ready (SRDYEN and RADYEN) to select whether the current READY bus operation will be terminated by the synchronous or ‘The 82284 clock generator provides synchroni- asynchronous ready. Either of the ready inputs. may zation from both synchronous and asynchronous terminate a bus operation. These enable inputs are ac- Sources (See Figure 30). The synchronous ready input tive low and have the same timing as their respective (SRDY) of the clock generatoris sampled with the falling ready inputs, Address decode logic usually selects aeas of CLK atthe endofphase 1 of eachTe. Thestateof whether the current bus operation should be terminated Is then broadcast to the bus master and bus con- hy ARDY or SRDY. troller via the READY output line. Data Bus Control Asynchronous Ready Figures 31, 32, and 33 show how the D1/A, DEN, data Many ‘systems have devices or subsystems that are bus, and address signals operate for different combina- asynchronous to the ysiem Clock: Asa raul, their tions of read, write, and idle bus operations. DT/R goes gay ‘outputs cannot be guaranteed to meet the . HIGH RDY set-up and hold time requirements. The 82284 Bolen curing aa bananas ait ins HIG asynchronous ready input (ARDY) Is designed to accept " ‘such signals. The input Is sampled at the begin- ee SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSFFFeFee 80286 1-99

Notes: 1. SRDYEN is active LOW.

1. tt SADYEN is HIGH, the state of SADY will not affect READY.

Figure 30. Synchronous and Asynchronous Ready phase of Ts. The delay in write data timing allows the shown in Figure 34. data busdoes not enterthree-state OFF between Teand active. The 80286 local bus may be used for several functions: antee ARDY will terminate the cycle. This section describes local bus activities which have _ edge of RESET unless the 80286is in the Halt condition. HOLD and HLDA allow another bus master to gaincon- _ CLKs after the trailing edge of the RESET pulse.

Figure 31. Back-to-Back Read-Write Cycles with the following ASM-286 assembly instructions; numerically odd physical address. Lock will not be shown active during the last cycle tobe —_—Struction queue. wait-states inserted. For Interrupt-Acknowledge cycles, ina code segment. ‘The 80286 Bus Unit (BU) will fetch instructions ahead of beyond the last full instruction in the code segment. the 6-byte prefetch queue are empty. to execute it causes exception 13.

moet! wrel eral orel wheal wo el oel oF el oe el oPel .

8 BF in ee ne it

1. Addrass, MIO and COD/INTA may start may start floating during any TC, depending on when internal
2. BHE and COOK may start floating after the end of any TC, depending on when internal 80286 bus arbiter
3. The earliest HOLD f time is shown which will always allow a subsequent memory cycle it pending.

and other machine status (i.e, Interrupts, Waits, Lock, etc.). Figure 34. MULTIBUS Write Terminated by Asynchronous Ready with Bus Hold

ADVANCED MICRO DEVICES 266 D M@ 0257525 0034465 2 mm AND SE ee . T-49-17-15 . Processor Extension Transfers (Highest) Any transfers which assert LOCK either ex- ‘ The processor extension interface uses VO port ad- plicitly (via the LOCK instruction pretix) or : Gresses 00F8(H), and 0OFA(H), and 0OFC(H) which are implicitly (Le., segment descriptor access, ee Part of the I/O port address range and is a reserved area, Interrupt acknowledge sequence, or an An ESC Instruction with EM=0 and TS=0 will perform XCHG with memory). '/O bus operations to one or more of these /O port ad- dresses independent of the value of IOPL and CPL. bier btbpet cde word etone SC instructions with memory references enable the CPU to accept PEREQ inputs for processor extension Local bus request via HOLD input. . operand transfers. The CPU will determine the operand Processor extension data operand transfer starting address and readhwrite status ot the instruction. via PEREQ input. For each operand transfer, two or three bus operations, ‘one word transfor with /O port address OOFA(H), and Data transfer performed by EU as partof an ‘one of two bus operations with memory are performed, instruction, Three bus operations are required for each word ‘Oper- (Lowest) An instruction prefetch request from BU. and aligned on an odd byte address. The EU will inhibit prefetching two proces- Sor clocks in advance of any data transfers Interrupt Acknowledge Sequence to minimize waiting by EU for a prefetch to Figure 35 illustrates an interrupt acknowledge: sequence finish, performed by the 80286 in response to an INTR: input. An interrupt acknowledge sequence consists of two INTA bus operations. The fist alows a master 259A Pro- Halt or Shutdown Cycles grammable Interrupt Controller (PIC) to determine which, if any, of its slaves should return the interrupt ta sep externaly Indicates aloe Shutdown cond vector Anelght-bitvectoris read by the 80286duringthe tons as a bus operation. These conditions occur due toa second INTA bus oy " HLT Instruction or multiple protection exceptions while eration to select an interrupt handler it instruction. Ahatt or shutdo foutine trom the interrupt table. attempting to execute one instruction. A halt or shutdown: bus operation is signalled when St, SO and COD/INTA The Master Cascade Enable(MCE) signalofthe82C288 are LOW and M/I0 is HIGH. At HIGH indicates halt, and 's used to enable the cascade address drivers, during Ai, LOW indicates shutdown. The 820288 bus controller INTA bus operations (see Figure 35), onto the local ad- does not issue ALE, nor is READY required to terminate dress bus for distribution to slave interrupt controllers via a halt or shutdown bus operation. the system address bus. The 80286 emits the LOCK ; signal (active LOW) during Ts of the first INTA bus opera- _Ouring halt or shutdown, the 80286 may service PEREQ tion. A local bus “hold” request will not be honored until of HOLD requests. A processor extension segmentover- the end of the second INTA bus operation. fun exception during shutdown will inhibit further service of PEREQ. Either NMI or RESET will force the 80286 out Three Idle processor clocks are provided by the 80286 of either halt or shutdown, An INTR, #f interrupts are between INTA bus operations to allow forthe minimum — enabled, or a processor extension ‘segment overrun ex- INTAto INTA time and CAS (cascade address) out delay ception will also force the 80286 out of halt, of the 8259A. The second INTA bus operation must al- ways have at least one extra Te state added via logic +4 System Configurations controlling READY, Azo-Ao are in three-state OFF until The versatile bus structure of the 80286 microsystem, after the first Te state of the second INTA bus operation. with a full complement of support chips, allows flexible This prevents bus contention belween the cascade ad- configuration of a wide range of systems. The basic con- dress drivers and CPU address drivers. The extra To figuration, shown in Figure 36, is similar to an |APX 86 State allows time for the 80286 to resume driving the maximum mode system. It includes the CPU plus an address lines for subsequent bus operations, 8259A interrupt controller, 82284 clock generator, and the 820288 Bus Controller. The IAPX 86 latches (29843 Local Bus Usage Priorities and 29845) and transceivers (29833 and 29863) may be The 80286 local bus Is shared among several internal __used in an 80286 microsystem. units and external HOLD requests. Incase of simultane- ous requests, their relative priorities are: OO 1-104 80286

1. First INTA cycle should have at least one wait state inserted fo meet 8259A minimum INTA pulse width.
2. Second INTA cyclo must have at least one wait state inserted since the CPU will not drive A,,-A,, BHE, and LOOK
3. TOCR is active for the first INTA cycle to prevent the 82289 from releasing the bus between INTA cycles in a
4. Azs-Ay exits three-state OFF during 92 of the second Te in the INTA cycle,

Figure 35. Interrupt Acknowledge Sequence

1 Extension K44——— VOU eater

Figure 36. Basic 80286 System Configuration (NPX) uses this interface. The IAPX 286/287 has all the between interrupt, 1/0, code and data bus cycles. dress propagation during the data transfer for the previ- operation which uses the MULTIBUS.

ADVANCED MICRO DEVICES 28£ D W™ 0257525 OO344b9 T mm AMD ; T-49-17-15 . . pt eos s rn a R On| AaAy . ss Lf sex FAS RS : Line CASI ee a i Ce] co I ABA ICO DRAM Ce rN al amgoc2 ee | Laat 56 62284 CLK mE [ak2 szczes 2 > Bus 16. Figure 38, 80266 Interface with the Am2968 Dynamic Memory Controller 09852-96 SS Table 15, 80286 Systems Recommended Pull-up Resistor Values

80286 Pin and Name | PulrupValue Ss Purpose

5-55 20K 10% pals peiogsens PEACR acive dog 60286 6-PEACK 53-ERROR Puil ERROR and BUSY inactive when 80287 20KQ+ 10% Rot present (or temporarily removed from 54-BUSY sockety Pull READY inactive within required minimum 63-READY 910Q45% time (C; = 150 pF, In S 7mA). OO 1-108 80286

Register Mode/Memory Mode with Displacement Length . Direction is to RegisterDirection Is from Register . A. Short Opcode Format Example 03552-37 . . Figure 39. 80286 Instruction Format Examples

ADVANCED MICRO DEVICES 26E D M@ 0257525 0034471 & mm AMD

80286 INSTRUCTION SET SUMMARY Real Address ModeOnly =» T-49-17-15

Instruction Timing Notes 1. Thisis aprotected mode instruction. Attempted exe- The Instruction clock counts listed below establish the _-—_—cution in real address mode will resutt in an unde- maximum execution rate of the 80286. With nodelaysin _ fined opcode exception (6). bus cycles, the actual clock count of an 80286 program 2 Asegment overrun exception (13) will occurifa word will average 5% more than the calculated clock count, operand reference at offset FFFF(H) Is attempted, due to instruction sequences which execute faster than . . they can be fetched from memory. 3. This instruction may be executed in real address ‘mode to initialize the CPU for protected mode. To calculate elapsed times for instruction ‘sequences, . ‘multiply the sum of all instruction clock counts, as listed 4. The IOPL and NT fields will remain 0. in the table below, by the processor clock period. An nanoseconds and requires an 80286 system clock (CLK . input) of 16 MHz. Either Mode Instruction Clock Count Assumptions 6 treason may occur, depending on the value of 1. The instruction has been prefetched, decoded, and _ 's ready for execution. Control transfer instruction 7. LOCK is automatically asserted regardless of the clock counts include all time required to fetch, de- Presence or absence of the LOCK instruction prefix, code, and prepare the next instruction for execution. 8. LOCK does not remain active between all operand 2. Bus cycles do not require wait states. transfers, 3. There are no processor extension data transfer or Protected Virtual Address Mode Only ‘ocal bus HOLD requests. 9. A general protection exception (13) will occur if the 4. ing i ion. memory operand cannot be used due to either a No exceptions occur during instruction execution. segment limit or access rights violation. If a stack Instruction Set Summary Notes ‘segment limit is violated, a stack segment overrun Addressing displacements selected by the MOD field are exception (12) occurs. Not shown. If necessary they appear after the instruction 10. For segment load operations, the CPL, RPL, and fields shown. DPL must agree with privilege rules to avold an ex- Above/below refers to unsigned value ception. The segment must be present to avoid a 0 unsigy not-present exception (11). If the SS register Is the Greater refers to positive signed value destination, and a segment-not-present violation oc- Less refers to less positive (more negative) signed curs, a stack exception (12) occurs. values 11. All segment descriptor accesses in the GDT or LDT iftd=1 then to register; if d = 0 then from register made by this instruction will automatically assert itw=1 then word instruction; if w=0 then byte TOCK to maintain: descriptor integrity in multiproces- instruction sor systems, reno ren jeg immediate detatoformthe 9 ip GALL INT. RET, IRET instructions referring to = ian- another code segment will cause a general protec- as=0 orto 1 er fe son tion exception (13) if any privilege rule is violated. x= don't care 13.A_ general protection exception (13) occurs if zs used for string primitives for comparison with ZF CPL#0. LAG It two clock counts are given, the smaller refers toa 14. A_general protection exception (13) occurs if register operand and the larger refers to a memory oper- CPL>IOPL. and. 15. The IF field of the flag word is not updated if *= add one clock if offset calculation requires sum- CPL>IOPL. The IOPL tleld Is updated only i ming 3 elements CPL=0. N= number of times repeated . 16. Any violation of privilege rules as applied to the se- m= number of bytes of code in next instruction lector operand do not cause a protection exception; Level (L)—Lexical nesting level of the Procedure father, the instruction does not return result and the 4 . zero flag Is cleared. The following comments describe Possible exceptions, side effects, and allowed usage for instructions in both _17. If the starting address of the memory operand vio- operating modes of the 80286. lates a segment limit, or an invalid access Is at- —J—-- 1-110 80286

ADVANCED MICRO DEVICES 26— D M@@ 0257525 0034472 T mM AND tempted, a general protection exception (13) willoc- 18. The destination of an INT, JMP, CALL, RET, or RET : cur before the ESC Instruction Is executed. A stack Instruction must be in the defined limit of a code segment overrun exception (12) will occur if the segment or a general protection exception (13) stack limit Is violated by the operand's starting ad- will occur. dress. If a segment limit Is violated during an at- T-49-17-15 tempted data transfer, then a processor extension segment overrun exception (8) occurs. 80286 1-111

ADVANCED MICRO DEVICES 26—E D ml Ges7ses 0034473 1 Me AND J-49-17-15 ABSOLUTE MAXIMUM RATINGS OPERATING RANGES functionality of the device is guaranteed. Strasses above those listed under ABSOLUTE MAXI- MUM RATINGS may cause permanent device failure. . Functionality at or above these limits Is not implied. Ex- . posure to absolute maximum ratings for extended perl- ‘ods may affect device reliability. OT DC CHARACTERISTICS (Vcc=5V +5%, Tesse =0 to +85° C) *namete [own | rus [om |e | “ Vi | Input LOW Voltage | 3 | 8 v Vin___| Input HIGH Voltage Veo+.5 v Vie [CLK input Low Votage [5 Vie [CLK input HIGH Voltage [98 eo Vox [Ouiput LOW Votlage [Tas mA 8 Vos [Output HIGH Vollage TT [ov==400 pA a [input Leakage Current [0 Ws Vas Veo | tk ho [ Output Leakage Current [0.48 Vs VarsVes—| | si0 A lee_[ Supply Current (tum on, 6°6)[Notet —‘|_} 600] —ma Geox [CLK input Capactancs [Feat Me |] 27. Cw { Other input Capacitance | Fo=t MMe || 197 pF Co [Input/Output Capacitance [ Fe=t Mie |_| 29] pF kof Output Leakage Current" 0 V & Voor s 045 V [| at] mk [ry Input Sustaining Current on Va = OV HA ten __[Input CLK Leakage Current 045 s Vs Ves |__| si] “pa en [Input CLK Leakage Current [0 Vs Vw s 0480 | [sa] “Ba Note: Low temperature is worst case, 1-412 80286

ADVANCED MICRO DEVICES 26— D M@@ 0257525 0034474 3 mm AMD SWITCHING CHARACTERISTICS T-49-17-15 Veo=+5V45%, Tense =0° to +85° C AC Timings are referenced to 0.8 V and 2.0 V points of signals as illustrated in datasheet waveforms, unless otherwise noted. Cin [ecm Fat Parameters| Description Test Conditions | Min. | Max. | Min.| Max. | Unit 1__[_ systemcloacicixrerod | | a | 125 | so] 125 | ns 2 | System Clock (CLK)LOWTime | attov | 15 | 100 | 12] 109 | ns . 3 [System Clock (CLK) HIGH Time | ata6v_ | 25 | 110 [te [113 [ns 17__ | System Clock (CLK) Riso Time | tovioaev [| if [8 [ns . 18 | SystemClock (CLK) Falltime | 36vio1.ov [| io] [8 [ns ‘4 | Asynchronous Inputs Setup Time | Notet (| 20 | | aot [ns S| Asynchronous InputsHoldTime | Notet | _20 || 20] [ns 6 | RESETSetuptime | Tt TT og ins 7 | ResetHoldtime | TT sf ns 8 | Read Data Setup Time PT to Pa ns g | Read DataHold Time a ns jo__|_ReAbYSewptime | Te ns v1 | READYHoldTime Ts as ns 12 | Status/PEACK Valid Delay [ Note2,Notes [1 | 40] -| - [ns Tea | SiasiPEACK Actve Delay | Note2,nows [== [af fre 12> |" Stalus/PEACK inactive Delay | Note2,Note3_ | - | =| 1] 30 | ns 13 |" Address ValidDelay | Note 2,Note3 [1 [eo] 1] 35 [ns 14 | Write Data Valid Delay | Note 2,Note3_ | o | sof of” 30 [ns 15 | Address/Status/Data Float Delay | Note2,Note4 | o | so] ol 47 [ns 16 | HUDAValidDelay | Note 2,Notos [oo | so] of 47 | ns

19 Address Valid to Status Note 3, Note 5, 27 ns

Notes: 1. Asynchronous inputs are INTR, NMI, HOLD PEREQ, ERROR, and BUSY. This specification is given only for testing purposes, to assure recognition at a specitic CLK edge. 2. Delay from 1.0V on the CLK to 0.8 or 2.0V or float on the output as appropriate for valid or floating condition, 3, Output load: C, = 100 pF. 4, Float condition occurs when output current Is less than |, in magnitude, going inactive reaching 0.8 V. 6. Forload capacitance of 10 pF on STATUS/PEACK lines, subtract typically 7 ns for 8 MHz spec, and maximum 7 ns for 410 MHz spec. 80286 1-113

ADVANCED MICRO DEVICES . e6€ D M@™@ 0257525 0034475 5 mm AMD SWITCHING CHARACTERISTICS (continued) T-49-17-15 Veo = +5 V+5%, Tease = 0° to +85°C AC Timings are referenced to 0.8 V and 2.0V Points of signals as illustrated in datasheet waveforms, unless otherwise noted. |__42.5MHz 7 6 MHz | 1_|' sysemGiock(cunpreiod [a0 | 15) a1 | tas] os 2 | System Clock (GLK) LOW Time | at oV | 14] 112 10 T110] ns . 3 | System Glock (GLK) HIGHTime_| at 3.6V | 13 | 114] 12 1181] ns. 17 _|' "System Clock (CLK) Rise Time [ 1.0V tov] | al af Tre 18 [System Clock (CLI) Fall Time | 36viot.ov | | a a] —] ns 4 [ Asynchronous inputs Setup Time | Nolet | 18. | | as] ] ns 5 | Asynchronous Inputs Hold Time _| inchronous Inputs Hold Time Hee fs ns s_ | RESETSeupTime | 4 ni 7 _{ nesetHoldtims ds | a 8 | Read Data Setup Time | | a ns 9 | Read Data Hold Time [oT ts 10__| "READY Setup Time "fe PY [1s | [ns M1 [READY Hold Time a 12 |’ Siatus/PEACK Valid Delay | Note2,Now3 | _- | =| a] a8] te t2a [_Status/PEACK Active Delay | "Note 2,Note3 | a | tala} 181 ns. 2p | "Siatus/PEACK inactive Delay | Note 2, Noto | 3 | 20] 1] “20 | ~ne 13 [Address Vaid Delay | Note 2, Notes | 1] aa] 1} 20] ns 14 [Wille Data Vad Delay | Note 2,Note3 | 0 | 30] oT 2a ns 15 | Address/Status/Data Float Delay | Note 2, Note 4 | 0 | a2] 0 | sa] ns 16 | HLDAVald Delay | Note 2, Note3 | 0 | 25] 0 | 98] ns

19 Address Valid to Status Note 3, Note 5, ns

Notes: 1. Asynchronous inputs are INTR, NMI, HOLD PEREQ, EAR, and BUSY. This specification is given only for testing Purposes, to assure recognition at a specific CLK edge. 2. Delay from 1.0¥V on the CLK to 0.8V ot 2.0V or float on the output as appropriate for valid or floating condition, 3. Output load: C, = 100 pF, 4. Float condition occurs when output current is loss than I,, in magnitude. 5. Delay measured from address either reaching 0.8 V or 2.0 V (valid) to status going active Teaching 2.0 V or status going inactive reaching 0.8 V. : 68. For load capacitance of 10 pF on STATUS/PEACK lines, subtract ‘typically 7 ns for 8 MHz speo, and maximum 7 ns for

10 MHz spec,

Note: 7. AC Test Loading on Outputs Lt 09852-39 4.0V 3.6V 3.6V cLK ~ Xa 1.0V 1.0V: 0.45 V 0365240 Note: 8. AC Drive and Measurement Points-CLK Input 1-114 80286 ) :

ADVANCED MICRO DEVICES 28£ D M@@ 0257525 OO3447b 7 mm AMD : T-49-17-15 4.0V CLK Input 3sv 36V 24V hew toeay Device 20Vv Output osv 03852-41 Note: AC Setup, Hold and Delay Time Measurement—General 80286 1-115

ADVANCED MICRO DEVICES 28E D Mm@ 0257525 0034477 9 mm AND T-49-17-15 SWITCHING WAVEFORMS Major Cycle Timing Read Cycle illustrated Write Cycle Illustrated with zero walt states with one wait state Sox Tipe ol. ok te P % Tete erate EE (2) @® m0 S erat] [tlc t— | | | fi hyp OK | nat Xana | Xa “es ef | ' ety | y_] BRE TTT EEX | anes Kf ae ae lo} [ @ D904 a tT [vamos] SS ro SS Etat LL Zz i. a SASSNNRNSNNNS NS Mz eed oe SNNSSSNINNNNAAND oO 7 ae ee o ee beter cu SSIS TT PS, eT . | afr | |= e- fer HT . a ® Jal 2 Lo oon Note: The modified timing is due to the CMDLY signal being active, 0386-42 * eee 1-116 80286

ADVANCED MICRO DEVICES 26— D ml gas7s2s 0034478 O mm AMD SWITCHING WAVEFORMS (continued) T-49-17-15

80286 Asynchronous Input Signal Timing 80286 Reset Input Timing and Subsequent

‘Bus Cycle Type Tk Vou o | 6 Tr ox Vow . poLK ® cK (S00 Note 1) a of ta i) fiote 1) . 2) Rosot INTR, NMI, HOLD, PEREG LINZ | XE. (See Noto 2.) Ey Vos , Te ee DK KEKE oux A Ve (0) 3682-49 ale tefuts Notes: 1. PCLK indicates which processor cycle phase will Reset EA c0ss2-44 occur on the next GLK. PCLK may not indicate the correct phase until the first bus cycle is performed, 2. These inputs are asynchronous. The setup and Note: When RESET meets the set-up time shown, the next hold times shown assure recognition for testing CLK will start or repeat 91 of a processor cycle. purposes, Exiting and Entering Hold En Bus Cycle Type Ww Tort, i 7 CLK ¥¢ Va © ® HUDA R (e) genoa) —o| © ® (S00 Note a) : or : aaa | rs @ 5 sc=@ =o FER OT : s einai ——— | (Seotiae 1) DHE LOCK ® © fect —— SO Eg MD, ” {See Note 2.) cone wom 6 Dey mmm nnn KEE Opn 03652-45 Notes: 1. These signals may not be driven by the 80286 during the time shown. The worst case in terms of latest float time is shown. 2. Tho data bus will be driven as shown if the last cycle before T, in the diagram was a write Ty. 3. The 80286 floats its status pins during T,. External 20 kO. resistors keep these signals high (see Table 15). 4, For HOLD request set-up to HLDA, refer to Figure 34, 5. BHE and LOCK are driven at this time but will not become valid until T,. 6. The data bus will remain in three-state OFF if a read cycle is performed. 80286 1-117

ADVANCED MICRO DEVICES 26£ D M™ 0257525 0034475 2 mm AMD SWITCHING WAVEFORMS (continued) T-49-17-15

80286 PEREQ/PEACK Timing Required PEREQ Timing for One Transfer Only

¥ Tt Te Te Ts Te ad ouK Va. > VO Read tp. ox to may orm ie tp 00 reo . —_ [7 Mavs re, [7 iitetimoneri ie [7 | arsine a Act S of seventeen PERER’ (oo Note2) (o) PEREO SSS PLL LDL ELE 03552-46 Assuming word-aligned memory operand; if edd-oligned, 80286 transfers toriom memory byte-at-a-time with two memory cycles. Notes: 1. PEACK always goes active during the first bus operation of a processor extension data operand transfer sequence, The first bus operation will be ether a memory read at operand addross or VO read at pont addross OOFA(H). 2. Toprevent a second processor extension data operand transfar, the worst caso maximum tim (shown above) Is:3x 1-11’ max~4 min. The actual, contiguration dependent, maximum timais:3x 1-11 max—4 min+ Ax 2x 1, Als the number of extra T. states added to either the first or second bus operation of the processor extension data operand transfer sequence, 1-118 80286

ADVANCED MICRO DEVICES 28— D M@™@ 0257525 0034480 9 mm AMD Initlal 80286 Pin State During Reset T-49-17-15 Bus Cycle Type arg tk i t ck va (See Note 2.) @) Q 2) US _ LE | Atleast y] | aS: 16 CLK Periods co . ae o~| PERK Unknown ee ee, | | toy, Neh Unknown re a | | te coomMTR Unknown nS Oa Corr Unknown a, En ® (See Note 3.) DL ALS he ® hold is NOT active (See Note 4.) HLOA Unknown 09729-47 Notes: 1. Set-up time for RESET T may be violated with the consideration that $1 of the processor clock may begin one system CLK period later. 2. Set-up and hold times for RESET | must be met for proper operation, but RESET | may occur during $1 or ¢2. ‘3. The data bus is only guaranteed to be in three-state OFF at the time shown, 4, HOLD Is acknowledged during RESET, causing HLDA to go active and the appropriate pins to float. If HOLD remains active while RESET goes inactive, the 80286 remains in HOLD state and will not perform any bus accesses until HOLD is deactivated. SSS 80286 1-119

ADVANCED MICRO DEVICES 26— D M@ 0257525 0034482 O mm AMD 80286 INSTRUCTION SET SUMMARY T-A9-17-15 . Protected Protected soe Virtual mene DATA TRANSFER MOV=Move: vols Register to Reglster/Momo 23° 2st 9 . se Rogistor/Memory to Register] 1000101 w| mod reg rim | 25" 28° 9 . Immodaw toregiton — [1100011») medoooun| daa [aa twoi] ax | ox ° Immodiatotoregister [101 1wrog [data ‘[dataitw=1 | 2 2 so Money toaccumiaer [1010000%] eatiow | adnigh —] s| os 0 ‘Accumulator to memory 8 3 ® Registermemory to 2st 17,19° 9,10,14 ‘Segment register Segment ragister to 23° 23° 8 registerimemory \\ PUSH=Push: ‘ Memory [rrstii ri [modt 00m s s ° Rogister 3 3 9 Segment register 3 3 9 Gi | OKIE ET Lr Cc CCL A nae ee = AES eee, : Memory [10001111 [mosooorm | s s 9 Ragister [0101 treo | 5 5 ® ‘Sogment register {reg 201) 5 20 9,10,14 XCHG = Exchange: Rogistor/memory with ast 3s 79 rogistor Registor with accumulator 3 3 IN =Input from: Fixed port [1110010w] pon | 5 5 14 Variable port Lit101 10m] 6 8 14 OUT =Output to: Fixed port [itioortw] “pon | 3 3 14 Varlable port [111011 iw] 3 3 4 XLAT= Translate byte to AL 11010111 5 5 ry LEA=Load EA to register [40001101 |modregrim_|] s x LDS sLoad pointer toDS [11000101 modrag rim | (mod « 11) La ar 910,11 LES=Load pointer to ES [11000100] modrog rim | (mod + 11) r at 9,10,11 LAHF= Load AH with flags 2 2 SAHF =Storo AH into flags 2 2 PUSHF = Push flags 3 3 ° POPF =Pop flags [10011104] 5 5 9.18 ‘Shaded areas indicate Instructions not available in iAPX 86, 88 microsystems. See footnotes at end of this document, 1-120 80286.

ADVANCED MICRO DEVICES 26E D m@ 0257525 0034482 2 mm AMD

1 T-49~17-15

80286 INSTRUCTION SET SUMMARY (continued)

Rome wihegeer mother [So0eobaw] matrogam | arlar| 2] o : Immediate toregisterimemory —-[10.00008w| moddorim | data [daaiiswaot] 37] 3,7 | 2 | 9 Immediate to accumulator [oooootow] data | “dataitwat | 3} 8 ADC = Add with carry: . Reg/momory with register to either artanrm] 2] 9 Immodiato to registorinemory —[1000006w| modororim| data [ataitsw=oi] a7} a7] 2] 9 Immediate to accumulator looototow] date | dataitw=t | 3} 3 INC-inerement: : . Registorimamary [rit1ii1w] modoo0 um) arlanr | 2} 9 Register 2} 2 SUB Subtract: Regimemory and register to elther [001010dw] modregrm | arpar} 2] 9 Immediato trom rogister/momory [1 00000sw | modtotnm| daa [dataifswat | 37°} 37 | 2] 9 Immodiato from accumulator [oo01110w| dam ‘| datatwat | 3} 3 Em ‘SBB = Subtract with borrow: Ragimamory and ragisterto either [000110dw| modregrim | ary ar 2 9 Immadiato from registermemory — [1000008w| moddtirim| data [daaitew=oi] a7} 37° | 2] 9 {mmediato from accumulator [oorortow] data] dataitw=7 | s} 3 DEC= Decrement: Registorimemory [rittitiw] modo svi] arlan | 2] 9 Rogistor at 2 CMP = Compare: Rogisterimomory withragistor =» [OO T1101 w] modregrim_| 26] 26) 2] 9 Register with register/memory ar; an] 2] 9 Immediate wit rogister memory —[1000008w]| modttinm{ data [dataitsw-01] 36°] 36° | 2] 9 Immediate with accumulator [oo1titow| data =| _datallwa=t | 3 3 NEG = Change sign [1111011w] modOt trim] 2) mi] 2) 7 . AAA= ASCII adjust for add footrotit| 3 3 DAA Decimal adjust for add 3 3 AAS=ASCIl adjust for subtract §= [001111114 | 3 3 DAS =Decimal adustfor subtract [00101111 | 3] 3 MUL = Multiply (unsigned) [isttoriw] mod 100 xm] Register-Byta 13 13 1 Rogistor-Word ai} at Memory-Byto 16" 16° 2 9 Momory Word w . ee oe oe OO 2 Rogistor-Byte 13 Register-Word at Memory-Byte 16 2 Memory-Word 24" 2 ‘Shaded areas indicate instructions not available In IAPX 66, 68 microsystems. See footnotes at ond of this document. 80286 1-121

ADVANCED MICRO DEVICES 2e6E D MM 0257525 0034483 4 mm AMD T-49-17-15 coe 80286 INSTRUCTION SET SUMMARY (continued) . ARITHMETIC (Continued) a ; le . is mn TOOT pe aT weal es | | oo] a a er ee : oedema: (LTTE Tw] matt] Rogister-Byta "0 4) 14 : . Rogister-Word zal : Memory-Byta wy] i] 26] 69 Momory-Word 2 25] 26] 69 . IDIVsIntoger divi signed) Register-Byto 17] 7 Rogister- Word 25) 25 Momory-Byta 20°} 20° 2 9 Memory-Word 2} 2) 2] 9 AAM = ASCII adjust for multiply 00001010 te} 6 AAD =ASCIl adjust for divide 14] 14 CBW =Convert byte to word a CWO = Convert word to double word a2 Losic ‘ShifvRotate instructions; Rogister/Memary by 1 ary art al 6 Sin] 5én, Rogister’Memary by CL Bin} ain? | 2] 9 pew oa ne oe Seales pS eee Peri (mien es | 9 T1T Instruction

000 ROL

001 ROR

010 RCL

100 ‘SHUSAL 101 ‘SHR Wt SAR AND =And: Regimemory and register to either 27) 27 9 Immediatotoregistormmemary — [1000000w| mod tO0rim| data | daatwet] a7} a7 ® Immediate to accumulator looroo1ow] data | dataitwa1] ay 8 TEST =And function to tlage, no result: Ragistorimemory and registor 26) 26° 9 Immodiato data and registerimomoy [TTT TO1 Tw] moddOOvm| data | daatw=i |] 3,6] 36° 8 Immediato data and accumulator [10101 00w| data | dataltw= 1] y 3 OR=Or: Rogimamory and register to either [ooo010dw 27] 27° Fy Immodiatotorogistarimemory —[1000000w| modoOtrim| daa | daatwet| 37| a7 9 Immediate to acoumulator loooottow] data | dataitwat| “8 XOR= Exclusive or: ‘ Regimemory and register tocither [001100dw ary 27 9 Immediate toregistarimemory —[1000000w] modi 10rm| data | daatw-t| 3,75) a,7° 9 Immediate to accumulator Jootto1ow] data | daaitw= i] y 8 NOT sInvert register/memary [isttottw] modo 1 Orm| 27] 27 9 Shaded areas Indleate Instructions not available In |APX 86, 88 microsystems. Soe footnotes at end of this document, SS 1-122 80286

ADVANCED MICRO DEVICES 26E D M@ 0257525 0034484 & MM AND ees ; T-49-17-15 STRING MANIPULATION: MOVS = Move bytaword 1010010w 5] ° 8 9 CMPS = Compare bytetword [totoor1w] 8 8 ° ISCAS = Scan bytelword [101011 1w| 7 7 9 LODS=Load bytewdto AVAX [10101 10w| 8 5 9 STOS=Stor bytefwd from AVA [10 10101w| 3 3 9 INS Input bytenvd from DX port [0110110 | 5 5 9,14 OUTS x Obit Bytes OX port OT Ot tw) renege g fers gig Fojeiedby cunt WOK eT Lee MOVS = Move string [11110010 | 1010010w 5+4n) S+4n 9 JCMPS.=Comparo sting [ititootz |totootiw| 5¥8n S490 9 SCAS =Scan sting [11ttootz | 1orottiw| 54a S+80 9 LODS =Load sting [tit1o10 | rorottow| Sean 5+4a 8 STOS=Stor0 sting [11110010 | torotoiw] 4+80 4430 9 Fee 8 ee Deck EOC |CALL= Call: Direct within sagment [11101000 | dispiow | asphigh | Tem| Tem} 2 8 Rogistor memory indirect Litiiittt | modo toum | TemAt+m| 7emitem{ 2] 9 ‘within segment Direct intersegment [roortoto [segmontofset | = taem} ase} 2] a.tt.t2 Protected Mode Only (Direct Intersegment): Via call gato to samo privilage lavel 4tem a.t1,12 Via call gate to different privilege level, no parameters 82+m) 18,11,12 Via call gate to different privilege level, x parameters 86+4x+m 8,11,12 Via TSS 177+m 8,11,12 Via task gate 182+m) 8,11,12 Indirect intersegment [isisiiitTmodotinim [imod-t) | 164m) 20em*| 2 fa.gitate Protected Mode Only (Indirect intersegment): Via call gate to same privilege level 444m" 8,9,11,12 Via call gate to diferent privilege level, no parameters 83+m* a.9,11.12 Via call gato to diferent privilege level, x parameters 90+4x+m* 8.9,11,12 Via TSS 180+m* 8.9,11,12 Via task gate 185+m* g.9,11.12 UMP = Unconditional jump ‘Shorviong [tivotott | dapiow | Tom 7+m 8 Direct within segment [iit01001 | dspiow | dephigh | Tem Tem 8 Rogister/mem indirect within segmen( 14111111 | modtoorum | ‘| 7+mt+m*|7+m,tt+m* 2 8,9 Direct ntorsagmont [istorore | sogmentotser } = t14m| 234m aatt2 Protected Mode Only (Indirect Intersegmont): Via call gato to same priviloge level 384m 84112 Via TSS 175+m. 81112 Via task gato 180+m 811.12 Indirect intersegment [istsiitt [mod totum [modstty ] tsem'| 26+me] 2 fao.tt.t2 ‘Shaded areas indicate instructions not available in iAPX 86, 88 microsystems. Soe footnotes at end of this document. SSSSSSSSSSsSsFsFsFFFFFFsSSSSSSSSSSsSS 80286 1-123

ADVANCED MICRO DEVICES 26— D M@ 0257525 0034485 6 ma AMD T-49-17- :

80286 INSTRUCTION SET SUMMARY (continued) 49-17-15

CONTROL TRANSFER (Continued): : Protected Mode Only (Indirect Intersegment) Via call gate to same privilege level Atam* s.9,11,12 : Via TSS. 178sm* le9.t1.12 Via task gato 1834m* e.9.11,12 . RET = Return from CALL: Within segment 11000011 ttem | stam | 2 a9 Within seg addingimmedtoSP [14000010] datalow | datahigh tem | tam | 2 89 Intersagmont 11001011 tem | asm | 2 Jagttae Intersogment adding immediate toSP/11001010] datslow | datahigh | 154m 2 f9,9,11,12 Protected Mode Only (RET): To different privilege level 554m JENZ =Jump an equal zero Tamor3 | 7amor3 8 JUJNGE = Jump on lass not greater or equal Temor3 | 7+mor3 8 JLENG = Jump on lass or equal not greater 7+mor3 | 7+mor3 8 JBMINAE= Jump on below not above or equal Tamor3 | 7+mor3 8 UBEAINAs ump on below or aqual not above [O1t10110] aap] Tamers | 7amor3 8 PISPE = Jump on parityiparity even [01111010] dsp _| Temor3 | 7+mor3 8 JO=Jump on overflow [ottto000| dsp | Temors | 7+mor3 8 JS =Jump on sign Tamor3 | 7+mor3 8 JNEINZ = Jump on not equal not zero Tamor3 | 74mor3 8 JNUJGE= Jump on not less groater or equal T+mor3 | 7+mor3 a JNLENG = Jump on not less or equal grestor Tamor3 | 74mor3 8 JNBNAES Jump on nat below above or equal Tamor3 | 7amor3 8 JNBENAs Jump on not below orequal above [01110111] disp ‘| Tamor3 | 7+mor3 8 ANP/SPO=Jump on not pariparodd [01111011] disp _| Tamor3 | 7+mor3 8 . JNO =Jump on not overfiow [o1110001| disp _| Temors | 7+mor3 8 INS = Jump on not sign [orrttoo1| dep _| Tamors | Zemor3 8 LOOP =Loop CX Times [11io00To] dsp‘ Bemor4 | B+mord 8 LOOPZ/LOOPE = Loop while zero equal 11100001| disp _| Bemor4 | semord 8 LOOPNZLOOPNE= Loop while notzoreeqal [14100000] aap] simora | armors | | eaters J Sao) Sra oo ee isp ee a ce Frr—“—SC—siC oh) Pel ol Shaded areas Indicate instructions not available in iAPX 86, 88 microsystems. See footnotes at end of this document, SS 1-124 80286 : !

7 ™ ADVANCED MICRO DEVICES 28E D mM 0257525 0034484 T mm AND OE ee Oe *

80286 INSTRUCTION SET SUMMARY (continued) T-49-17-15

CONTROL TRANSFER (Continued): INT=Interrupt: . Type specified [11001101] type | 234m 2 Type 3 110014100 . 234m 2 - INTO = Interrupt on overflow [iroo1rto | 24-mor3} 24-ors} $2 (itro)} (Bitno (interrupt) | (interrupt) Protected Mode Only: Via interuptor trap gate to same privilege lovel 4040 811,12 Via interuptor trap gate to ft diferent privilege level 78+n 8,11,12 Via Task Gate 167 +1 811,12; IRET sintorrupt rotum 17+m] 314m) 24] 89,11, 12,18 Protected Mode Only: To different privilege level 55+m 89,11, 12,15 To different task (NT =1) 169+m | 6,9,11,12 4 | 2a a i (EEE SSS ae PROCESSOR CONTROL CLC =Clear cary ooo 2 7 CUC-= Complement cary [iirtoros| 2 2 STC 2Sot cary [ii111004] 2 2 CLD =Clear direction [11111100] 2 7 STD=Sot drection [siitsso1] 2 q CLI =Clear interrupt [ ts111010] 3 ] STlzSot intorrupt 2 | HLTsHat L 11110100] 2 WAIT: Wait | roorro1s| 3 EB LOCK = Bus lock prefix Jit10000 oO O) CTS =Clear task switched flag 00000110 2 3 ESC «Procossor Extension Escapo e-2r] seo] 5 {TTT LL are opcode to processor extension) SEG = Segment override prefix [ooTregT TO) o Ol} Shaded areas indicate instructions not available in iAPX 86, 88 microsystems. ‘See footnotes at end of this document. . SSS 80286 1-125

ADVANCED MICRO DEVICES 28E D M™ 0257525 0034487 1 mm AMD 80286 INSTRUCTION SET SUMMARY (continued) . T-49-17-15 st taney deciver utc woe o0061 111] enon | | ee re at et oy [oooatsia| ae | 3 | feagaa| women 7 [geno L_seseasel selon) | a Lo | stnrmooesmiewes — onenisii sassoesDecsom = | a | ax| as | 0 | Hit ae SS ot ier tree SE i | oe Lalo. Nontytsdaccess asurineny [0005 ti11| aoooee¢] matso0ra a | sie | Vivonetean Teron] aonseoel eric | | se) | a | Shaded areas: indicate Instructions not available in IAPX 86, 88 microsystems. 18 footnotes at end of this document. ee 1-126 80286

ADVANCED MICRO DEVICES 26E D M@@ 0257525 0034488 3 mm AND ~ SSS —+— Footnotes T-49-17-15 The effective Address (EA) of the memory operand is ‘SEGMENT OVERRIDE PREFIX computed according to the mod and r/m fiekis: if mod= 11 then 1/m is treated as a REG fleld REG Is assigned according to the following: = = 0°, : i ‘Segment timed 00 then DISP = 0°, disp-low and disp-high are REG Register if mod=01 then DISP-=disp-low sign-extended to 16 °° ’ B bits, disp-high Is absent 10 ss . lf mod = 10 then DISP = disp-high: disp-low " os . SS if m= 000 then EA = (BX) + (SI) +DISP if #’m=001 then EA (BX) +(Dl) +DISP REG is assigned according to the following table: it/m=010 then EA=(BP) +(SI) +DISP - 16-Bi(w=1) _&-BIt(w=0) if vm =011 then EA =(BP) + (DI) +DISP 000. AX 000 AL if r/m= 100 then EA=(SI) + DISP 001 = Ox 001 CL 010 =DX 0100 «OL if /m= 101 then EA=(DI) + DISP 011 BX 011 BL = 5 100 SP 100 AH tt m= 110 then EA = (BP) + DISP 101 BP 01 CH if ¢m= 111 then EA=(BX) +DISP 110 SI 110 =DH

111 Dt 111 BH

DISP follows 2nd byte of instruction (before data if re- quired) The physical addresses of all operands addressed by “except if mod=00 and r/m=110 then EA=disp-high: the BP register are computed using the SS segment disp-low. register. The physical addresses of the destination op- erands of the string primitive operations (those ad- dressed by the Di register) are computed using the ES segment, which may not be overridden. SSS 80286 1-127