80186

80186 AMD | Alldatasheet

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High Integration 16-Bit Microprocessor iAPX86 Family DISTINCTIVE CHARACTERISTICS a © Integrated feature set © High performance processor ~ Enhanced 10 MHz 8086-1 CPU Two times the performance of the standard 8086 Clock generator 4M byte/sec bus bandwidth interface ‘Two independent, high-speed DMA channels © Direct addressing capability to 1M byte of memory Programmable interrupt controller © Completely abject code compatible with all existing Three programmable 16-bit timers iAPX 86, 88 software Programmable memory and peripheral chip-select ‘Ten new instruction types logic Compatible with 29843/45, 29833/63, 8284, and Programmable wait state generator 8288 bus support components Local bus controller © Optional numeric processor extension @ Available in 10 MHz (80186-10), 8 MHz (80186) © Available in 68-pin Plastic Leaded Chip Carrier (PLCC), Ceramic Leadless Chip Carrier (LCC), and Pin Grid Array (PGA) packages. > GENERAL DESCRIPTION Q “The 80186 is a highly integrated 16-bit microprocessor. It software and adds 10 new instruction types to the existing | ) effectively combines 15-20 of the most common iAPX 86 set. 5 ‘system components onto one. The 80186 provides two times greater throughput than the standard 5 MHz 8086. ‘The 80186 comes in a 68-pin package and requires a single fa) The 80186 is upward compatible with 8086 and 8088 +5 V power supply rs) BLOCK DIAGRAM =z writ =. ‘ranma fa) CAKOUT Vee GNO 14 ners wm OUT 1 TMA OUTS = | }t TR OW Ten IN D | ma | | | wre : ot —W ml ma Hose ee 9 Ea 1 Prccramusnie | masstens SY < || BREE | sa] . be } [mse Q | (sete [coat | 8 | TERA ‘nat aac =] soy —|.| ound onrens ito pus mrenrace ser fee] ete mapa ft REGISTERS PROGRAMMABLE - me [ oie | on |rmanstis Coun LOTT oo | PRESS it | ue atone OOK LJ ADO ANS ic ar nr BC mes Ree ; 180009560 Figure 1. ass D 78 Issue Date: March 1989 :

| Ceramic Leadless Chip Carrier (LCC*) Top Bottom E _. | DW] ee z. *LCC package placed in socket top down. oe Pin Grid Array (PGA) Pins Facing Up Pins Facing Down LOTOTOKOTOTOIOIOLO) (TOIDIOTOIOLOFOIO) @Q©QOCOQOQOOOO® ©OOOOOQQOOO® ®O®OOOOOOO 7 , OOOOOOOO®

CONNECTION DIAGRAMS (Cont'd.) Plastic Leaded Chip Carrier (PLCC) Top Bottom Deez Trivia Delp giz CY Poratetateststeateatetrateslestratealestral Gq fia Eo op a fa Eo op ~ ta fal “Ge oft fe fe} sQGeo ots fc a] sho oH fl fa ‘fo ofl: | a oe of} cl As iffe SB. | » BEBEBHEEBEEREBeee NA Vb ctty Teno a Ta eae PLCC package placed in socket top up. (PLCC pin-out same as LCC.)

ORDERING INFORMATION

_~ Commodity Products AMD commodity products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: a. Temperature Range b. Package Type cc. Device Number d. Speed Option e. Optional Processing \\ a ft _ B L__.. ernons. epocgssia Blank = Standard Processing B= Burn in 4. SPEED OPTION Blank = 8 MHz 0 = 10 MH €. DEVICE NUMBER/DESCRIPTION aoree Highrintegraion 16-84 Microprocessor b. PACKAGE TYPE R= 88-Pin Ceramic Leacless Chip Camer (CAZ068) A= 68-Termnal Pin Grd Array (CGX088) N= 6e.Fin Plaste Leaded Chip Carri (PL 068) _ a. TEMPERATURE RANGE* Blank = Commercial (0 to + 70°C) 1 = Industrial (-40 to + 85°C) Valid Combinations Valid Combinations Valid Combinations list configurations planned to be supported in| volume for this device. Consut the local AMD sales office to confirm availability of specitic valid combinations, to check on newly released aid combinations, and to obtain additonal data on AMD's standard itary grade products. [AR AiR | eors6a |

[Pino | Name [| vo | esription. S| [ss [Woo Voc 1 | Sytem Foor +5 va powor suo [26.60 [ves ves] 1 [swomGrend s7 Reset Output indicates that the 80186 CPU is being reset; and can be used as a system reset. It is oie eh Send ne pena Zo a npr naan oc Sey $e BE sas Crpta Poc, Et d pro bo eciral corso 1 & andorra ans par Taal crystal for the intemal crystat oscillator. X1 can interface to an extemal clock instead of a crystal. The input of oscillator frequency is internally divided by two to generate the clock signal (CLKOUT). ‘CLKOUT Clock Output provides the system with a 50% duty cycle waveform. All device pin timings are specified telative to CLKOUT. CLKOUT has sufficient MOS drive capabilities for a numeric processor extension. ‘System Reset causes the 80186 to immediately terminate its present activity, clear the internal logic, Se ee eee erat a ne Soins bee fetching instructions approximately 7 clock cycles after RES is returned HIGH. RES is required to be LOW for greater than 4 clock cycles and is internally synchronized. For proper initialization, the LOW-to- HIGH transition of RES must occur no sooner than 50 microseconds after power up. This input is provided with a Schmitt-ngger to taciitate power-on IES goneraton via an FIC notwork. Whon FES: ‘occurs, the 80186 will drive the status lines to an inactive level for one clock, and then tri-state them. 47 TEST ‘TEST is examined by the WAIT instruction. if the TEST input is HIGH when "WAIT" execution begins, instruction execution will suspend, TEST will bo resampled until it goss LOW, at which time execution wil resume. If interrupts are enabled while the 80186 is waiting for TEST, interupts will be serviced. This input is synchronized internally. TH o Tria seats or loa SRG] Sea, pwnng wpa Ws FOTN Wom ne TMR INT These inputs are active HIGH (or LOW-to-HIGH transitions are counted) and internally synchronized. THe OUT “Tnor cpa a used ipa agi pulse cr ezine waretrn peeralon reatiag pone Ria ours Ber a Sasa rn ry A na vn FIG by a evil Gn wi aoe ala DAA chard (hal av 8 ao Lag app apg pepe epee apie ‘Non-Maskable Interrupt is an edge-triggered input which causes a type 2 interrupt. NMI is not maskable ra ehh: yo oe eo ord Preteen tod ca oe itachi enone eden pe eo TT {| Wstabe Tasrap Ragunss car be voaoeuisd by seeing one tase ne Wan sonigned as 42 INT2/INTAO vo inputs, these pins are active HIGH. Interrupt Requests are synchronized intemally. INT2 and INT3 may a INTS/INTAT vo be configured via software to provide active-LOW interrupt-acknowledge output signals. All interrupt Fe ee ee oe a et interrupt requests must remain active unti the interrupt is acknowledged. When iRMX mode is selected, the function of these pins changes (see Interrupt Controller section of this data sheet), 65-68 A19/S6, ° Address Bus Outputs (16-19) and Bus Cycie Status (3-6) reflect the four most significant address bits Rares NN Ble epee ap a ae ep oir meres S| samo senate ons wet “ee i a a | [ss] Fresno st pa | ‘$3, S4, and S5 are defined as LOW during T2-T4. AD15-AD0- vo ‘Adaress/Data Bus (0-18) signals constiute ine time multipexed memory oF /O address (T;) and data {T2, Tg, Tw, and T4) bus. The bus is active HIGH. Ag is analogous to! for the lower byte of the data. bus, pins D7 through Dp. It is LOW during T; when a byte is to be transferred onto the lower portion of Se ie eu Oe eon BREST During Tr the Bus High Enable signal should be used to determine if data is to be enabled onto the ‘most significant half of the data bus, pins D15-Dg. BHE is LOW during Ty for read, write, an interrupt acknowledge cycles when a byte is to be transferred on the higher half of the bus. The S7 status information is available during T2, T3, and T.. S7 is logically equivalent to BHE. The signal is active roman wales ari Ta Taare BHE and AO Encodings [CBRE Vatwe [no Vawe [Funes id a A [0] 1 | Byte Transter on upper hall of data bus (01508) [ [ofa Trantor on tower hao data bas 70s) ALE/QSO, ‘Address Latch Enable/Queue Status 0 is provided by the 80186 to latch the address into the 8282/ Cea ae aan See Seen eae, gate a, PE eer eer eer eure ees ee Pope afore cima pinned eny ep ney gi ed edge is generated off the CLKOUT rising edge in T; as in the 8086. Note that ALE is never floated.

PIN DESCRIPTION (Cont.) [rinno. | name | vo _| Description WA/OSt Write Sirobe/Quoue Status 1 indicates that the data on the bus is fo be written into a memory or an 70. See ee ne a ote ng fom cag OLD k Ce eee eee ee Om minced bake mace the ALE/QSO and WA/QS1 pins provide information about processor/instruction queue interaction. [os | ost Queue Operation a ee _ ee ee a ‘RO/OSMD Read Strobe indicates that the 80186 is performing a memory or I/O read cycie. AD is active LOW for floated. RID is active LOW, and floats during "HOLD." RD is driven HIGH for one clock during Reset, and then the output driver is floated. A weak internal pull-up mechanism on the AD line holds it HIGH ee ee ne ere ahaa So od provide ALE, WR, and FID, or if the Queue-Status should be provided. AD should be connected to GND eee ans Sour coe ARDY. ‘Asynchronous Ready informs the 80186 that the addressed memory space or I/O device will complete ae er ee a o aing ee of ROY soe CE ae ae te a at nabick Noesrona ait ppabsbom peermedia er teeny Flay bol gr er preety pee Cee ae SE aera ps SRDY ‘Synchronous Ready must be synchronized externally to the 80186. The use of SRDY provides a Ree ee caer ny ering oars Pere hitpri heen enters tar Shomer te er Seek cre mi 9 eine aaa er a oe ee ee ee Needy FE ee ee ee navatieate imran tinatearasee, Cae a ee as ree oar ma A re Ney COCK ‘TOCK output indicates that_other system bus masters are not to gain control of the system bus while TOGK is active LOW. The COCK signal is requested by the LOCK prefix instruction and is activated at Soe ee en a ene Bek mets romans Peary iter t meer hetero LOCK is asserted. When executing more than one LOCK instruction, always make sure there are six — bytes of code between the end of the first LOCK instruction and the start of the second LOCK instruction. COCK is active LOW, is driven HIGH for one clock during RESET, and then floated. ‘50, 51, 52 Bus cycle status 50-S2 are encoded to provide bus-transaction information:

80186 Bus Cycle Status Information

[est [ st [oes oyete ited a eo Frees vo A a a a Ct [oro Dat worony | a a er AE 52 may be used as a logical M/IO indicator, and 57 as a OT/A indicator. The status lines are dren HIGH for one clock during Reset, and then floated until a bus cycle TD bent OLD hates Fal arto is Wana eaueing the bea ba Te HOLD pl ave AGA fee ee, ERED cain al erties mast gaasiad Sock he Sbiee a pom SADA reins Soa ae er rea eye Sunt tarot ower DX What SOOT EE Ee es eee ten ang Seal be Upper Nomar Gp Soke a aire COW ould whenever 8 ema refroce is made to ho Goze Homer p Soe 8a aa UO ut we Maced sors bee HOLD Ta — address range activating UCS is software programmable. Tes Lower Memory Chip Select is active LOW whenever a memory reference is made to the defined lower Sir ER an “aint Taded dys SA hss re eas 38, 37, 36, MCSO-3 ‘Mid-Range Memory Chip Select signais are active LOW when a memory reference is made to the address ranges activating MCS0-3 are software programmabie. 25 FOSS Peripheral Chip Select signals 0-4 are active LOW when a reference is made to the defined peripheral 27-30 PCST-4 area (65K byte /O space). These lines are not floated dunng bus HOLD. The address ranges activating BESET orcas renee

previously latched value of A1 during a bus HOLD. At is active HIGH. POSEIAZ Peripheral Gp Select 6 o Latched A2 may be programmed fo provide sovenh perghera chip elec. Previously latched value of A2 ducing a bus HOLD. A2 is active HIGH. during each memory and /O access. DEN is HIGH whenever DT/A changes state. 1e existing 7 instruction set specific registers for operand and address calculations.

80186 BASE ARCHITECTU Status and Control Registers

Figure 2. 80186 General Purpose Register Set

Figure 3. Status Word Format Table 2. Status Word Bit Function Instruction Set

• control transfer, high-level instructions, and processor control.

Carry Flag — Set on high-order bit carry These categories are summarized in Figure 4. CF _| or borrow; cleared otherwise. _ cleared otherwise. modes are discussed later in this data sheet. otherwise. linear contiguous sequence of up to 64K (2"®) 6-bit bytes.

Figure 4. 80186 Instruction Set All mnemonics copyright Intel Corp.

Addressing Modes ° aco: ead (unpacked) representation of the decimal The 80186 provides eight categories of addressing modes to gts 0-9. spacity operands. Two addressing modes are provided for © Packed BCD: A byte (packed) representation of two deci- instructions that operate on register or immediate operands: ral ous (0-9). One digit is stored in each nibble (4-bits) of te. © Register Operand Mode: The operand is located in one of ‘ the 8- or 16-bit general registers. . re pane “eecuea sein famed oie are to number © Immediate Operand Mode: The operand is included in the using @ numeric data processor configuration.) instruction. In general, individual data elements must fit within defined Six modes are provided to specify the location of an operand ‘segment limits. Figure 7 graphically represents the data types in a memory segment. A memory operand addrass consists of ‘supported by the 80186. two 16-bit components: a segment base and an offset. The segment base is supplied by a 16-bit segment register either : * implicity chosen by the addressing mode or explicitly chosen moe (TTT by a segment override prefix. The offset, also called the ove effective address, is calculated by summing any combination SON OT A oaTOOE of the following three address elements: ; © the displacement (an 8- or 16-bit immediate value con- ween [TT ] tained in the instruction); 7 ‘© the base (contents of either the BX or BP base registers); ie woe ° a i word © the index (contents of either the SI or DI index registers) ce err Sua Any carry out from the 16-bit addition is ignored. Eight-bit ARTO displacements are sign extended to 16-bit values. semen 1°30? as +t oe contnatong otto tee suse semors dire he sx ane MTTICN PTT memory addressing modes, described below. a © Direct Mode: The operand's offset is contained in the sromen ge"? “Sy * “taal? Fatt & rucon a a 6 TOD depacoment amen =o © Register indirect Mode:The operand’ offset is in one of the ON OS ee ————— registers SI, Di, BX, or BP. 1 ° Pans A © Based Mode: The operand's offset is the sum of an 8- or onmgags [OTT TT 16-bit displacement and the contents of a base register (BX = or BP). wate — © Indexed Mode: The operand's offset is the sum of an 8- or enue Pen? A 1 16-bit displacement and the contents of an index register scm, CTT) baad creer) €6! or Di. (00) gt w par oe © Based Indexed Mode: The operand's offset is the sum of 1 tN 9 1 tt oy 0 4 the contents of a base register and an index register. asca CT) we creer) © Based Indexed Mode with Displacement: The operand's CHEE, counsen, Sikectan offset is the sum of a base register's contents, an index 7 hg 1 th 97 0 register's contents, and an 8- or 16-bit displacement. “oo [TTT] wee Creer) Data Types Feweer ence ‘The 80186 directly supports the following data types: / \\ ° ays ° rT) ors ° © Integer: A signed binary numeric value contained in an 8-bit eee tT) we reper) byte or a 16-bit word. All operations assume a 2's comple- Crews |e NEWOROT GVIEWORDO ment representation. Signed 32 and 64 bit integers are no td 42 gy tt °. ted ric data r. a oat anton trey tame robe roooes Tey © Ordinal: An unsigned binary numeric value contained in an Bit byte or a 16-bit word. \\—saeron —+— ore nit sho? 06 48 se 43 62 ot 0g © Pointer: A 16- or 32-bit quantity, composed of a 16-bit offset FLoxtwe (CILIITIiIiritr) component or a 16-bit segment base component in addition ‘ener > to @ 16-bit offset component. “aeons arse © String: A contiquous sequence of bytes or words. A string DFo02940 may contain from 1K to 64K bytes. NOTE: "SUPPORTED BY 80186 WITH A NUMERIC DATA © ASCII: A byte representation of alphanumeric and control PROCESSOR characters using the ASCII standard of character represen- tation. Figure 7. 80186 Supported Data Types

/O Space Table 4. 80186 Interrupt Vectors ‘Separate instructions address the 1/O space with either an 8- Type Instructions bit port address, specified in the instruction, or a 16-bit port Divide Error 0 | DIV, IDIV address in the DX register, 8-bit port addresses are zero Exception extended such that Ais-Ag are LOW. I/O port addresses —_| Single Step 1 | sae2 | Alt 00F8(H) through OOFF(H) are reserved. Interrupt NMI 2 1 All Breakpoint 3 a INT Interrupts Interrupt —_ INTO Detected 4 "4 INTO An interrupt transfers execution to a new program location. ‘Overflow The old program address (CS:IP} and machine state (Status Exception Word) are saved on the stack to allow resumption of the | array Bounds 5 ++ | BouND interrupted program. interrupts fall into three classes: hard- Exception ware initiated, INT instructions, and instruction exceptions. —_| Unused-Opcode 6 +1 | undefined Hardware initiated interrupts occur in response to an external Exception Opeodes input and are classified as non-maskable or maskable. ESC Opcode 7 | +s | E80 Opcodes Exception Programs may cause an interrupt with an INT instruction. | Timer O Interrupt a | 2areee Instruction exceptions occur when an unusual condition, which Timer 1 Interrupt 18 2B? prevents further instruction processing, is detected while Timer 2 Interrupt a9 | 20% attempting to execute an instruction. If the exception was Reserved 9 3 caused by executing an ESC instruction with the ESC trap bit | DMA 0 Interrupt 10 4 ‘set in the relocation register, the return instruction will point to DMA 1 Interrupt 1 5 the ESC instruction, or to the segment override prefix immedi- INTO Interrupt 12 6 ately preceding the ESC instruction if the prefix was present. INT1 Interrupt 13 7 In all other cases, the return address from an exception will | INT2 Interrupt 14 8 point at the instruction immediately following the instruction INT Interrupt 15 9 causing the exception. A table containing up to 256 pointers defines the proper Notes. interrupt service routine for each interrupt. Interrupts 0-31, ened i ~ some of which are used for instruction exceptions, are 1. These are generated as the result of an instruction reserved. Table 4 shows the 80186 predefined types and +2, ‘The is handled as in the 8086, default priority levels. For each interrupt, an 8-bit vector must assay’ All three one source of f to bbe supplied to the 80186 which identifies the appropriate table "the interrupt controller. The Timer interrupts all have ‘entry. Exceptions supply the interrupt vector internally. in the same detaum prtorty evel wah respect to al other addition, internal peripherals and noncascaded external inter- been Prony ‘hey have @ defined rupts will generate their own vectors through the internal priori a ‘amongst themselves. (Priority 2A is interrupt controller. INT instructions contain or imply the vector higher priority ‘an 2B.) Each Timer int hes a ‘and allow access to all 256 interrupts. Maskable hardware fr vector type ruber torrupt initiated interrupts supply the 8-bit vector to the CPU during an 4. Delault prirtios Ye the Interrupt sources are used interrupt acknowledge bus sequence. Non-maskable hard- only if \\ Briones for ine program each owes into a ware interrupts use a predefined internally supplied vector. tnijue priory tevel. ***5, An escape opcode will cause a trap only if the proper Interrupt Sources bit is set in the peripheral control block relocation register. The 80186 can service interrupts generated by software or hardware. The software interrupts are generated by specific instructions (INT, ESC, unused OP, etc.) or the resus of conditions specified by instructions (array bounds check, INTO, DIV, IDIY, ete.) All interrupt sources are serviced by an SINGLE-STEP INTERRUPT (TYPE 1) indirect call through an element of a vector table. This vector table is indexed by using the interrupt vector type (Table 4), Generated after most instructions if the TF flag is set. multiplied by four. All hardware-generated interrupts are sam- Interrupts will not be generated after prefix instructions (@.9., — pled at the end of each instruction. Thus, the software REP), instructions which modify segment registers (e.9., POP. interrupts will begin service first. Once the service routine is DS), or the WAIT instruction. entered and interupts are enabled, any hardware source of sufficient priority can interupt the service routine in progress. | NON-MASKABLE INTERRUPT-NMI (TYPE 2) The software generated 80186 interrupts are described below. ‘An external interrupt source which cannot be masked. DIVIDE ERROR EXCEPTION (TYPE 0) BREAKPOINT INTERRUPT (TYPE 3) Generated when a DIV oF IDIV instuction quotient cannot be Ayen=inihe vorsion Of tha, INT imwcton It eee te cn expressed in the number of bits in the destination. type 3 interrupt).

INTO DETECTED OVERFLOW EXCEPTION inactive and an internal processing interval elapses, the 80186 (TYPE 4) begins execution with the instruction at physical location Fe some redef Generated during an INTO instruction if the OF bit is set. re. RES also S218 Some registers 10 ined values ARRAY BOUNDS EXCEPTION (TYPE 5) Ri Generated during a BOUND instruction if the array index is Table 5. 80186 Initial Register State after RESET memory at a location indicated by one of the instruction ‘operands. The other operand indicates the value of the index 1 be checked [cove Segment rr _| UMUSED OFCODE EXCEPTION (TYPE 6 ESCAPE OPCODE EXCEPTION (TYPE 7) enon exciton atone ot ESC open (08 DFH). This exception will only be generated if a bit in the relocation register is set. The retum address of this excepton [__UMCS | Frat) | will point to the ESC instruction causing the exception. If a segment override prefix preceded the ESC instruction, the return address will point to the segment override prefix. 80186 CLOCK GENERATOR Hardware-generated interrupts are divided into two groups: The 80186 provides an on-chip clock generator for both maskable interupts and non-maskable interrupts. The 80186 internal and external clock generation. The clock generator provides maskable hardware interrupt request pins INTO- features a crystal oscillator, a divide-by-two counter, synchro- INT3. In addition, maskable interrupts may be generated by nous and asynchronous ready inputs, and reset circuitry. ‘the 80186 integrated DMA controller and the integrated timer unit, The vector types for these interrupts is shown in Table 4. Oscillat Software enables these inputs by setting the interrupt flag bit sciilator (iF) in the Status Word. The interrupt controller is discussed in SR vaipheral seosan of tie dat sees ‘The oscillator circuit of the 80186 is designed to be used with a parallel resonant fundamental mode crystal. This is used as Further maskable interrupts are disabled while servicing an the time base for the 80186. The crystal frequency selected interrupt because the IF bit is reset as part of the response to will be double the CPU clock frequency. Use of an LC or RC an interrupt or exception. The saved Status Word will reflect circuit is not recommended with this oscillator. If an external the enable status of the processor prior to the interrupt. The —_gscialltor is used, it can be connected directly to input pin X1 in interrupt flag will remain zero unless specifically set. The —_tieu of a crystal. The output of the oscillator is not directly interrupt return instruction restores the Status Word, thereby available outside the 80186. The recommended crystal config restoring the original status of IF bit. If the interrupt return re- uration is shown in Figure 8. enables interrupts, and another interrupt is pending, the 80186 will immediately service the highest-priority interrupt pending, » ie., no instructions of the main line program will be executed. Tr PF x + Non-Maskable Interrupt Request (NMI) TX mitz CRYSTAL Anon-maskable interrupt (NMI) is also provided. This interrupt Xe is serviced regardless of the state of the IF bit. A typical use of sor06 NMI would be to activate a power failure routine. The 20 pF activation of this input causes an interrupt with an internally supplied vector value of 2. No external interrupt acknowledge ‘sequence is performed. The IF bit is cleared at the beginning ‘of an NMI interrupt to prevent maskable interrupts from being = serviced. X = 20 for 10 Miz (80186-1) X= 16 for 8 MHz (80186-3) Single-Step Interrupt X = 12 for 6 MHz (80186-6) ‘TC001851 The 80186 has an internal interrupt that allows programs to execute one instruction at a time. It is called the single-step interrupt and is controlled by the single-step flag bit (TF) in the Figure 8. Recommended 80186 Crystal Status Word. Once this bit is set, an intemal single-step Configuration interrupt will occur after the next instruction has been execut- ed. The interrupt clears the TF bit and uses an internally lock ‘supplied vector of 1. The IRET instruction is used to set the TF a Generator bit and transfer control to the next instruction to be single- The 80186 clock generator provides the 50% duty cycle stepped. processor clock for the 80186. It does this by dividing the oscillator output by 2 forming the symmetrical clock. If an Initialization and Processor Reset external oscillator is used, the state of the clock generator will Processor initialization or startup is accomplished by driving change on the falling edge of the oscillator signal. The the FES input pin LOW. RES forces the 80186 to terminate all CLKOUT pin provides the processor clock signal for use ‘execution and local bus activity. No instruction or bus activity outside the 80186. This may be used to drive other system will occur as long as RES is active. After RES becomes components, All timings are referenced to the output clock.

READY Synchronization generated to control the flow of data through the transceivers. The operation of these signals is shown in Table 6. The 80186 provides both synchronous and asynchronous ready inputs. Asynchronous ready synchronization is accom- Table 6, Transceiver Control Signals Description plished by circuitry which samples ARDY in the middle of Tz, Taurean ne mae leu wun anOvesemied © “pwane [__nsion HIGH. One-half CLKOUT cycle of resolution time is used. Full ‘synchronization is performed only on the rising edge of ARDY, DEN (Data Enable) Enables the output drivers of the ie., the falling edge of ARDY must be synchronized to the transceivers. It is active LOW CLKOUT signal if it will occur during Tz or Tw. HIGH-to-LOW during memory, I/O, or INTA transitions of ARDY must be performed synchronously to the cycles. CPU clock. DT/A (Data Transmit/ Determines the direction of trav- _ - - Receive) el through the transceivers, A ‘A second ready input (SRDY) is provided to interface with HIGH level directs data away externally synchronized ready signals. This input is sampled at from the processor during write the end of Tz and again at the end of each Tw unti it is operations, while a LOW level sampled HIGH. By using this input rather than the asynchro- ivects data toward the proces- nous ready input, the half-clock cycle resolution time penalty is sor during a read operation. eliminated. This input must satisfy set-up and hold times to guarantee proper operation of the circuit. Local Bus Arbitration lit i The 80186 uses a HOLD/HLDA system of local bus ex- in atin, he S016, a pao he tga stinseact_ TT ens an anyones bv range mech and peripheral blocks. This is discussed in the Chip Selact/ "iS. This means multiple masters utilizing the same bus can Ready Logic description. operate at separate clock frequencies. The 80186 provides a single HOLD/HLDA pari through which all other bus masters. RESET Logic may gain cotnrol of the local bus. This requires external circuitry to arbitrate whcih external device will gain control of ‘The 80186 provides both a RES input pin and a synchronized —_the bus from the 80186 when there is more than one alternate RESET pin for use with other system components. The RES local bus master. When the 80186 relinquishes control of the input pin on the 80186 is provided with hysteresis in order to local bus, it floats DEN, RD, WR, S0-S2, LOCK, ADO-AD15, facilitate power-on Reset generation via an RC network. A16-A19, BHE, and DT/R to allow another master to drive RESET is guaranteed to remain active for at least five clocks these lines directly. given a RES input of at least six clocks. RESET may be delayed up to two and one-half clocks behind FES. ‘The 80186 HOLD latency time, ie., the time between HOLD - request and HOLD acknowledge, is a function of the activity —_ Multiple 80186 processors may be synchronized through the occurring in the processor when the HOLD request is re- RES input pin, since this input resets both the processor and ceived. A HOLD request is the highest-priority activity request divide-by-two internal counter in the clock generator. In order which the processor may receive: higher than instruction to insure that the divide-by-two counters all begin counting at fetching or internal DMA cycles. However, if a DMA cycle is in the same time, the active going edge of HES must satistya25 progress, the 80186 will complete the transfer before reiin- ns setup time before the falling edge of the 80186 clock input. quishing the bus. This implies that if a HOLD request is In addition, in order to insure that all CPUs bagin executing in received just as a DMA transfer begins, the HOLD latency time the same clock cycle, the reset must satisfy a 25ns setup time —_—_ can be as great as 4 bus cycles. This will occur if a DMA word before the rising edge of the CLKOUT signal of all the transfer operation is taking place from an odd address to an Processors. odd address. This is a total of 16 clocks or more, if WAIT states are required. In addition, if locked transfers are per- LOCAL BUS CONTROLLER formad, the HOLD latency time will be increased by the length ‘The 80186 provides a local bus controller to generate the local of the locked transfer. bus control signals. In addition, it employs a HOLD/HLDA protocol for relinquishing the local bus to other bus masters. it_ | Local Bus Controller and Reset also provides contro! lines that can be used to enable external pon receipt of a RESET pulse from the FES input, the local buffers and to direct the flow of data on and off the local bus. bus controller will perform the following actions: Memory/Peripheral Control . Drive DEN, RD, and WR HIGH for one clock cycle, then The 80186 provides ALE, RD, and WR bus control signals. co The RD and WA signals are used to strobe data from memory NOTE: FE is also provided with an intemal pultup de- to the 80186 or to strobe data from the 80186 to memory. The vice to prevent the processor from inadvertently enter- ALE line provides a strobe to address latches for the mult- ing Queue Status mode during reset. ~ plexed address/data bus, The 80186 local bus controller does © Drive SO-S2 to the passive state (all HIGH) and then float. not provide a memory/| ‘signal. If this is required, the user will have to use the S2 signal (which wil require external © "66 LOCK HIGH and then float. latching), make the memory and I/O spaces nonoverlapping, © Tristate ADO-15, A16-19, BHE, DT/A. OF use only the integrated chip-select circuitry. © Drive ALE LOW (ALE Is never floated). Transceiver Control © Drive HLDA LOW. The 80186 generates two control signals to be connected to The 20186 generates two contol signals to be connected ‘0 INTERNAL PERIPHERAL INTERFACE sxotion of wanscaivers for era buflering without adding Al the 60168 integrated peinherals re conbotod via 16-t external logic. These control lines, DT/R and DEN, are registers contained within an internal 256-byte control block.

zeros). All of the defined registers within this control block may _ peripheral blocks has not substantially changed. address range corresponding to a chip-select range is not bY the CPU or by the integrated DMA unit. (erates in 1/0 space. If the contol 1 rodistor proc is mapped memory, while four are provided for midrange memory. into ‘space, the upper 4 bits e base address must .

3 The range for each chip select is user-programmable and can

relocation register is set to 20FFH. This causes the control _are in bytes, whereas 80186 memory is arranged in words. byte control register block is shown in Figure 10. used, the memory block size will be 128K, not 64K. Figure 9. Relocation Register

Relocation Register FEH chip-select register, as explained below. DMA Descriptors Channel 1 DoH The 80186 provides a chip select for low memory called LCS. starting at location OOOOOH. the upper limit, the size of the memory block is also defined.

7 ABH Table 8 shows the relationship between the upper address

Chip-Select Control Registers OH selected and the size of the memory block obtained. Figure 10. Internal Register Map 4 FFFFH 128K 1FFBH defined. Table 7 shows the relationship between the base become active until the LMCS register is accessed. address selected and the size of the memory block obtained. Address | Memory | UMCS Value this chip-select register. Fe000 32K Fe3BH address and size of this memory block are programmable. Table 7. Any combination of bits 6-13 not shown in Table 7 will fange biock. ‘Thus, if the total block size is 23K, each chip larger upper memory area is desired ‘the first range and MCS3 being active for the last range. are greater than or equal to UMCS (with bits 0-5 0") will desoribed in a later section.

Treated as 16-bit registers located on even boundaries in I/O _ble Base Address (PBA) of the peripheral chip-select block. this register correspond to bits 19-10 of the 20-bit Programma- register. Figure 15. PACS Register specify READY mode for PCS0-PCS3. bits is shown in Table 12. Table 10. PCS Address Ranges Table 12. READY Bits Programming Pcso PBA —PBA+ 127 0 | 0] 0 | 0 wait states, external RDY also used. 1] 0 | 0 | 0 wait states, external RDY ignored. by the MPCS register (which is also used to set the size of the ignored. register is located at offset A8H in the internal control block. nored. 6 is used to select whether the peripheral chip selects are nored. the MPCS and the PACS registers are undefined, however READY, not in series if the external READY is used (R2 = 0). Table 11. MS, EX Programming Values wait states, not six. This is because the two wait states 0 = Peripherals mapped into I/O space. cycles accessing internal peripherals. MPCS bits 0-2 are used to specify READY mode for PCS4- ‘of MPCS set the PCS4-6 READY mode. READY with the integrated ready generator. Ready consideration (ie. UMCS resets to FFFBH).

9 Pee Ine] 1 vee ne on] om | || oe ae]

Figure 18. DMA Control Register ° gardless of the state of the bit. @ the mode of synchronization; 01 Source synchronization. ‘© whether bytes or words will be transferred; 10 Destination synchronization. ‘© whether interrupts will be generated after the last transfer; 11 Unused. number of DMA cycles; transfer. . 2 (B/W) after each transfer. ‘The DMA channel control registers may be changed while the transfer. operation will affect the current DMA transfer. channel. DMA Control Word Bit Descriptions 1 high priority. Bw: Byte/Word (0/1) Transfers. Set at same priority level. CHG/NOCHG: Change/Do not change (1/0) ST/ 1: Enable DMA requests from timer 2. STOP biti this bit sat when wring Bit 3 Bit 3 is not used. to the control word, the ST/STOP bit 'S not used.

‘dresses, since this will allow data to be accessed in a single when destination synchronization is performed, however. Data memory access. will not be fetched from the source address until the destina- tion device signatis that it is ready to receive it. When DMA Transfer Count Register destination synchronized transfers are requested, the DMA DMA e-bit ; controller will relinquish control of the bus after every transfer. co This regeter is ane antod ate every DMA tren tf no other bus activity is initiated, another DMA cycle will regardless of the state of the TC bit in the DMA Control Bein alter two processor clocks. This js dane to. allow the Register. If the TC bit in the DMA control word is set, however, tination device time to remove its request if another DMA ccivaty wil terminate wher the Wanster count register wans(er 18 not desired. Since the DMA controller will relinguish reaches zero. ‘the bus, the CPU can initiate a bus cycle, As a result, a . complete bus cycle will often be insarted between destination synchronized transfers. These lead to the maximum DMA DMA Requests transfer rates shown in Table 14. Data transfers may be either source or destination synchro- nized, that is either the source of the data or the destination of Rates the data may request the data transfer. In addition, DMA Table 14. Maximum DMA Transfer transfers may be unsynchronized; that is, the transfer will take Type of place continually until the correct number of transfers has Synchronization ‘occurred. When source or unsynchronized transfers are per- ‘Selected formed, the DMA channel may begin another transfer immedi- : ately after the end of a previous DMA transfer. This allows Uneynchronized 2MBytes/o0e | MBytes/s0° complete transfer to take place every 2 bus cycles or eight Seawater eymch | iaMoywersec | 1 Muvocreoc clock cycles (assuming no wait states). No prefetching occurs lafion MBytes! bs HIGHER REGISTER | XxX XXX ‘ADDRESS LOWER REGISTER| A1S-A12 | At1-A6 | A7-A4 ‘ADDRESS 15 oO XXX = DON'T CARE Figure 18a. DMA Memory Pointer Register Format DMA Acknowledge on pra have been Generated, Therotre, tne ‘source ‘and destination transfer pointers, transfer count register No explicit DMA acknowledge pulse is provided. Since both ff be this bit la 2et. source and destination pointers are maintained, a ead from a" “20d? Must be Programmed Before this bit is requesting source, or a write to a requesting destination, | Each DMA register may be modified while the channel is should be used as the DMA acknowledge signal. Since the operating. If the CHG/NOCHG bit is cleared when the control chip-select lines can be programmed to be active for a given register is written, the ST/STOP bit of the contro! register will block of memory or 1/0 space, and the DMA pointers can be _not be modified by the write. if multiple channel registers are programmed to point to the same given block, a chip-select __moxified, itis recommended that a LOCKED string transfer be line could be used to indicate a OMA acknowledge. used to prevent a DMA transfer from occurring between DMA updates to the channel registers. The DMA channels may be programmed such that one DMA Channels and Reset channel is always given priority over the other, or they may be DMA fil perform the followi programmed such as to alternate cycles when both have DMA. asin ESET, the channels wi "9 requests pending. OMA cycles always have priority over internal CPU cycles except between locked memory accesses © ‘The Start/Stop bit for each channel will be rest to STOP. or word accesses the odd memory locations; however, an ‘extemal bus hold takes priority over an internal DMA cycle. © Any transfer in progress is aborted. Because an interrupt request cannot suspend a DMA opera: tion and the CPU cannot access memory during a DMA cycle, IMERS ous DMA cyces, An NMI request Sowever wil cause al (ee Figure To) two at imtomnal gl giniens ond ave . p (s00 Figure 19). Two are are internal DMA activity to halt. This alows the CPU to quickly connected to four extemal pins (2 per timer). They can be respond to the NMI request. used to count external events, time external events, generate nonrepetitive waveforms, etc. The third timer is not connected DMA Programming to any extemal pins, and is useful for real-time coding and time DMA cycles will occur whenever the ST/STOP bit of the Control delay applications. in addition, this third timer can be used as a Register is set. If synchronized transfers are programmed, a prescaler to the other two, or as a DMA request source.

ALT: INH: ‘The ALT bit determines which of two MAX COUNT registers is The inhibit bit allows for selective updating of the enable (EN) used for count comparison. If ALT = 0, register A for that timer _bit. If INH is a one during the write to the mode/control word, is always used, while if ALT = 1, the comparison will alternate _then the state of the EN bit will be modified by the write. If INH between register A and register B when each maximum count _is a zero during the write, the EN bit will be unatfected by the is reached. This alternation allows the user to change one —_operation. This bit is not stored: it wil always be a 0 on a read. MAX COUNT register while the other is being used, and thus . provides a method of generating nonrepetitive wavetorms, INT: Square waves and pulse outputs of any duty cycle are a When set, the INT bit enables interrupts from the timer, which subset of available signals obtained by not changing the final will be generated on every terminal count. If the timer is count registers. The ALT bit also determines the function of configured in dual MAX COUNT register mode, an interrupt will the timer output pin. If ALT is zero, the output pin will go LOW be generated each time the value in MAX COUNT register A is for one clock, the clock after the maximum countis reached, If reached, and each time the value in MAX COUNT register B is ALT is one, the output pin will reflect the current MAX COUNT —_ reached. If this enable bit is cleared after the interrupt request register being used (0/1 for B/A). has been generated, but before a pending interrupt is ser- CONT: viced, the interrupt request will still be in force. (The request is latched in the Interrupt Controller.) Setting the CONT bit causes the associated timer to run continuously, while resetting it causes the timer to halt upon = MC: maximum count. If CONT = 0 and ALT = 1, the timer will count The Maximum Count bit is set whenever the timer reaches its to the MAX COUNT register A value, reset, count to the final maximum count value. If the timer is configured in dual register B value, reset, and halt. MAX COUNT register mode, this bit will be set each time the EXT: value in MAX COUNT register A is reached, and each time the value in MAX COUNT register B is reached. This bit is set ‘The external bit selects between intemal and external clocking _regardless of the timer’s interrupt-enable bit. The MC bit gives for the timer. The external signal may be asynchronous with the user the ability to monitor timer status through software respect to the 80186 clock. If this bit is set, the timer will count instead of through interrupts. LOW-to-HIGH transitions on the input pin. If cleared, it will count an internal clock while using the input pin for control. In RIU: this mode, the function of the external pin is defined by the The Register In Use bit indicates which MAX COUNT registor ATG bit The maximum input to output transition latency time jx euveeay ‘being used tor comparison to the timer count may be as much as six clocks. However, clock inputs may be value, A zero value indicates register A. The RIU bit cannot be pipelined as closely together as every four clocks without written, ie., its value is not affected when the control register losing clock pulses. is written, It is always cleared when the ALT bit is zero. PB Not all mode bits are provided for timer 2. Certain bits ‘The prescaler bit is ignored unless internal clocking has been are hardwired as indicated below: selected (EXT = 0}. Ifthe P bit is a zero, the timer will count at ‘one-fourth the internal CPU clock rate. If the P bit is a one, the ALT =0, EXT =0, P=0, RTG=0, RIU=0 output of timer 2 will be used as a clock for the timer. Note that the user must initialize and start timer 2 to obtain the prescaled Count Registers clock. Each of the three timers has a 16-bit count register. The RTG: current contents of this register may be read or written by the . processor at any time. If the register is written into while the Retrigger bit is only active for internal clocking (EXT = 0). In timer is counting, the new value will take effect in the current this case it determines the control function provided by the count cycle. input pin.

1 ATG =, the input level gates the internal clock on and oft, Max Count Registers

If the input pin is HIGH, the timer will count; if the input pin is Timers 0 and 1 have two MAX COUNT registers, while timer 2 LOW, the timer will hold its value. As indicated previously, the has a single MAX COUNT register. These contain the number input signal may be asynchronous with respect to the 80186 ~—of events the timer will count. In timers 0 and 1, the MAX cock. COUNT register used can alternate between the two max When ATG = 1, the input pin detects LOW-to-HIGH transi. count values whenever the current maximum count is tions. The first such transition starts the timer running, clearing ‘reached. The condition which causes a timer to reset is the timer value to zero on the first clock, and then increment- ‘equivalent between the current count value and the max count ing thereafter. Further transitions on the input pin will again being used. This means that if the count is changed to be reset the timer to zero, from which it will start counting up above the max count value, or if the max count value is again. If CONT = 0, when the timer has reached maximum changed to be below the current value, the timer will not reset ‘count, the EN bit will be cleared, inhibiting further timer activity. to zero, but rather will count to its maximum value, “wrap EN: around" to zero, then count until the max count is reached. The enable bit provides programmer control over the timer’s Timers and Reset FUN/HALT statu, when ot the timer is gratia to incre, Upon RESET, the Timers wil perform the following ations: ‘ment subject to the input pin constraints in the int 1 i rode {discussed previously), When cleared, the timer willbe ® Al! EN (Enable) bits are reset proverting timer counting inhibited from counting. All input pin transitions during the time All SEL. (Select) bits are reset to zero. This selects MAX EN is zero will be ignored. If CONT is zero, the EN bit is COUNT register A, resulting in the Timer Out pins going automatically cleared upon maximum count. HIGH upon RESET.

INTERRUPT CONTROLLER four external interrupt pins. The interrupt controller is set into ‘one of these three modes by programming the correct bits in The 80186 can receive interrupts from a number of sources, the INTO and INT1 contro! registers. The modes of interrupt both internal and external. The internal interrupt controller controller operation are as follows: serves to merge these requests on a priority basis, for individual service by the CPU. Internal interrupt sources Fully Nested Mode (Timers and DMA channels) can be disabled by their own control registers or by mask bits within the interrupt controller. When in the fully nested mode four pins are used as direct The 80186 interrupt controller has its own control registers __iNterrupt requests. The vectors for these four inputs are that sot the mode of operation for the controller. generated internally. An in-service bit is provided for every interrupt source. If a lower-priority device requests an interrupt The interrupt controller will resolve priority among requests while the in-service bit (IS) is set, no interrupt will be generated ~ that are pending simultaneously. Nesting is provided so by the interrupt controller. In addition, if another interrupt interrupt service routines for lower priority interrupts may request occurs from the same interrupt source while the themselves be interrupted by higher priority interrupts. A block inservice bit is set, no interrupt will be generated by the diagram of the interrupt controller is shown in Figure 21. interrupt controller. This allows interrupt service routines to The interrupt controller has a special iRMX 86 compatibil operate with interrupts enabled without being themselves mode that allows the use of ne 80186 within the AMX S interrupted by lower-priority interrupts. Since interrupts are operating system interrupt structure. The controller is sot in enabled, higher-priority interrupts will be serviced this mode by setting bit 14 in the peripheral control block When a service routine is completed, the proper |S bit must be relocation register (see iRMX 86 Compatibility Mode section). reset by writing the proper pattern to the EO! register. This is In this mode, the internal 80186 interrupt controller functions required to allow subsequent interrupts from this interrupt as a “slave” controller to an external ‘master’ controller. source and to allow servicing of lower-priority interrupts. An ‘Special initialization software must be included to properly set EO! command is issued at the end of the service routine just up the 80186 interrupt controller in RMX 86 mode. before the issuance of the retum trom interrupt instruction. f the fully nested structure has been upheld, the next highest- MASTER (NON-IRMX) MODE OPERATION priority source with its IS bit set is then serviced. Interrupt Controller External Interface Cascade Mode For external interrupt sources, five dedicated pins are provid- ‘The 80186 has four interrupt pins and two of them have dual ed. One of these pins is dedicated to NMI, non-maskable functions. In the fully nested mode the four pins are used as interrupt. This is typically used for power-fail interrupts, etc. direct interrupt inputs and the corresponding vectors are The other four pins may function either as four interrupt input generated internally. In the cascade mode, the four pins are lines with internally generated interrupt vectors, as an interrupt configured into interrupt input-dedicated acknowledge signal line and an interrupt acknowledge line (called the “cascade pairs. The interconnection is shown in Figure 22. INTO is an _ mode'’) along with two other input lines with internally generat- interrupt input interfaced to an 8259A, while INT2/INTAO ed interrupt vectors, or as two interrupt input lines and two serves as the dedicated interrupt acknowledge signal to that dedicated interrupt acknowledge ouput lines. When the inter- peripheral. The same is true for INT1 and INTS/INTAT. Each Tupt lines are configured in cascade mode, the 80186 interrupt —_pair can selectively be placed in the cascade or non-cascade controller will not generate internal interrupt vectors. mode by programming the proper value into INTO and INT1 External sources in the cascade mode use externally generat- control registers. The use of the dedicated acknowledge ed interrupt vectors. When an interrupt is acknowledged, two. signals eliminates the need for the use of external logic to INTA cycles are initiated and the vector is read into the 80186 generate INTA and device select signals. ‘on the second cycle. The capability to interface to external The cascade mode allows the. lity to serve up to 82598 programmable interupt controlar is thus provided pq Mummers aanwen caueue thea the too ef external when the Inputs are configured In cascade mode, master and slave 8259As. Three levels of priority are created, requiting priority resolution in the 80186 interrupt controller, Interrupt Controller Modes of Operation the master 8259As, and the slave 8259As. If an external The basic modes of operation of the interrupt controller in non- interrupt is serviced, one IS bit is set at each of these levels. iRMX mode are similar to the 8259A, The interrupt controller When the interrupt service routine is completed, up to three responds identically to internal interrupts in all three modes: _end-of-interrupt commands must be issued by the program- the difference is only in the interpretation of function of the mer.

Figure 21. Interrupt Controller Block Diagram rupt source will not be recognized unless the in-service bit for adjacent me locat in the rogister file. est pin. As a result, if external interrupt controller . extemal master’s IS register is required to determine if there is _t allows other requests to be serviced. active and the next interrupt service routine is entered. set the indicated in-service bit. The 80186 provides a Poll Progress.

inputs are active HIGH. In the edge sense mode or the level- interrupt acknowledge or by reading the poll register. The IS. In the edge-sense mode, i the level remains high after the Crm™merrupt command issued by the CPU. Interrupt Controller Registers register will be HIGH only after an inactive-to-active transition. contains 15 registers. All registers can both be read or written edges the requests. CPU when it receives interrupt requests from devices with a registers, and vice versa. Figure 22. Cascade Mode Interrupt Connection

so all interrupts are unmasked.

3 Te raga onins gorrl wor conto se nr

allow prompt service of all non-maskable interrupts. Figure 23. Interrupt Controller Registers Figure 24. In-Service, Interrupt Request, and Mask Register Formats Figure 25. Priority Mask Register Format Figure 26. Interrupt Status Register Format

no longer accept external inputs. There are however, enough mods of operation. the initialization software must program the proper priority PIC-inputs. Figure 30. EO! Register Format Figure 31. Poll Register Format

20108 SLAVE INTERRUPT OUTPUT

Figure 32. IRMX 86 Interrupt Controller Interconnection

Correct master-slave interface requires decoding of the slave ‘Figure 35. The interrupt request bits are set when a request addresses (CASO-2). Slave 8259As do this internally. Be- arrives from an internal source, and are rest when the cause of pin limitations, the 80186 salve address will have to processor acknowledges the request. be decoded externally. INTT is used as a slave-select input. Note that the slave vector address is transferred internally, but Mask Register the READY input must be supplied externally This register contains a mask bit for each interrupt source. The INT2 is used as an acknowledge output, suitable to drive the format for this register is shown in Figure 35. If the bit in this INTA input of an 6259A. register corresponding to a particular interrupt source is set, any interrupts from that source will be masked. These mask Interrupt Nesting bits are exactly the same bits which are used in the individual ~ JRMX 86 mode operation allows nesting of interrupt requests. control registers, i.e., changing the state of a mask bit in this When an interrupt is acknowledged, the priority logic masks off -‘“ogister will also change the state of the mask it in the all priority levels except those with equal or higher priority. __iNdividual interrupt control register corresponding to the bit. Vector Generation in the IRMX 86 MODE Control Registers Vector generation in iRMX mode is exactly like that of an These registers are the control words for all the internal 8259A slave. The interrupt controller generates an 8-bit vector interrupt sources. The format of these registers is shown in which the CPU multiplies by four and uses as an address into a Figure 36. Each of the timers and both of the DMA channels vector table. The significant five bits of the vector are user- have their own Control Register. programmable while the lower three bits are generated by the . Prony logic. These bits represent the encoding of the proriy TRE bits of the Control Registers are encoded as follows: level requesting service. The significant five bits of the vector pr, a.bit encoded field indicating a priority level for the ‘are programmed by writing to the Interrupt Vector register at ' courcer note that each source must be programmed offset 20H. at specified levels. Specific End-of-Interrupt msk: mask bit for the priority level indicated by pr, bits. In IRMX mode the specific EO! command operates to reset an in-service bit of a specific priority. The user supplies a 3-bit priority-level value that points to an in-service bit to be reset. ‘The command is executed by writing the correct value in the OFFSET Specific EO! register at offset 22H. LEVEL 5 CONTROL REGISTER (TIMER 2) SAH Interrupt Controller Registers in the iIRMX LEVEL 4 CONTROL REGISTER ~~ 86 Mode (TIMER 1) 38H All control and command registers are located inside the internal peripheral control block. Figure 33 shows the offsets LEE OTT OSTER | a6 of these registers. LEVEL 2 CONTROL REGISTER | 344 End-of-Interrupt Register (OMA 0) The end-of-interrupt register is a command register which can LEVEL 0 CONTROL REGISTER | go, only be written. The format of this register is shown in Figure (TIMER 0) 34. It initiates an EO! command when written by the 80186 CPU INTERRUPT-REQUEST REGISTER | 2EH The bits in the EOI register are encoded as follows: on INSERVICE REGISTER 2CH Le Encoded value indicating the priority of the IS bit to be reset. ‘eset PRIORITY-LEVEL MASK REGISTER | 2AH In-Service Register This register can be read from or written into. It contains the in- [ _wask ncaisren | 28H service bit for each of the internal sources. The format for this register is shown in Figure 35. Bit positions 2 and 3 corre- IF I TI spond to the DMA channels; positions 0, 4, and 5 correspond SPECIFIC EO! REGISTER 22H to the integral timers. The source's IS bit is set when the processor acknowledges its interrupt request. INTERRUPT VECTOR REGISTER | 20H Interrupt Request Register This register indicates which internal peripherals have interrupt Figure 33. Interrupt Controller Registers requests pending. The format of this register is shown in (IRMX86 Mode) 29 .

Figure 39. Typical 80186 Computer

Ce) 7 CONTROLLER | > COMMANDS. Figure 40. Typical 80186 Multi-Master Bus interface

ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Voltage on Any Pin with Temperature (Ta) .--soreeeesessessisseeeseeeeO 10 +70°C Respect to Ground... 1.0 V tO +7 V (To) sessesceecseesteesstesneseesseeO tO +110°C Stresses above those listed under ABSOLUTE MAXIMUM ta eure Cred -40 to 485°C PATINGS may cause 1 dev Functionaliy Tomporaure Tne 4D @ 250 Meier ose nuke ts not device falure, Fim ha escesseseseneeneeeseceesseeese ‘maximum ratings for extended periods may affect device Operating ranges define those limits between which the _ reliability. functionality of the device is guaranteed. DC CHARACTERISTICS [Parameters | ___ Description Test Conditions [win [wax [unite | [w+ meutow vonage TCT vos Input High Voltage + [ow ER Tae | cvs [vm | [wir] trot High Votage FEST CT 8 Moots | vos in = 2.5mA tor S052 [va [ev venoe RTS Sate owe [| oe |_| [Vou | Owipot High Vonage | loam 40a a [Vos [taser oor ‘ec Power Supply Current [tare stom 7 co i [reat Coakage Curent [Ven eVoo Pet [io | Outpt Leakage Curent | OMBV<Vour<Voo | To [Vero | Glock Output Low | a soma To volts | [Weo | Glock Output High [tons 200A vote | [Vou | Goce input Low votage [Vos [Vou | Gock inpat in vote Toca 10 | Vote a [Gio | 0 Capactanes Tr SWITCHING CHARACTERISTICS PIN TIMING 80186 Timing Requirements All Timings Measured At 1.5 Volts Unless Otherwise Noted 20186-10 (tommtz)| #0186 (eM) | [Parameters | Description [Test Gonaltions | win [Max [win [wax | Units | [__Tover [Baan | CT Ts [tax [Basins wT Ts TARYHOH ‘Asynchronous Ready . |? | [= | {AREADY) Active Setup Time’ [__TaRvict [AREADY inactive Soup Time [| | eT a Ts | [tonanyx[AREADY Hog Time TT ns [TaRvont[AREADY Inactive Hod Time] TT os Lm [aware | f=. t=t [| (READY) Transition Setup Timo [worsay | SREADY Transiton How Time | | Ps [river from sew TC ts [vos [NTR NM, TEST TIMERIN, Sows” [Tes Tas ns [wor Tora, paar. Setup” ase **For Industrial Grade Parts only 0 .

SWITCHING CHARACTERISTICS (Cont'd.)

80186 Master Interface Timing Responses

| soree-rocomin | soveeremricy | Description Test Conditions [win [| mex | min | max _| a a [yeux | ao | Tera | 5 | a a Pet tt {after float) [reetse | | renee | a oe [rent [ALE isco Doay___ | ee a [rence | [rena [ro] a a a a [eteuse [| retcwao [ro] a a A [_Teverx | Gontor nace Doey | a a ere tt (Non-Write Cycle) a a [0 [aes a a [feictae | retonas [r] Pos ~~ - s [| o [ | [trun [RD win [eae [Preece] rs] [_—rwewe WR wie [arouse | [ererctao| rs] [rotors | [rotcnras | [ra] a a a A CO [-—Teio [Reset aay a a A [-“Tonosy | Guewe Si Oey | a a [—Teox [Sans Ho Time | a a a [as as a Se [rexcsy | Crpsat have Dewy PC Chip-Select Hold from a a | “Towosx | Gne-sotesnaetve Doy Pe fs fe

SWITCHING CHARACTERISTICS (Cont'd.)

80186 CLKIN Requirements

sovee-r0crowra) | eores cents) | Test conations | win | wax | min | wax | A a [eh Tex Rae tine te a vot [ree [CUR tow Tere vei a

80186 CLKOUT Timing (200 pF load)

[Parameters | Description | Test Conditions | _ min | Max [Min | Max | Unite | [Teco [oumecnoursew tC] dT TT | a RO [Yooh | GcKOUT tow tine | as vats arenes] rarotcurs [Pe | [roar 6cKOUT igh Tine | 15 wots erouctso] | Yaroucurs | [re | [Tarnow —[Ginour ase tine | iowsswe [| @ | [| [—recao11 | CiKOUT Fat Te] 35 wtvors J re fs SWITCHING TEST INPUT/OUTPUT WAVEFORM a _ ons caroorero AC testing inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0." The clock is driven at 4.3V and 0.25V. Timing measurements are made at 1.5V for both a logic "1" and "0."

anita, cc. a | = “ee a ast Pe TON ea o| = wares? re [TX Jere] XD ommort TF met 4 Lf ee ce a Coe am. me _| i ry a GT

SWITCHING WAVEFORMS (Cont'd.) MAJOR CYCLE TIMING (Cont'd.) Vow ‘TOMICH? “ef Ate 4 Sot sel _ * seet at Eee wes ramet nontects [| Xmen KP [we tT) ~ FS Te TCHLH: Tous — ct TCLAZ -TOVCL- a ac (onl mw perso eee ey * = SI renerv — oA “ [wen Fret FY | = TCHCSX ow a rece rosea Y= 'WF006223 Notes: 1. Following a Write cycle, the Local Bus is floated by the 80186 only when the 80186 enters a "Hold Acknowledge” state. 2. INTA occurs one clock later in RMX-mode. 3. Status inactive just prior to Ts.

SWITCHING WAVEFORMS (Cont'd.) 14 +> ‘cuxour Tew | teu OK wF006231 cuxouT ROS, rat TNVCH Tivo. Mi, vest wNTO-3 TIMERIN WFO06240 ‘cuKour Tenasy 80, 081 ‘WF006250 se :

SWITCHING WAVEFORMS (Cont'd.) ee bo vos a rome ~ -AROY TARYCHL TARYLCL. wor roars exon veut - (ie) wots HOLD-HLDA TIMING a a caer THveL ” THYCL ‘HOL”D seu vu ‘HULDA - | — ‘TOLAY veut eo106 \\--- > sates aR ———__:- or o-7 vonev. fF wove RO,WR tT8s --- woes ze . == oT, Rn neonens . ,

SWITCHING WAVEFORMS (Cont'd.) Tox ToUcK. 4 (CLKIN) Town —| TeKUA Tenex Temicea: Towzct1 ‘euxout TeKo. ToL. TeHCL. TeLct WF006292 TIMER ON 80186 wer TweRn Teurmy |= ‘TMEROUT 2-6 CLOCKS. wFo0ea00 80186 INSTRUCTION TIMINGS © All word-data is located on even-address boundaries. The following instruction timings represent the minimum All jumps and calls include the time required to fetch the execution time in clock cycles for each instruction. The timings opcode of the next instruction at the destination address. given are based on the following assumptions: All instructions which involve memory reference can require © The opcode, along with any data or displacement requifed — on (and in some cases, two) additional clocks above the for execution of a particular instruction, has been pre- " vo) and resides in the ‘at the time itis minimum timings shown. This is due to the asynchronous ° nature of the handshake between the BIU and the Execution © No wait states or bus HOLDS occur. unit.

a AS paps or 2 peat eo : peste en gs zn Sep eg 8 psn an porno weno ‘ Sayre: pt : usin =P A = POP = Pop: weno = ‘Segment regster (reg#o1) | 8 — | Paste we eps an Regt wth accuraslor 3 wep tome fan . vate pt : Fast pon : vere ot ’ HLAT = Tara be to AL " Lede Land EA ate ‘ LDS - Load pointer to 0S (wos 11) | 8 LE5- Lao or £8 wrote) | ‘ LAME = Lond AM wi gs 2 SANE Store AM ito age 3 PUSHE = Push age ° Por =n ts : Shaded areas indicate new 80186 instructions not available in 8086 or 8088 microprocessors. 4 ‘

INSTRUCTION SET SUMMARY (Cont'd.) lameron | FORMAT [Se | comm | “ARITHMETIC ‘DD = Add: Reg/memory wih register to other —-« [COO0O0 dw] modi] 3/10 Inmedate to register / memory (:oc000sw] modooorm | deta | datait's w=01 | 46 Innate cmt om | ances ADC = Add with carry: Reg/memory wih register o einer = [OT 00 aw] ned eg im] a0 Immediate to register/memory sooooosw] madorovm | cata | cats w=01 | lad INC = Increment: Rogister/momory ed 00 Or 315 Register 01000 19 3 SUB = Subtract: Rog/monee nd pe 1 ter ar \\nmediate trom register/memory [sococosw] moatorem [data [ dais w=or | anne SBB = Subtract with borrow: Rog/mamory and register to einer = [OOO TTOdw] mod reg im _| a0 Irnmediate trom register/memory [xocooosw] mdortem | data | dais w=01 | ane DEC = Decrement: Rogistor/mamory Lsiiiiiw[ mod oo tem | ans Rogistor 01001 v9 3 CMP = Compare: Parma wrt ano Register with register/memory ano Immediate with registor/mamory yooooosw] madtitvm [dau [ caatsw-0r | ano AAA = ASCII aust for add 8 DAA = Docimal adjust for add Oo100111 4 AAS = ASCII adjust for subtract 7 DAS = Docimal adjust for subwact ‘4 we = ns naan Rogiste- Byte 25-28 Rogistor-Word 35-97 Momory-Byta 32-38 Momory Wore a8 MUL = Integer mutiply (signed): Rogistor- Byte 25-28 Registor-Word 34-37 Memony-Byia 31-38 Memory Word 0-6 B= Owe toot Rogistor-Byt0 20 Register-Word 38 Memory Byte 35 Memory Word “4 ‘Shaded areas indicate new 80186 instructions not available in 8086 or 8088 microprocessors. Al mnemonics copyright of Intel Corp. 1983

[meron roma | ts am FORMAT Cycies TARMTMETIC Toor 11 = oe ie soa wee Nomen Ee ~ | anit et tr mato ® [AAD ASCI aust for divide 1s CW - Comet nt word 2 CCWD= Convert wrd 16 doe word ‘ Loaie Seheotate Iatrctone: Rego menay by. 7 tnatreton ooo ot ooe non $08 eran AND = hoc Reg/memory and register 19 ether anno | Test = And function 10 Reps no result ete manay a ear ano Inmet ea ad reper ano Imemodate data and accumator aa | one on= or Rox/maner an est eer v0 Inet 1 manny ans Inmet 1 couse om | ren XOR = Exchatve 07 Pa/mamoy a ota Ser ane Immo 1 acauttr ou | enon NOT net piston 3 STRING MANIPULATION: MOVE Hom ta /nr +0 CcuPS = Compare bye/wort sez CAS = Scan by/word 5+150 —~ | L008 = toed yrs to ALIAX eenn STOS = Stor byte/wa from ALIA e+0n our-ouxt ones bien (Etetiee) Shaded areas indicate new 80186 instructions not available in 8086 or 8088 microprocessors. ‘A mnemonic copyright of Intl Cop. 1983

INSTRUCTION SET SUMMARY (Cont'd.) ome cycles STRING MANIPULATION (Continued): Repeated by count in OX MOVE ~ Move sting “ CPS - Compare sting = SOAS = Scan sting 18 L005 = Load sting i $708 = Store sting iD INS = inp sting Seen | Repeats ernbgresanneinct tet be Saeuecare sete tent ctot eines pert tegen ames TPrebtdedalaug Sati teere ta em LRH AIAG fees eye certain gel exude Rawamated CALL = Cate rect wan segment “ Register memory we fndet watin sogrnent Drees intersegrent 2 tect terogrene (modes | bal UMP = Unconditional jump: Sroaiiong "0 Drees witin segment co Regetermamory inrect witin seomant war rect ietersogmant ta loc naregment (roses | bad RET = Return from CALL: Wann segment 6 wien og acing med to 5° = [100010] wawtow | aamnon | * Intersogmant bad Intersegment eting immediate 10 6 bad ‘Shaded areas indicate new 80186 instructions not available in 8086 or 8088 microprocessors. All mnemonics copyright of Intel Corp. 1983

[meron drome |S | cm | FORMAT Cycles: co HOR Bow JE/2 = erp on eausl 200 ana | 19 tae JLIINGE™= snp on fs ot gest of ea ana | Ste SELIG = S009 cs si at got wa jen _— | s2/0NAe =e 00 beow not stove oF oa ans JBE/INA = Jump on below oF equ! not sbove ane \\P1 Jun on pty pry on ns 0 ro on ovation a 48 =u on sn a INEZINZ = Jump on not equal not zero ana INLISGE = Jung on tls str oF en ana ANLE/JG = Jump on not loss © oul ater ana LINB/JAE = Jung on not below above or ex ans INBE/IA-= heron not blow oF eg above ans 4JNP/4PO = Jump on nok pa / par 0 ans {0 = Jo ort ovtow wa 28 uo 0 on wa 00? «Lop x ons LooPz/LOOPE = Loop whe zero oxi ene LOOPNZ/LOOPNE = Lo%p wie not 20 on one JOKE = ump on OX zar0 te | Me taken ~ s | uray ee ee oe r= orp Tyan eesti INTO = interuot on overtow iNT not ‘cs RET = Interrupt return Shaded areas indicate new 80186 instructions not available in 8086 or 8088 microprocessors. All mnemonics copyright of intel Corp. 1983

INSTRUCTION SET SUMMARY (Cont'd.) Clock FORMAT Cycles: PROCESSOR CONTROL CLE = Glee cary {CMC ~ Complement cary STC = Set cary CLD= Gear rection STD Set cirecton CL Clear interop S71 Set intemupt wu Hat WAIT = Wt LOCK = Bus lock roi C= Processor Extnsion Escape (TTT LLL are opcode to processor extonsion) FOOTNOTES REG is assigned according to the following table: The effective Address (EA) of the memory operand is 16-Bit (w= 1) 8-Bit (w=0) computed according to the mod and r/m fields: 00 ax oo at if mod = 11 then 1/m is treated as a REG field oor ox oor CL if mod = 00 then DISP= 0", disp-low and disp-high are o10 BX O10 DL <aent 011 BX 011 BL if mod = 01 then DISP = disp-low sign-extonded to 16-bits, 400 SP $00 AH disp-high is absent 101 BP 401 CH if mod = 10 then DISP = disp-high: disp-low 110 84 10 DH it ¥/m = 000 then EA = (BX) + (SI) + DISP 111 DL 411: BH if 17m = 001 then EA = (BX) + (O)) + DISP if r/m-=010 then EA = (BP) + (SI) + DISP if /m=011 then EA = (BP) + (Dl) + DISP if t/m= 100 then EA = (S) + DISP “The physical addresses of all operands addressed by the BP if r/m-= 101 then EA = (Ol) + DISP , register are computed using the SS segment register. The if r/m-=110 then EA = (BP) + DISP physical addresses of the destination operands of the string if r/m= 111 then EA = (BX) + DISP Primitive operations (those addressed bythe Di! register) are DISP follows 2nd byte of instruction (before data if required) Computed using the ES segment. which may not be overrid- “except if mod = 00 and r/m= 110 then EA = disp-high: disp-iow. SEGMENT OVERRIDE PREFIX 001reg110 reg is assigned according to the following: Segment reg Register oo gS 01 cs 10 ss W Ds

a

PHYSICAL DIMENSIONS (Cont'd.) CGX068 BOTTOM VIEW (Pins facing up) Pa (Releorce Comer [+ wro1esc_——»} oes Nppieee ie 4 Fissesisseal + a] ©@ oo ae ‘| oo YY eo us L s| ©@ V7 eo os eo | ee 1 oo sy 10 eee ‘a Races) on 38 I+ ‘00 298 a *For reference only. All dimensions are measured in inches. BSC is an ANSI standard for Basic Space Centering.

PHYSICAL DIMENSIONS (Cont'd.) PL 068 dhe # q b ft q p fis ge 4 5 a) er es q et q Er ‘it “ rosenas “For reference only, All dimensions are measured in inches. BSC is an ANSI standard for Basic Space Centering.

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PACKAGE OUTLINES* Ceramic DIPs (CD) cD 024 1.235 1.290 po ooo | ds ‘Ses _Semororoooo + +f [+ .005 Min. ‘L 0 # ccd ase a8 — 7150 aa + fie oe ois ta rosoris cp 028 : 143s 1.490 nooo oon ye co Sooo ooo 500 560 150 MIN, ; te roses * For reference only. NOTE: Package dimensions are given in inches. To convert to millimeters, multiply by 25.4. ea eee nets Te conver fo milimeters, mulpy by 254 6-1 1780 a-11

ADVANCED MICRO DEVICES 46D D M@®@ 0257525 gge?7001 2 ms CHAPTER 6 General Information T-90-20 PACKAGE OUTLINES (Continued) Ceramic DIPs (CD) (Continued) cD 040 3035 ~ (098 MAX. AEerae iii ert 88 we e pt 8 it hy <I @ rosa cDVvo40 2.035 2.096, oo > 098 MAX, a ponnannnannaanadi (4\\ + E) Sooo eo oy = Dl 7 Dl >| > 005 MIN. C z e a B i ¢ E ¥ Pe i ty a E] rowes NOTE: Package dimensions are given in inches, To convert to millimeters, multiply by 25.4, 1781 a-i2 62

ADVANCED MICRO DEVICES TbD D - Qes?ses ooe7o0e 4 _ CHAPTER 6 General Information PACKAGE OUTLINES (Continued) 7-90-20 Ceramic Sidebrazed DIPs (SD) SD 040 | : ee Se a apie F ee i ae sll a SD 048 2B |.-soonnx wo aim # : 8 uu! pial pa % 98 : ber rownue NOTE: Package dimensions are given in inches. To convert to millimeters, multiply by 25.4. 6-3

1782 A-13

ADVANCED MICRO DEVICES JbD D ml Oes?ses o0e7003 bm ee CHAPTER 6 T-90-20 General Information ee PACKAGE OUTLINES (Continued) Ceramic Leadless Chip Carriers (CL/CLV) CL 044 084 100 500, 25095" $e BSC A BN ares = ors . 095 | | 250

8 H Bsc she F

022 5 — : NY ss i | 625 MAX: £40 660 ‘PIO sose2se CLV044 an a ii 20 ie | 250 0° 054 aso . 088 it HW It Cr = "~~ - Pairiin LJ ' 1 Se | ous_,| | 1" TE fase ’ i f rae aso BSC Fi oe og Y 4 ‘015 MIN re er Tenby 285 22-4 ; = 7 CI 015 625 MAX.- 860 PD KOM. NOTE: Package dimensions are given in inches. To convert to millimeters, multiply by 25.4, -S ml by 28

1783 A-14 oe

7-90-20 General information PACKAGE OUTLINES (Continued) 68-Pin Square Leadless Chip Carrier (CA2) CA2068 —— =| J i He N A NS Ar , #! LS 8 Eee wwe HUUUKSS

045 MIN, I I

— + _ | ;

1784 B-01 “8

ADVANCED MICRO DEVICES 9bD D m@ 0257525 0027005 T CHAPTER 6 T-90-20 General Information Rabiner oem PACKAGE OUTLINES (Continued) Ceramic Pin-Grid-Array Package (CG/CGX) CGX068 BOTTOM VIEW 1.149, 228, 075 x ‘ones 1.180 (055 (REFERENCE COf ) [10 Bsc————>| ABCDEFGHIJI KL ifteecocboooe ro 2] 00000600000 s| ©o@ ! (Xo) ay 4] Oo dH Coo} , : 1.440 5] ©®@ eo Bsc 7] © i eo 080 2] OO 1 (Xo) 140 s} Ge ! ee ous 1] CODOOHOHOOOG ocd io 90090009 hs (090 x 45° REF. “foo.8se “(@PLACES) | oso cd i OEE 108 1198 PID #075478 NOTE: Package dimensions are given in inches. To convert to millimeters, multiply by 25.4. Sa ic lS ISI

1785 B-02 66