74HC03_V01 SS | Alldatasheet
Document overview
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Technical content
www.siliconsupplies.com Die Size (Unsawn) 1200 x 1350 47 x 53 µm mils Minimum Bond Pad Size 106 x 106 4.17 x 4.17 µm mils Die Thickness 350 (±20) 13.78 (±0.79) µm mils Top Metal Composition Al 1%Si 1.1µm Back Metal Composition N/A – Bare Si High Speed CMOS Logic – 74HC03 Quad 2-Input Open Drain NAND Gate in bare die form Output Drive Capability: 10 LSTTL Loads Low Input Current: 1µA Outputs directly inter face CMOS, NMOS and TTL Operating Voltage Range: 2V to 6V CMOS High Noise Immunity Function compatible with 74LS03. Rev 1.0 16/04/18 Features:
Ordering Information
The following part suffixes apply: No suffix - MIL-STD-883 /2010B Visual Inspection For High Reliability versions of this product please see 54HC03 Supply Formats: Mechanical Specification Default – Die in Waffle Pack (400 per tray capacity) Sawn Wafer on Tape – On request Unsawn Wafer – On request Die Thickness <> 350µm(14 Mils) – On request Assembled into Ceramic Package – On request The 74HC03 is fabricated using a 2.5µm 5V CMOS process and has the same high speed performance of LSTTL combined with CMOS low power consumption. This device is comprised of 3 stages including buffer output, which enables high noise immunity with stable output. With an external pull-up resistor the device can be used in wired AND configuration. This device can be also used as an LED driver and in any other application requiring a current sink. All inputs are protected from damage due to static discharge by internal diode clamps to V CC and Ground.
Description
Die Dimensions in µm (mils) 1200 (47) 1350 (53) PART OBSOLETE - DISCONTINUED
www.siliconsupplies.com d High Speed CMOS Logic – 74HC03 Rev 1.0 16/04/18Pad Layout and Functions 1200µm (47.24 mils) 1350µm (53.15 mils) 0,0 COORDINATES (mm) PAD FUNCTION X Y 1 A1 0.131 0.460 2 B1 0.131 0.153 3 Y1 0.305 0.121 4 A2 0.489 0.121 5 B2 0.786 0.121 6 Y2 0.970 0.131 7 GND 0.980 0.462 8 Y3 0.980 0.764 9 A3 0.950 1.115 10 B3 0.713 1.125 11 Y4 0.543 1.125 12 A4 0.369 1.125 13 B4 0.131 1.091 14 VCC 0.131 0.631 CONNECT CHIP BACK TO VCC OR FLOAT Truth Table Logic Diagram 2 3 4 5 6 9 10 11 12 DIE ID INPUTS OUTPUT A B Y L L H H L H L H Z Z Z L H = High level (steady state) L = Low level (steady state) Z = High Impedance state Pad 14 = VCC Pad 7 = GND PART OBSOLETE - DISCONTINUED
www.siliconsupplies.com PARAMETER SYMBOL MIN MAX UNITS DC Supply Voltage VCC 2 6 V DC Input or Output Voltage VIN ,VOUT 0 VCC V Operating Temperature Range TJ 0 +85 °C VCC = 2.0V 0 1000 VCC = 4.5V 0 500 Input Rise and Fall Time VCC = 6.0V tr, tf 0 400 ns Recommended Operating Conditions3 (Voltages referenced to GND) Absolute Maximum Ratings1 PARAMETER SYMBOL VALUE UNIT DC Supply Voltage (Referenced to GND) VCC -0.5 to +7.0 V DC Input Voltage (Referenced to GND) VIN -1.5 to VCC +1.5 V DC Output Voltage (Referenced to GND) VOUT -0.5 to VCC +0.5 V DC Input Current, per pin IIN ±20 mA DC Output Current, per pin IOUT ±25 mA DC VCC or GND Current, per pin ICC ±50 mA Power Dissipation in Still Air2 P D 750 mW Storage Temperature Range TSTG -65 to 150 °C High Speed CMOS Logic – 74HC03 Rev 1.0 16/04/18 1. Operation above the absolute maximum rating may cause device failure. Operation at the absolute maximum ratings, for extended periods, may reduce device reliability. 2. Measured in plastic DIP package, results in die form are dependent on die attach and assembly method. 3. This device contains protection circuitry to guard against dama ge due to high static voltages or electric fields. However, pr ecautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-im pedance circuit. For proper opera tion, VIN and V OUT should be constrained to the range GND ≤ (V IN or VOUT) ≤ VCC. Unused inputs must always be tied to an appropriate logic vo ltage level (e.g., either GND or VCC). Unused outputs must be left open. LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE4 UNITS 2.0V 1.5 1.5 1.5 4.5V 3.15 3.15 3.15 Minimum High-Level Input Voltage VIH 6.0V VOUT = 0.1V or VCC -0.1V │IOUT│≤ 20µA 4.2 4.2 4.2 V 2.0V 0.5 0.5 0.5 4.5V 1.35 1.35 1.35 Maximum Low-Level Input Voltage VIL 6.0V VOUT = 0.1V or VCC -0.1V │IOUT│≤ 20µA 1.8 1.8 1.8 V PART OBSOLETE - DISCONTINUED
High Speed CMOS Logic – 74HC03 Rev 1.0 16/04/18 LIMITS PARAMETER SYMBOL VCC CONDITIONS UNITS 25°C 85°C FULL RANGE4 2.0V 0.1 0.1 0.1 4.5V 0.1 0.1 0.1 VIN = VIH │IOUT│≤ 20µA 6.0V 0.1 0.1 0.1 4.5V VIN = VIH │IOUT│≤ 4.0mA 0.26 0.33 0.33 Maximum Low-Level Output Voltage VOL V 6.0V VIN = VIH │IOUT│≤ 5.2mA 0.26 0.33 0.33 Maximum Input Leakage Current IIN 6.0V VIN = VCC or GND ±0.1 ±1.0 ±1.0 µA Maximum 3-State leakage current IOZ 6.0V VOUT=VCC or GND VIN = VIL or VIH ±0.5 ±5.0 ±5.0 µA Maximum Quiescent Supply Leakage Current ICC 6.0V VIN = VCC or GND IOUT = 0µA 1 10 10 µA LIMITS PARAMETER SYMBOL VCC CONDITIONS UNITS 25°C 85°C FULL RANGE4 2.0V 120 150 150 4.5V 24 30 30 Maximum Propagation Delay, CL = 50pF, A or B to Y (Figures 2,4) tPLZ, tPZL ns tr = tf = 6ns 6.0V 20 26 26 2.0V 75 95 95 4.5V 15 19 19 Maximum Output Transition Time, CL = 50pF, any Output (Figures 2,4) tTHL ns tr = tf = 6ns 6.0V 13 16 16 Maximum Input Capacitance CIN - - 10 10 10 pF Maximum Three-State Output Capacitance (Output in High- Impedance State) COUT - - 10 10 10 pF TYPICAL Power Dissipation TA = 25°C, pF Capacitance (Per Gate)6 CPD - VCC = 5.0V 8 5. Not production tested in die form, characterized by chip design and tested in package LAT. 6. Used to determine the no-load dynamic power consumption: PD = CPD VCC f + ICC VCC. Page 4 of 5 www.siliconsupplies.com PART OBSOLETE - DISCONTINUED