74HC02 SS | Alldatasheet
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High Speed CMOS Logic – 74HC02 Quad 2-Input NOR Gates in bare die form Output Drive Capability: 10 LSTTL Loads Low Input Current: 1µA Outputs directly inter face CMOS, NMOS and TTL Die Size (Unsawn) 610 x 610 24 x 24 µm mils Minimum Bond Pad Size 85 x 85 3.35 x 3.35 µm mils Die Thickness 350 (±20) 13.78 (±0.79) µm mils Top Metal Composition Al 1%Si 1.1µm Back Metal Composition N/A – Bare Si Operating Voltage Range: 2V to 6V Function compatible with 74LS02 High Noise Immunity CMOS process Rev 1.0 22/04/19 Features:
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Description
The 74HC02 2-Input NOR Gate is fabricated on a .35µm advanced CMOS process combining high speed LSTTL performance with CMOS low power. The device performs the Boolean function Y = (A + B) or Y = A • B in positive logic. Internal circuitry comprises of three stages and includes buffered output for high noise immunity and stability. Inputs are compatible with standard CMOS outputs; with pull-up resistors, they are compatible with LSTTL outputs. The product die size is significantly smaller than industry peers due to its re-design and production using a more advanced CMOS process. Die Dimensions in µm (mils) The following part suffixes apply: 610 (24) No suffix - MIL-STD-883 /2010B Visual Inspection For High Reliability versions of this product please see 54HC02 610 (24) Supply Formats: Mechanical Specification Default – Die in Waffle Pack (400 per tray capacity) Sawn Wafer on Tape – On request Unsawn Wafer – On request Die Thickness <> 350µm(14 Mils) – On request Assembled into Ceramic Package – On request Page 1 of 5 www.siliconsupplies.com A ll data sheet.com
d High Speed CMOS Logic – 74HC02 Rev 1.0 22/04/19 COORDINATES (µm) PAD FUNCTION X Y 1 1Y -230 -52 2 1A -230 -230 3 1B -95 -230 4 2Y 0 -230 5 2A 95 -230 6 2B 230 -230
7 GND 230 -45
14 VCC -230 45
CONNECT CHIP BACK TO VCC OR FLOAT Pad Layout and Functions Logic Diagram 610µm (24 mils) 610µm (24 mils) 0,0 Pad 14 = VCC Pad 7 = GND 2 3 4 5 6 9 10 11 Truth Table INPUTS OUTPUT A B Y L L H H L H L H H L L L H = High level (steady state) L = Low level (steady state) Page 2 of 5 www.siliconsupplies.com A ll data sheet.com
www.siliconsupplies.com High Speed CMOS Logic – 74HC02 Rev 1.0 22/04/19 PARAMETER SYMBOL MIN MAX UNITS Supply Voltage VCC 2 6 V DC Input or Output Voltage VIN ,VOUT 0 VCC V Operating Temperature Range TA 0 +85 °C VCC = 2V 0 1000 VCC = 4.5V 0 500 Input Rise or Fall Times tr, tf VCC = 6.0V 0 400 ns Recommended Operating Conditions2 (Voltages referenced to GND) Absolute Maximum Ratings1 PARAMETER SYMBOL VALUE UNIT DC Supply Voltage (Referenced to GND) VCC -0.5 to +7.0 V DC Input Voltage (Referenced to GND) VIN -0.5 to VCC +0.5 V DC Output Voltage (Referenced to GND) VOUT -0.5 to VCC +0.5 V DC Input Current IIN ±20 mA DC Output Current, per pad IOUT ±25 mA DC Supply Current, VCC or GND ICC ±50 mA Power Dissipation in Still Air PD 750 mW Storage Temperature Range TSTG -65 to 150 °C 2. This device contains protection circuitry to guard against dama ge due to high static voltages or electric fields. However, pr ecautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance ci rcuit. For proper operation, VIN and V OUT should be constrained to the range GND ≤ (V IN or VOUT) ≤ VCC. Unused inputs must always be tied to an appropriate logic vo ltage level (e.g., either GND or V CC). Unused outputs must be left open. 1. Operation above the absolute maximum rating may cause device failure. Operation at the absolute maximum ratings, for extended periods, may reduce device reliability. LIMITS PARAMETER SYMBOL VCC CONDITIONS 0°C to 25°C ≤ 85°C UNITS 2.0V 1.5 1.5 3.0V 2.1 2.1 4.5V 3.15 3.15 Minimum High-Level Input Voltage VIH 6.0V VOUT = 0.1V or VCC -0.1V │IOUT│≤ 20µA 4.2 4.2 V 2.0V 0.5 0.5 3.0V 0.9 0.9 4.5V 1.35 1.35 Maximum Low-Level Input Voltage VIL 6.0V VOUT = 0.1V or VCC -0.1V │IOUT│≤ 20µA 1.8 1.8 V A ll data sheet.com
High Speed CMOS Logic – 74HC02 Rev 1.0 22/04/19 LIMITS PARAMETER 3. Not production tested in die form, characterized by chip design and tested in package LAT. 4. Used to determine the no-load dynamic power consumption: PD = CPD VCC f + ICC VCC. SYMBOL VCC CONDITIONS ≤ 85°C UNITS 0°C to 25°C 2.0V 1.9 1.9 4.5V 4.4 4.4 VIN = VIH or VIL │IOUT│≤ 20µA 6.0V 5.9 5.9 V 3.0V VIN = VIH or VIL │IOUT│≤ 2.4mA 2.48 2.34 4.5V VIN = VIH or VIL │IOUT│≤ 4.0mA 3.98 3.84 Minimum High-Level Output Voltage VOH 6.0V VIN = VIH or VIL │IOUT│≤ 5.2mA 5.48 5.34 V 2.0V 0.1 0.1 4.5V 0.1 0.1 VIN = VIL or VIL │IOUT│≤ 20µA 6.0V 0.1 0.1 V 3.0V VIN = VIL or VIL │IOUT│≤ 2.4mA 0.26 0.33 4.5V VIN = VIL or VIL │IOUT│≤ 4.0mA 0.26 0.33 Maximum Low-Level Output Voltage VOL 6.0V VIN = VIL or VIL │IOUT│≤ 5.2mA 0.26 0.33 V Maximum Input Leakage Current IIN 6.0V VIN = VCC or GND ±0.1 ±1.0 µA Maximum Quiescent VIN = VCC or GND Supply Leakage Current3 ICC 6.0V IOUT = 0µA 1 10 µA LIMITS PARAMETER SYMBOL VCC CONDITIONS UNITS 0°C to 25°C ≤ 85°C 2.0V 75 95 3.0V 30 40 4.5V 15 19 Maximum Propagation Delay, Input A or B to CL = 50pF, Output Y (Figure 1,2) tPLH, tPHL ns tr = tf = 6ns 6.0V 13 16 2.0V 75 95 3.0V 30 40 4.5V 15 19 Maximum Output Rise and Fall Time, CL = 50pF, Any Output (Figure 1,2) tTLH, tTHL ns tr = tf = 6ns 6.0V 13 16 Page 4 of 5 www.siliconsupplies.com A ll data sheet.com
www.siliconsupplies.com High Speed CMOS Logic – 74HC02 Rev 1.0 22/04/19 AC Electrical Characteristics Continued3 LIMITS PARAMETER DISCLAIMER: The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Silicon Supplies Ltd hereby disclaims any and all warranties and liabilities of any kind. LIFE SUPPORT POLICY: Silicon Supplies Ltd components may be used in life support devices or systems only with the express written approval of Silicon Supplies Ltd, if a failure of such components can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Switching Waveform DUT CL* OUTPUT TEST POINT Test Circuit * Includes all probe and jig capacitance Figure 1 – Propagation Delay & Output Transition Time Figure 2 SYMBOL VCC CONDITIONS UNITS 0°C to 25°C ≤ 85°C Maximum Input Capacitance CIN - - 10 10 pF TYPICAL Power Dissipation TA = 25°C, pF Capacitance Per Gate4 CPD - VCC =5.0V 22 3. Not production tested in die form, characterized by chip design and tested in package LAT. 4. Used to determine the no-load dynamic power consumption: PD = CPD VCC f + ICC VCC. A ll data sheet.com