64LC20

CAT64LC10 CATALYST | Alldatasheet

Document overview

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Technical content

Y RESET GND RDY/ BUSY VCC CS SK RESET GND DO DI CAT64LC10/20/40 1K/2K/4K-Bit SPI Serial EEPROM

FEATURES

I Low power CMOS technology I 2.5V to 6.0V operation I Self-timed write cycle with auto-clear I Hardware reset pin I Hardware and software write protection I Commercial, industrial and automotive temperature ranges I Power-up inadvertant write protection I RDY/ BSYBSYBSYBSYBSY pin for end-of-write indication I 1,000,000 program/erase cycles I 100 year data retention

DESCRIPTION

The CAT64LC10/20/40 is a 1K/2K/4K-bit Serial EEPROM which is configured as 64/128/256 registers by 16 bits. Each register can be written (or read) serially by using the DI (or DO) pin. The CAT64LC10/20/40 is manufactured using Catalyst’s advanced CMOS EEPROM floating gate technology. It is designed to endure 1,000,000 program/erase cycles and has a data retention of 100 years. The device is available in 8-pin DIP, SOIC and TSSOP packages. BLOCK DIAGRAM PIN CONFIGURATION PIN FUNCTIONS Pin Name Function CS Chip Select SK Clock Input DI Serial Data Input DO Serial Data Output VCC +2.5V to +6.0V Power Supply GND Ground RESET Reset RDY/BUSY Ready/BUSY Status © 2004 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice Doc. No. 1021, Rev. C 64LC10/20/40 F02 VCC ADDRESS DECODER MEMORY ARRAY 64/128/256 x 16 DATA REGISTER MODE DECODE LOGIC CLOCK GENERATOR OUTPUT BUFFER DOSK CS DI RESET GND RDY/BUSY

Doc. No. 1021, Rev. C ABSOLUTE MAXIMUM RATINGS* Voltage on any Pin with Package Power Dissipation *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. RELIABILITY CHARACTERISTICS Symbol Parameter Min. Max. UnitsReference Tes t Method N END (3) Endurance 1,000,000 Cycles/Byte MIL-STD-883, Test Method 1033 TDR (3) Data Retention 100 Years MIL-STD-883, Test Method 1008 VZAP (3) ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015 ILTH (3)(4) Latch-Up 100 mA JEDEC Standard 17 CAPACITANCE (TA = 25°C, f= 1.0 MHz, VCC =6.0V) Symbol Test Max. Units Conditions C I/O(3) Input/Output Capacitance (DO, RDY/BSY)8 p F V I/O = 0V C IN(3) Input Capacitance (CS, SK, DI, RESET) 6 pF V IN = 0V Note: (1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) This parameter is tested initially and after a design or process change that affects the parameter. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V CC +1V.

Doc. No. 1021, Rev. C D.C. OPERATING CHARACTERISTICS VCC = +2.5V to +6.0V, unless otherwise specified. Note: (1) VOH and VOL spec applies to READY/BUSY pin also Limits Sym. Parameter Min. Typ. Max. UnitsTes t Conditions ICC Operating Current 2.5V 0.4 mA f SK = 250 kHz EWEN, EWDS, READ 6.0V 1 mA f SK = 1 MHz ICCP Program Current 2.5V 2 mA 6.0V 3 mA ISB (1) Standby Current 3 µAV IN = GND or VCC CS = VCC ILI Input Leakage Current 2 µAV IN = GND to VCC ILO Output Leakage Current 10 µAV OUT = GND to VCC VIL Low Level Input Voltage, DI –0.1 V CC x 0.3 V VIH High Level Input Voltage, DI V CC x 0.7 V CC + 0.5 V VIL Low Level Input Voltage, –0.1 V CC x 0.2 V CS, SK, RESET VIH High Level Input Voltage, V CC x 0.8 V CC + 0.5 V CS, SK, RESET VOH (1) High Level Output Voltage 2.5V VCC – 0.3 V I OH = –10µA 6.0V V CC – 0.3 V I OH = –10µA

2.4 V I OH = –400µA

VOL (1) Low Level Output Voltage 2.5V 0.4 V I OL = 10µA 6.0V 0.4 V I OL = 2.1mA

Doc. No. 1021, Rev. C Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) This parameter is sampled but not 100% tested. (3) t PUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. WRITE CYCLE LIMIITS Symbol Parameter Min. Max. Units tWR Program Cycle Time 2.5V 10 ms 4.5V–6.0V 5 A.C. OPERATING CHARACTERISTICS VCC = +2.5V to +6.0V, unless otherwise specified. Limits Symbol Parameter Min. Typ. Max. Units tCSS CS Setup Time 100 ns tCSH CS Hold Time 100 ns tDIS DI Setup Time 200 ns tDIH DI Hold Time 200 ns tPD1 Output Delay to 1 300 ns tPD0 Output Delay to 0 300 ns tHZ (2) Output Delay to High Impendance 500 ns tCSMIN Minimum CS High Time 250 ns tSKHI Minimum SK High Time 2.5V 1000 ns 4.5V–6.0V 400 tSKLOW Minimum SK Low Time 2.5V 1000 ns 4.5V–6.0V 400 tSV Output Delay to Status Valid 500 ns fSK Maximum Clock Frequency 2.5V 250 kHz 4.5V–6.0V 1000 tRESS Reset to CS Setup Time 0 ns tRESMIN Minimum RESET High Time 250 ns tRESH RESET to READY Hold Time 0 ns tRC Write Recovery 100 ns POWER-UP TIMING (1)(3) Symbol Parameter Min. Max. Units tPUR Power-Up to Read Operation 10 µs tPUW Power-Up to Program Operation 1 ms

Figure 1. A.C. Testing Input/Output Waveform (2)(3(4) (CL = 100 pF) (2) Input Rise and Fall Times (10% to 90%) < 10 ns. (4) Input and Output Timing Reference = VCC x 0.3 and VCC x 0.7.

memory intended for use with all standard controllers. 16 format. All instructions are based on an 8-bit format. polled during a WRITE operation. Figure 2. Sychronous Data Timing Figure 3. Read Instruction Timing

10101000 ADDRESS*

Figure 4. Write Instruction Timing Figure 5. Ready/BUSYBUSYBUSYBUSYBUSY Status Instruction Timing

10100100 ADDRESS* D15 D0

An alternative to get RDY/BSY status is from the DO pin. will cause the DO pin to output the RDY/BSY status. operation and output a READY status. Figure 6. RESET During BUSYBUSYBUSYBUSYBUSY Instruction Timing Figure 7. EWEN Instruction Timing

5064 FHD F09

such as READ, EWEN and EWDS. preceded by an execution of the EWEN instruction. EWDS has been executed or a power-down has occured. affected by the RESET input. Figure 8. EWDS Instruction Timing

Doc. No. 1021, Rev. C

ORDERING INFORMATION

Notes: (1) The device used in the above example is a 64LC10SI-TE13 (SOIC, Industrial Temperature, Tape & Reel) P: PDIP S: SOIC (JEDEC) J: SOIC (JEDEC) U: TSSOP UR: TSSOP (Rotated) L: PDIP (Lead free, Halogen free) V: SOIC (JEDEC) (Lead free, Halogen free) W: SOIC (JEDEC) (Lead free, Halogen free) Y: TSSOP (Lead free, Halogen free) YR: TSSOP (Rotated) (Lead free, Halogen free)

Doc. No. 1021, Rev. C PACKAGING INFORMATION 8-LEAD TSSOP (U)

7.72 TYP

4.16 TYP

(1.78 TYP)

0.42 TYP

0.65 TYP

LAND P ATTERN RECOMMEND ATION -A- -B- 3.2 6.4 ABC0.2 8 5 3.0 + 0.1 4.4 + 0.1 ALL LEAD TIPS PIN #1 IDENT. 1 4 ALL LEAD TIPS 1.1 MAX TYP 0.1 C (0.9) 0.10 + 0.05 TYP 0.19 - 0.30 TYP

0.3 M A B S C S

0.09 - 0.20 TYP 0.6+0.1 SEATING PLANE GAGE PLANE 0.25 o - 8 o DETAIL A -C-

Doc. No. 1021, Rev. C Catalyst Semiconductor, Inc. Corporate Headquarters

1250 Borregas Avenue

Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catalyst-semiconductor.com Publication #: 1021 Revison: C Issue date: 11/3/04 Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: DPP ™ AE 2 ™ Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete.

REVISION HISTORY

Date Rev. Reason 9/3/2004 B Added Green packages in all areas Updated DC Operating Characteristics table & notes 11/17/2004 C Changed I SB from 1µA, Max to 3µA, Max in DC Operating Characteristics table