54VHC373

54VHC373 SS | Alldatasheet

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Very High Speed CMOS Logic - 54VHC373 8-bit transparent D-Type Latch with 3-State Outputs in bare die form Rev 1.0 26/09/20 Description Features:  High Speed: t PD = 7.2ns (MAX) VCC = 5V Die Size (Unsawn) 1630 x 1630 64 x 64 µm mils Minimum Bond Pad Size 108 x 108 4.25 x 4.25 µm mils Die Thickness 350 (±20) 13.78 (±0.79) µm mils Top Metal Composition Al 1%Si 1.1µm Back Metal Composition N/A – Bare Si  Outputs Sink/Source 8mA  Outputs directly inter face CMOS, NMOS and TTL  Low Input Current: 1µA  Operating Voltage Range: 2V to 5.5V  Replacement for 54HC373, 54AC373, 54AHC373  Full Military Temperature Range.

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The following part suffixes apply:  No suffix - MIL-STD-883 /2010B Visual Inspection  “ H” - MIL-STD-883 /2010B Visual Inspection + MIL-PRF-38534 Class H LAT  “ K” - MIL-STD-883 /2010A Visual Inspection (Space) + MIL-PRF-38534 Class K LAT LAT = Lot Acceptance Test. For further information on LAT process flows see below. www.siliconsupplies.com\\quality\\bare-die-lot-qualification Supply Formats: Mechanical Specification  Default – Die in Waffle Pack (100 per tray capacity)  Sawn Wafer on Tape – On request  Unsawn Wafer – On request  Die Thickness <> 350µm(14 Mils) – On request  Assembled into Ceramic Package – On request The 54VHC373 consists of eight D-type transparent latches fabricated using a 1.5µm 5V advanced CMOS process to combine high speed performance LSTTL performance with CMOS low power consumption. Each latch is equipped with separate D-Type inputs and 3-State outputs for bus oriented applications. Data output changes asynchronously and data may be latched even when the outputs are not enabled. Device inputs accept standard CMOS outputs or LSTTL outputs using pull-up resistors. All inputs are equipped with protection circuits against static discharge and transient excess voltage. Die Dimensions in µm (mils) 1630 (64) 1630 (64) Page 1 of 7 www.siliconsupplies.com All d ata sheet.com

www.siliconsupplies.com d Very High Speed CMOS Logic - 54VHC373 Rev 1.0 26/09/20Pad Layout and Functions Logic Diagram COORDINATES (mm) PAD FUNCTION X Y 1 OE 0.149 0.489 2 1Q 0.149 0.319 3 1D 0.182 0.149 4 2D 0.498 0.149 5 2Q 0.674 0.149 6 3Q 0.855 0.149 7 3D 1.025 0.149 8 4D 1.341 0.149 9 4Q 1.379 0.319 10 GND 1.379 0.499 11 LE 1.379 1.0275 12 5Q 1.379 1.2085 13 5D 1.341 1.3785 14 6D 1.025 1.3785 15 6Q 0.855 1.3785 16 7Q 0.674 1.3785 17 7D 0.498 1.3785 18 8D 0.182 1.3785 19 8Q 0.149 1.2085 20 VCC 0.149 1.0385 21 VCC 0.149 0.722 CONNECT CHIP BACK TO VCC OR FLOAT INPUTS OUTPUT OE LE D Q L L L H H H L X H L X X H L No Change Z H = High level (steady state) L = Low level (steady state) Z = High Impedance X = Don’t care Truth Table Pad 10 = GND, Pad 20 & 21 = VCC 1630µm (64.17 mils) 1630µm (64.17 mils) 1 3 4 5 6 7 8 1314 15 16 17 18 DIE ID 0,0 All d ata sheet.com

www.siliconsupplies.com Very High Speed CMOS Logic - 54VHC373 Rev 1.0 26/09/20 Recommended Operating Conditions3 (Voltages referenced to GND) Absolute Maximum Ratings1 PARAMETER SYMBOL VALUE UNIT DC Supply Voltage (Referenced to GND) VCC -0.5 to +7.0 V DC Input Voltage (Referenced to GND) VIN -0.5 to +7.0 V DC Output Voltage (Referenced to GND) VOUT -0.5 to VCC +0.5 V DC Input Current, per pad IIN ±20 mA DC Output Current, per pad IOUT ±25 mA DC Supply Current, VCC or GND ICC ±75 mA Power Dissipation in Still Air2 P D 180 mW Storage Temperature Range TSTG -65 to 150 °C 3. This device contains protection circuitry to guard against dama ge due to high static voltages or electric fields. However, pr ecautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance ci rcuit. For proper operation, VIN and V OUT should be constrained to the range GND ≤ (V IN or VOUT) ≤ VCC. Unused inputs must always be tied to an appropriate logic vo ltage level (e.g., either GND or V CC). Unused outputs must be left open. 1. Operation above the absolute maximum rating may cause device failure. Operation at the absolute maximum ratings, for extended periods, may reduce device reliability. 2. Measured in plastic DIP package, results in die form are dependent on die attach and assembly method. LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE4 UNITS 2.0V 1.50 1.50 1.50 3.0V 2.10 2.10 2.10 Minimum High-Level Input Voltage VIH 5.5V VOUT = 0.1V or VCC -0.1V │IOUT│≤ 20µA 3.85 3.85 3.85 V 2.0V 0.50 0.50 0.50 3.0V 0.90 0.90 0.90 Maximum Low-Level Input Voltage VIL 5.5V VOUT = 0.1V or VCC -0.1V │IOUT│≤ 20µA 1.65 1.65 1.65 V 2.0V 1.92 1.90 1.90 3.0V 2.92 2.90 2.90 4.5V 4.42 4.40 4.40 5.5V VIN = VIH or VIL │IOUT│-50µA 5.52 5.40 5.40 3.0V VIN = VIH or VIL │IOUT│-4mA 2.58 2.48 2.40 Minimum High-Level Output Voltage VOH 4.5V VIN = VIH or VIL │IOUT│-8mA 3.94 3.80 3.70 V PARAMETER SYMBOL MIN MAX UNITS DC Supply Voltage VCC 2 5.5 V DC Input or Output Voltage VIN ,VOUT 0 VCC V Operating Temperature Range TJ -55 +125 °C Output Current IOUT - ±8 mA VCC = 3.3V 0 100 Input Rise and Fall Time VCC = 5.5V tr, tf 0 20 ns/V All d ata sheet.com

www.siliconsupplies.com Very High Speed CMOS Logic - 54VHC373 Rev 1.0 26/09/20 LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE4 UNITS CL = 15pF 11.4 13.5 14.5 3.3V ±10% CL = 50pF 14.9 17.0 19.0 CL = 15pF 7.2 8.5 9.0 Maximum Propagation Delay, D to Q, (Figure 1,5) tPLH, tPHL ±10% CL = 50pF 9.2 10.5 11.5 ns CL = 15pF 11.0 13.0 14.0 3.3V ±10% CL = 50pF 14.5 16.5 18.5 CL = 15pF 7.2 8.5 9.0 Maximum Propagation Delay, LE to Q, (Figure 2,5) tPLH, tPHL ±10% CL = 50pF 9.2 10.5 11.5 ns 3.3V ±10% 13.2 15.0 17.0 Maximum Propagation Delay, OE to Q, (Figure 3,6) tPLZ, tPHZ ±10% CL = 50pF 9.2 10.5 11.5 ns CL = 15pF 11.4 13.5 14.5 3.3V ±10% CL = 50pF 14.9 17.0 19.0 CL = 15pF 8.1 9.5 10.5 Maximum Propagation Delay, OE to Q, (Figure 3,6) tPZL, tPZH ±10% CL = 50pF 10.1 11.5 13.0 ns 5. Not production tested in die form, characterized by chip design. LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE4 UNITS 2.0V 0.09 0.10 0.10 3.0V 0.09 0.10 0.10 4.5V 0.09 0.10 0.10 5.5V VIN = VIH or VIL │IOUT│= 50µA 0.09 0.10 0.10 3.0V VIN = VIH or VIL │IOUT│= 4mA 0.36 0.44 0.50 Maximum Low-Level Output Voltage VOL 4.5V VIN = VIH or VIL │IOUT│= 8mA 0.36 0.44 0.50 V Maximum Input Leakage Current IIN 5.5V VIN = VCC or GND ±0.1 ±1.0 ±2.0 µA Maximum 3-State Leakage Current IOZ 5.5V High Z Output, VIN = VIL or VIH, VOUT=VCC or GND ±0.25 ±2.5 ±10 µA Maximum Quiescent Supply Leakage Current4 ICC 5.5V VIN = VCC or GND │IOUT│≤ 0µA 4 40 80 µA All d ata sheet.com

www.siliconsupplies.com Very High Speed CMOS Logic - 54VHC373 Rev 1.0 26/09/20 LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE4 UNITS Maximum Input Capacitance CIN 5V ±10% CL = 50pF 10 10 10 pF Maximum 3-State Output Capacitance COUT 5V ±10% CL = 50pF 12 12 12 pF LIMITS Power Dissipation Capacitance7 CPD - TJ = 25°C, VCC =5.0V 54 pF 6. Not production tested in die form, characterized by chip design. 7. Used to determine the no-load dynamic power consumption: PD = CPD VCC f + ICC VCC. Timing Requirements6 LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE4 UNITS CL = 15pF 4.0 4.0 4.0 3.3V ±10% CL = 50pF 4.0 4.0 4.0 CL = 15pF 4.0 4.0 4.0 Minimum Setup Time, D to LE (Figure 4) tSU ±10% CL = 50pF 4.0 4.0 4.0 ns CL = 15pF 1.0 1.0 1.0 3.3V ±10% CL = 50pF 1.0 1.0 1.0 CL = 15pF 1.0 1.0 1.0 Minimum Hold Time, LE to D (Figure 4) th ±10% CL = 50pF 1.0 1.0 1.0 ns CL = 15pF 5.0 5.0 5.0 3.3V ±10% CL = 50pF 5.0 5.0 5.0 CL = 15pF 5.0 5.0 5.0 Minimum Pulse Width, LE (Figure 4) tw ±10% CL = 50pF 5.0 5.0 5.0 ns 3.3V ±10% 1.5 1.5 1.5 Propagation delay difference between outputs tOSLH,tOSHL ±10% CL = 50pF 1.0 1.0 1.0 ns All d ata sheet.com