54LVU04 SS | Alldatasheet
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Low Voltage CMOS Logic – 54LVU04 rm Rev 1.0 27/07/19 Low Voltage CMOS Un-buffered Hex Inverter in bare die fo Output Drive Capability: 10 LSTTL Loads Low Input Current: 1µA Inputs directly accept TTL (V CC 2.7V - 3.6V) Outputs directly inter face CMOS, NMOS and TTL Operating Voltage Range: 1V to 5.5V Improved direct replacement for 54HCU04 High Noise Immunity CMOS process. Features:
Ordering Information
The following part suffixes apply: No suffix - MIL-STD-883 /2010B Visual Inspection “ H” - MIL-STD-883 /2010B Visual Inspection + MIL-PRF-38534 Class H LAT “ K” - MIL-STD-883 /2010A Visual Inspection (Space) + MIL-PRF-38534 Class K LAT LAT = Lot Acceptance Test. For further information on LAT process flows see below. www.siliconsupplies.com\\quality\\bare-die-lot-qualification Supply Formats: Mechanical Specification Default – Die in Waffle Pack (100 per tray capacity) Sawn Wafer on Tape – On request Unsawn Wafer – On request Die Thickness <> 350µm(14 Mils) – On request Assembled into Ceramic Package – On request
Description
The 54LVU04 Hex Inverter consists of six independent inverter gates performing the Boolean function Y = Ᾱ in positive logic. The device is an upgraded replacement for industry standard 54HCU04 and is optimised for low voltage operation. Device inputs are compatible with standard CMOS outputs and also accept TTL directly with a supply between 2.7 and 3.6V. Un-buffered outputs produce lower linear gain for increased compatibility + reliability in crystal oscillator related applications. All inputs are protected against ESD and excess voltage transients. Die Dimensions in µm (mils) 1330 (52) 1420 (56) Die Size (Unsawn) 1330 x 1420 52 x 56 µm mils Minimum Bond Pad Size 108 x 108 4.25 x 4.25 µm mils Die Thickness 350 (±20) 13.78 (±0.79) µm mils Top Metal Composition Al 1%Si 1.1µm Back Metal Composition N/A – Bare Si Page 1 of 6 www.siliconsupplies.com PART OBSOLETE - DISCONTINUED
www.siliconsupplies.com Low Voltage CMOS Logic – 54LVU04 Rev 1.0 27/07/19Pad Layout and Functions Logic Diagram 1200µm (47.24 mils) 1350µm (53.15 mils) COORDINATES (mm) PAD FUNCTION X Y 1 1A 0.130 0.463 2 1Y 0.130 0.230 3 2A 0.381 0.126 4 2Y 0.616 0.126 5 3A 0.881 0.126 6 3Y 1.116 0.126 7 GND 1.115 0.631 8 4Y 1.115 0.846 9 4A 1.115 1.181 10 5Y 0.804 1.194 11 5A 0.569 1.194 12 6Y 0.378 1.194 13 6A 0.143 1.194 14 VCC 0.130 0.813 CONNECT CHIP BACK TO VCC OR FLOAT DIE ID 10 9 6 5 4 3 11 12 13 Truth Table INPUTS A OUTPUT Y H L L H H = High level (steady state) L = Low level (steady state) Pad 14 = VCC Pad 7 = GND PART OBSOLETE - DISCONTINUED
www.siliconsupplies.com Low Voltage CMOS Logic – 54LVU04 Rev 1.0 27/07/19Absolute Maximum Ratings1 PARAMETER SYMBOL VALUE UNIT DC Supply Voltage (Referenced to GND) VCC -0.5 to +7.0 V DC Input Voltage (Referenced to GND) VIN -0.5 to VCC +0.5 V DC Output Voltage (Referenced to GND) VOUT -0.5 to VCC +0.5 V DC Input Current IIN ±20 mA DC Output Current, per pad IOUT ±50 mA DC Supply Current, VCC or GND, per pad ICC ±50 mA Power Dissipation in Still Air2 P D 750 mW Storage Temperature Range TSTG -65 to 150 °C PARAMETER SYMBOL MIN MAX UNITS Supply Voltage VCC 1 5.5 V DC Input or Output Voltage VIN ,VOUT 0 VCC V Operating Temperature Range TJ -55 +125 °C VCC = 1V ≤ VCC< 2V 0 500 VCC = 2V ≤ VCC< 2.7V 0 200 VCC = 2.7V ≤ VCC< 3.6V 0 100 Input Rise or Fall Times tr, tf VCC = 3.6V ≤ VCC< 5.5V 0 50 ns Recommended Operating Conditions3 (Voltages referenced to GND) 3. This device contains protection circuitry to guard against dama ge due to high static voltages or electric fields. However, pr ecautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance ci rcuit. For proper operation, VIN and V OUT should be constrained to the range GND ≤ (V IN or VOUT) ≤ VCC. Unused inputs must always be tied to an appropriate logic vo ltage level (e.g., either GND or V CC). Unused outputs must be left open. LIMITS 1. Operation above the absolute maximum rating may cause device failure. Operation at the absolute maximum ratings, for extended periods, may reduce device reliability. 2. Measured in plastic DIP package, results in die form are dependent on die attach and assembly method. PARAMETER SYMBOL V CC CONDITIONS 25°C 85°C FULL RANGE 4 UNITS 1.2V 1.0 1.0 1.0 2.0V 1.6 1.6 1.6 2.7V 2.4 2.4 2.4 3.0V 2.4 2.4 2.4 3.6V 2.4 2.4 2.4 4.5V 3.6 3.6 3.6 Minimum High-Level Input Voltage VIH 5.5V VOUT = 0.1V or VCC -0.1V │IOUT│≤ 20µA 4.4 4.4 4.4 V PART OBSOLETE - DISCONTINUED
Low Voltage CMOS Logic – 54LVU04 Rev 1.0 27/07/19 LIMITS PARAMETER SYMBOL VCC CONDITIONS UNITS 25°C 85°C FULL RANGE4 1.2V 0.2 0.2 0.2 2.0V 0.4 0.4 0.4 2.7V 0.5 0.5 0.5 3.0V 0.5 0.5 0.5 3.6V 0.5 0.5 0.5 4.5V 0.9 0.9 0.9 VOUT = 0.1V or VCC -0.1V │IOUT│≤ 20µA Minimum Low-Level Input Voltage VIL V 5.5V 1.1 1.1 1.1 1.2V 1.05 1.0 1.0 2.0V 1.85 1.8 1.8 2.7V 2.55 2.5 2.5 3.0V 2.85 2.8 2.8 VIN = VIH or VIL V 3.6V 3.45 3.4 3.4 │IOUT│≤ 100µA 4.5V 4.35 4.3 4.3 5.5V 5.35 5.3 5.3 3.0V VIN = VIH or VIL │IOUT│≤ 6mA 2.48 2.40 2.20 Minimum High-Level Output Voltage VOH 4.5V VIN = VIH or VIL │IOUT│≤ 12mA 3.70 3.60 3.50 V 1.2V 0.15 0.2 0.2 2.0V 0.15 0.2 0.2 2.7V 0.15 0.2 0.2 3.0V 0.15 0.2 0.2 3.6V 0.15 0.2 0.2 4.5V 0.15 0.2 0.2 5.5V VIN = VIL or VIL │IOUT│≤ 100µA 0.15 0.2 0.2 V 3.0V VIN = VIL or VIL │IOUT│≤ 6mA 0.33 0.40 0.50 Maximum Low-Level Output Voltage VOL 4.5V VIN = VIL or VIL │IOUT│≤ 12mA 0.40 0.55 0.65 V Maximum Input Leakage Current IIN 5.5V VIN = VCC or GND ±0.1 ±1.0 ±1.0 µA Maximum Quiescent Supply Leakage Current ICC 6.0V VIN = VCC or GND IOUT = 0µA 4 20 40 µA Page 4 of 6 www.siliconsupplies.com PART OBSOLETE - DISCONTINUED
Low Voltage CMOS Logic – 54LVU04 Rev 1.0 27/07/19 AC Electrical Characteristics5 LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE4 UNITS 1.2V 70 80 100 2.0V 22 26 31 2.7V 5. Not production tested in die form, characterized by chip design and tested in package. 6. Used to determine the no-load dynamic power consumption: PD = CPD VCC f + ICC VCC 16 19 23 3.0V 13 15 18 Maximum Propagation Delay, Input A or B to Output Y (Figure 1,2) tPLH, tPHL 4.5V CL = 50pF, Input tr = tf = 2.5ns RL = 1kΩ ns 11 13 16 Maximum Input Capacitance CIN 5.5V - 7 7 7 pF TYPICAL Power Dissipation TJ = 25°C, pF Capacitance, Per Inverter6 CPD 5.5V VIN = GND or
36 VCC
Figure 1 – Propagation Delay & Output Transition Time Page 5 of 6 www.siliconsupplies.com PART OBSOLETE - DISCONTINUED
www.siliconsupplies.com Low Voltage CMOS Logic – 54LVU04 Test Circuit DISCLAIMER: The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Silicon Supplies Ltd hereby disclaims any and all warranties and liabilities of any kind. LIFE SUPPORT POLICY: Silicon Supplies Ltd components may be used in life support devices or systems only with the express written approval of Silicon Supplies Ltd, if a failure of such components can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. DUT CL* OUTPUT TEST POINT * Includes all probe and jig capacitance Figure 2 PART OBSOLETE - DISCONTINUED