54LVC1G04 SS | Alldatasheet
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Technical content
Low Voltage CMOS Logic – 54LVC1G04 Single Inverter Gate in bare die form Rev 1.0 29/06/19 /g3 Inputs directly interface TTL Inputs accept up to 5.5V enabling level translation down to VCC Wide Supply Voltage: V CC 1.65V - 5.5V Output Drive capability: ±24mA, V CC = 3V Low Quiescent C urrent: 10µA max High speed: t pd 5.5ns max, VCC = 3V Full Military Temperature Range Tiny die size. Features:
Ordering Information
The following part suffixes apply: No suffix - MIL-STD-883 /2010B Visual Inspection
Description
The 54LVC1G04 single inverter gate performs the Boolean function Y = Ā. The inverter can be driven by either 3.3V or 5V inputs enabling use of this device in a mixed 3.3V and 5V environment. The 54LVC1G04 operates over a 1.65V to 5.5V supply range with low power consumption and is fully specified for partial power-down applications using I OFF. The IOFF circuitry disables the output, preventing damaging backflow current through the device when it is powered down. The device suits level translation and interfacing TTL to CMOS logic applications at low power. Die Dimensions in µm (mils) “ H” - MIL-STD-883 /2010B Visual Inspection + MIL-PRF-38534 Class H LAT “ K” - MIL-STD-883 /2010A Visual Inspection (Space) + MIL-PRF-38534 Class K LAT LAT = Lot Acceptance Test. For further information on LAT process flows see below. www.siliconsupplies.com\\quality\\bare-die-lot-qualification Supply Formats: Mechanical Specification Default – Die in Waffle Pack (400 per tray capacity) Sawn Wafer on Tape – On request 420 (17) 380 (15) Die Size (Unsawn) 420 x 380 17 x 15 µm mils Minimum Bond Pad Size 76 x 76 2.99 x 2.99 µm mils Die Thickness 280 (±20) 11.02 (±0.79) µm mils Top Metal Composition Al-Si-Cu 3 µm Back Metal Composition N/A – Bare Si Unsawn Wafer – On request Die Thickness <> 280µm(11 Mils) – On request Assembled into Ceramic Package – On request Page 1 of 6 www.siliconsupplies.com
www.siliconsupplies.com Low Voltage CMOS Logic – 54LVC1G04 Rev 1.0 29/06/19 Logic Diagram Function Table INPUT A OUTPUT Y H L L H H = High level (steady state) L = Low level (steady state) Expanded Logic Diagram Pad Layout and Functions COORDINATES (µm) PAD FUNCTION X Y 1 GND -70.4 95.2 2 A -65.9 -95.2 3 V CC 62.6 -95.2 4 Y 39.6 95.2 CONNECT CHIP BACK TO VCC OR FLOAT 420µm (16.53 mils) 380µm (14.96 mils) 1 4 2 3 0,0 DIE ID
www.siliconsupplies.com Absolute Maximum Ratings2 PARAMETER SYMBOL VALUE UNIT DC Supply Voltage (Referenced to GND) VCC -0.5 to +6.5 V DC Input Voltage (Referenced to GND) VIN -0.5 to +6.5 V DC Output Voltage – Active Mode -0.5 to VCC +0.5 V DC Output Voltage – Power-Down Mode VCC = 0V VOUT -0.5 to +6.5 V DC Input Clamp Current, VIN < 0 IIK -50 mA DC Output Clamp Current, VOUT < 0 IOK -50 mA DC Output Current IOUT ±50 mA DC VCC or GND Current ICC ±100 mA Power Dissipation in Still Air3 P D 250 mW Storage Temperature Range TSTG -65 to 150 °C Low Voltage CMOS Logic – 54LVC1G04 Rev 1.0 29/06/19 2. Operation above the absolute maximum rating may cause device failure. Operation at the absolute maximum ratings, for extended periods, may reduce device reliability. 3. Measured in plastic TSSOP package, results in die form are dependent on die attach and assembly method. Recommended Operating Conditions4 (Voltages referenced to GND) PARAMETER SYMBOL MIN MAX UNITS DC Supply Voltage VCC 1.65 5.5 V DC Supply Voltage – Data retention only VCC 1.5 - V DC Input Voltage VIN 0 5.5 V DC Output Voltage VOUT 0 V CC V VCC = 1.65V - -4 VCC = 2.3V - -8 VCC = 2.7V - -12 VCC = 3V - -24 High-Level Output Current VCC = 4.5V IOH - -32 mA VCC = 1.65V - 4 VCC = 2.3V - 8 VCC = 2.7V - 12 VCC = 3V - 24 Low-Level Output Current VCC = 4.5V IOL - 32 mA Operating Temperature Range TJ -55 +125 °C VCC = 1.65V - 2.7V 0 20 ns/V Input Transition Rise & Fall Rate VCC = 2.7V - 5.5V Δt / ΔV 0 10 ns/V 4. This device contains protection circuitry to guard against dama ge due to high static voltages or electric fields. However, pr ecautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance ci rcuit. For proper operation, VIN and V OUT should be constrained to the range GND ≤ (V IN or VOUT) ≤ VCC. Unused inputs must always be tied to an appropriate logic vo ltage level (e.g., either GND or V CC). Unused outputs must be left open.
www.siliconsupplies.com Low Voltage CMOS Logic – 54LVC1G04 Rev 1.0 29/06/19 LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE5 UNITS Minimum High-Level Input Voltage VIH V Maximum Low-Level Input Voltage VIL V 1.65 - 5.5V VIN = VIH or VIL, IOUT = -100µA VCC -0.1 VCC -0.1 VCC -0.1 1.65V VIN = VIH or VIL, IOUT = -4mA 1.2 1.2 0.95 2.3V VIN = VIH or VIL, IOUT = -8mA 1.9 1.9 1.7 V 2.7V VIN = VIH or VIL, IOUT = -12mA 2.2 2.2 1.9 3.0V VIN = VIH or VIL, IOUT = -24mA 2.3 2.3 2.0 Minimum High-Level Output Voltage VOH 4.5V VIN = VIH or VIL, IOUT = -32mA 3.8 3.8 3.4 V 1.65 - 5.5V VIN = VIH or VIL, IOUT = 100µA 0.1 0.1 0.1 1.65V VIN = VIH or VIL, IOUT = 4mA 0.45 0.45 0.70 2.3V VIN = VIH or VIL, IOUT = 8mA 0.3 0.3 0.45 V 2.7V VIN = VIH or VIL, IOUT = 12mA 0.4 0.4 0.60 3.0V VIN = VIH or VIL ,IOUT = 24mA 0.55 0.55 0.80 Maximum Low-Level Output Voltage VOL 4.5V VIN = VIH or VIL, IOUT = 32mA 0.55 0.55 0.80 V Input Leakage Current IIN 0V - 5.5V VIN = 5.5V or GND ±1 ±1 ±5 µA Power-Off Leakage Current IOFF 0V VIN or VOUT
www.siliconsupplies.com Low Voltage CMOS Logic – 54LVC1G04 Rev 1.0 29/06/19 LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE5 UNITS 1.65 - 1.95V CL = 30pF, Input tr = tf ≤ 2ns, RL = 1kΩ, VIN = VCC 7.5 7.5 9.5 2.3 - 2.7V CL = 30pF, Input tr = tf ≤ 2ns, RL = 500Ω, VIN = VCC 5 5 6.5 2.7V CL = 50pF, Input tr = tf ≤ 2.5ns, RL = 500Ω, VIN = 2.7V 5.2 5.2 7.0 3.0 - 3.6V CL = 50pF, Input tr = tf ≤ 2.5ns, RL = 500Ω, VIN = 2.7V 4.2 4.2 5.5 Propagation Delay Input A to Output Y (Figure 1,2) tPD 4.5 - 5.5V CL = 50pF, Input tr = tf ≤ 2.5ns, RL = 500Ω, VIN = VCC 3.7 3.7 5.0 ns TYPICAL Input Capacitance CIN 3.3V VIN = GND to VCC, TJ = 25°C 5 pF TYPICAL Power Dissipation Capacitance7 CPD 3.3V VIN = GND to VCC, TJ = 25°C 14 pF 6. Not production tested in die form, characterized by chip design and tested in package. 7. Used to determine the no-load dynamic power consumption: PD = CPD x VCC x fi x N + Ʃ(CL x VCC x fo) in microwatts. LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE5 UNITS Supply Current ICC 1.65 -5.5V VIN = 5.5V or GND, IOUT = 0A 4 4 10 µA Additional Supply Current ΔICC 2.3 - 5.5V VIN = VCC - 0.6V, IOUT =0A, Per pad 500 500 500 µA