54HCT86 SS | Alldatasheet
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Technical content
High Speed CMOS TTL Input – 54HCT86 Quadruple 2-Input Exclusive OR Gate IC in bare die form Output Drive Capability: 10 LSTTL Loads Rev 1.0 09/01/19 Low Input Current: 1µA Outputs directly inter face CMOS, NMOS and TTL Operating Voltage Range: 4.5V to 5.5V TTL / CMOS compatible Input Levels Function compatible with 54LS86 Full Military Temperature Range. Features:
Ordering Information
The 54HCT86 Hex Inverter is fabricated using a 2.5µm 5V CMOS process with the same high speed performance of LSTTL combined with CMOS low power consumption. The device contains four independent gates and performs the Boolean function Y = A ⊕ B = AB + AB in positive logic. The device is characterized over the full Military Temperature Range. All inputs are protected against ESD and excess voltage transients. Device inputs directly accept LSTTL or CMOS.
Description
Die Dimensions in µm (mils) The following part suffixes apply: 1600 (63) 1250 (49) No suffix - MIL-STD-883 /2010B Visual Inspection “ H” - MIL-STD-883 /2010B Visual Inspection + MIL-PRF-38534 Class H LAT “ K” - MIL-STD-883 /2010A Visual Inspection (Space) + MIL-PRF-38534 Class K LAT LAT = Lot Acceptance Test. For further information on LAT process flows see below. www.siliconsupplies.com\\quality\\bare-die-lot-qualification 1600 x 1250 63 x 49 µm Die Size (Unsawn) mils Minimum Bond Pad Size 120 x 120 4.72 x 4.72 µm mils 350 (±20) Die Thickness 13.78 (±0.79) µm mils Top Metal Composition Al 1%Si 1.1µm Back Metal Composition N/A – Bare Si Supply Formats: Mechanical Specification Default – Die in Waffle Pack (400 per tray capacity) Sawn Wafer on Tape – On request Unsawn Wafer – On request Die Thickness <> 350µm(14 Mils) – On request Assembled into Ceramic Package – On request Page 1 of 5 www.siliconsupplies.com A ll data sheet.com
d High Speed CMOS TTL Input – 54HCT86 Rev 1.0 09/01/19 COORDINATES (mm) PAD FUNCTION X Y 1 A1 0.125 0.500 2 B1 0.125 0.125 3 Y1 0.305 0.130 4 A2 0.635 0.125 5 B2 0.995 0.125 6 Y2 1.355 0.125 7 GND 1.355 0.435 8 Y3 1.355 0.610 9 A3 1.355 1.000 10 B3 0.995 1.000 11 Y4 0.745 1.000 12 A4 0.485 1.000 13 B4 0.125 1.000 14 VCC 0.125 0.710 CONNECT CHIP BACK TO VCC OR FLOAT Pad Layout and Functions 1600µm (62.99 mils) 1250µm (49.21 mils) 3 4 5 6 DIE ID 12 11 10 9 0,0 Logic Diagram Function Table INPUTS OUTPUT A B Y L L H H L H L H L H H L Y = A ⊕ B = AB + AB H = High level (steady state) L = Low level (steady state) Page 2 of 5 www.siliconsupplies.com A ll data sheet.com
www.siliconsupplies.com High Speed CMOS TTL Input – 54HCT86 Rev 1.0 09/01/19 PARAMETER SYMBOL MIN MAX UNITS Supply Voltage VCC 4.5 5.5 V DC Input or Output Voltage VIN ,VOUT 0 VCC V Operating Temperature Range TJ -55 +125 °C Input Rise or Fall Times tr, tf - 500 ns Recommended Operating Conditions3 (Voltages referenced to GND) Absolute Maximum Ratings1 PARAMETER SYMBOL VALUE UNIT DC Supply Voltage (Referenced to GND) VCC -0.5 to +7.0 V DC Input Voltage (Referenced to GND) VIN -0.5 to VCC +0.5 V DC Output Voltage (Referenced to GND) VOUT -0.5 to VCC +0.5 V DC Input Current IIN ±20 mA DC Output Current, per pad IOUT ±25 mA DC Supply Current, VCC or GND, per pad ICC ±50 mA Power Dissipation in Still Air2 P D 750 mW Storage Temperature Range TSTG -65 to 150 °C 3. This device contains protection circuitry to guard against dama ge due to high static voltages or electric fields. However, pr ecautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance ci rcuit. For proper operation, VIN and V OUT should be constrained to the range GND ≤ (V IN or VOUT) ≤ VCC. Unused inputs must always be tied to an appropriate logic vo ltage level (e.g., either GND or V CC). Unused outputs must be left open. 1. Operation above the absolute maximum rating may cause device failure. Operation at the absolute maximum ratings, for extended periods, may reduce device reliability. 2. Measured in plastic DIP package, results in die form are dependent on die attach and assembly method. LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE4 UNITS 4.5V 2.0 2.0 2.0 Minimum High-Level Input Voltage VIH 5.5V VOUT = 0.1V or VCC-1 │IOUT│≤ 20µA 2.0 2.0 2.0 V 4.5V 0.8 0.8 0.8 Maximum Low-Level Input Voltage VIL 5.5V VOUT = 0.1V or VCC-1 │IOUT│≤ 20µA 0.8 0.8 0.8 V 4.5V 4.4 4.4 4.4 5.5V VIN = VIL or VIH │IOUT│≤ 20µA 5.4 5.4 5.4 Minimum High-Level Output Voltage VOH 4.5V VIN = VIL or VIH │IOUT│≤ 4.0mA 3.98 3.84 3.70 V 4.5V 0.1 0.1 0.1 5.5V VIN = VIH or VIL │IOUT│≤ 20µA 0.1 0.1 0.1 Maximum Low-Level Output Voltage VOL 4.5V VIN = VIH or VIL │IOUT│≤ 4.0mA 0.26 0.33 0.40 V A ll data sheet.com
High Speed CMOS TTL Input – 54HCT86 Rev 1.0 09/01/19 LIMITS PARAMETER SYMBOL VCC CONDITIONS UNITS FULL RANGE4 25°C 85°C Maximum Input Leakage Current IIN 5.5V VIN = VCC or GND ±0.1 ±1.0 ±1.0 µA Maximum Quiescent Supply Leakage Current3 ICC 5.5V VIN = VCC or GND IOUT = 0µA 2 20 40 µA ≥ -55°C 25°C to 125°C Additional Quiescent Supply Current5 ΔICC 5.5V VIN = 2.4V, Any One Input. VIN = VCC or GND, Other Inputs IOUT = 0µA 2.9 2.4 mA 5. Total Supply Current = ICC + ΣΔICC LIMITS PARAMETER SYMBOL VCC CONDITIONS FULL RANGE4 25°C 85°C UNITS Maximum Propagation Delay, Input A to Input Y (Figure 1,2) ±10% CL = 50pF, tPLH tr = tf = 6ns 24 30 36 Maximum Propagation Delay, Input A to Input Y (Figure 1,2) tPHL 5V ±10% CL = 50pF, tr = tf = 6ns 24 30 36 ns Maximum Output Rise and Fall Time (Figure 1,2) tTLH, tTHL 5V ±10% CL = 50pF, tr = tf = 6ns 15 19 22 ns Maximum Input Capacitance CIN - - 10 10 10 pF TYPICAL Power Dissipation Capacitance TJ = 25°C, Per Gate7 CPD - pF VCC =5.0V 36 6. Not production tested in die form, characterized by chip design and tested in package. 7. Used to determine the no-load dynamic power consumption: PD = CPD VCC f + ICC VCC. Page 4 of 5 www.siliconsupplies.com A ll data sheet.com
High Speed CMOS TTL Input – 54HCT86 Rev 1.0 09/01/19 Page 5 of 5 www.siliconsupplies.com DISCLAIMER: The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Silicon Supplies Ltd hereby disclaims any and all warranties and liabilities of any kind. LIFE SUPPORT POLICY: Silicon Supplies Ltd components may be used in life support devices or systems only with the express written approval of Silicon Supplies Ltd, if a failure of such components can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Switching Waveform DUT CL* OUTPUT TEST POINT Test Circuit * Includes all probe and jig capacitance Figure 1 – Propagation Delay & Output Transition Time Figure 2 A ll data sheet.com