54HCT373 SS | Alldatasheet
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Technical content
High Speed CMOS TTL Input – 54HCT373 8-bit transparent D-Type Latch with 3-State Outputs in bare die form Rev 1.0 07/02/19 Output Drive Capability: 15 LSTTL Loads Low Input Current: 1µA TTL / CMOS compatible Input Levels Features: Outputs directly inter face CMOS, NMOS and TTL Operating Voltage Range: 4.5V to 5.5V Function compatible with 54LS373 Full Military Temperature Range.
Ordering Information
The following part suffixes apply: No suffix - MIL-STD-883 /2010B Visual Inspection “ H” - MIL-STD-883 /2010B Visual Inspection + MIL-PRF-38534 Class H LAT “ K” - MIL-STD-883 /2010A Visual Inspection (Space) + MIL-PRF-38534 Class K LAT LAT = Lot Acceptance Test. For further information on LAT process flows see below. www.siliconsupplies.com\\quality\\bare-die-lot-qualification Supply Formats: 1460 x 1550 Die Size (Unsawn) 57 x 61 µm mils 108 x 108 Minimum Bond Pad Size 4.25 x 4.25 µm mils 350 (±20) Die Thickness 13.78 (±0.79) µm mils Mechanical Specification Default – Die in Waffle Pack (100 per tray capacity) Sawn Wafer on Tape – On request Unsawn Wafer – On request Die Thickness <> 350µm(14 Mils) – On request Top Metal Composition Al 1%Si 1.1µm Back Metal Composition N/A – Bare Si Assembled into Ceramic Package – On request The 54HCT373 consists of eight D-type transparent latches fabricated using a 2.5µm 5V CMOS process to combine high speed performance LSTTL performance with CMOS low power consumption. Each latch is equipped with separate D-Type inputs and 3-State outputs for bus oriented applications. Data output changes asynchronously and data may be latched even when the outputs are not enabled. Device inputs directly accept both standard CMOS and LSTTL outputs. All inputs are equipped with protection circuits against static discharge and transient excess voltage.
Description
Die Dimensions in µm (mils) 1460 (57) 1550 (61) Page 1 of 7 www.siliconsupplies.com A ll data sheet.com
www.siliconsupplies.com d High Speed CMOS TTL Input – 54HCT373 Rev 1.0 07/02/19Pad Layout and Functions 1460µm (57.48 mils) 1550µm (61.02 mils) 0,0 Logic Diagram DIE ID 9 131415 16 17 18 3 4 5 6 7 7 COORDINATES (mm) PAD FUNCTION X Y 1 OE 0.1205 0.597 2 1Q 0.1205 0.3595 3 1D 0.1205 0.122 4 2D 0.413 0.1225 5 2Q 0.582 0.1225 6 3Q 0.7415 0.1225 7 3D 0.913 0.1225 8 4D 1.234 0.116 9 4Q 1.232 0.29 10 GND 1.232 0.51 11 LE 1.232 0.842 12 5Q 1.232 1.0795 13 5D 1.232 1.317 14 6D 0.9395 1.3165 15 6Q 0.7705 1.3165 16 7Q 0.611 1.3165 17 7D 0.4395 1.3165 18 8D 0.1185 1.323 19 8Q 0.1205 1.149 20 VCC 0.1205 0.929 CONNECT CHIP BACK TO VCC OR FLOAT INPUTS OUTPUT OE LE D Q L L L H H H L X H L X X H L No Change Z H = High level (steady state) L = Low level (steady state) Z = High Impedance X = Don’t care Truth Table Pad 10 = GND, Pad 20 = VCC A ll data sheet.com
www.siliconsupplies.com High Speed CMOS TTL Input – 54HCT373 Rev 1.0 07/02/19 PARAMETER SYMBOL MIN MAX UNITS Supply Voltage VCC 4.5 5.5 V DC Input or Output Voltage VIN ,VOUT 0 VCC V Operating Temperature Range TJ -55 +125 °C Input Rise or Fall Times tr, tf - 500 ns Recommended Operating Conditions3 (Voltages referenced to GND) Absolute Maximum Ratings1 PARAMETER SYMBOL VALUE UNIT DC Supply Voltage (Referenced to GND) VCC -0.5 to +7.0 V DC Input Voltage (Referenced to GND) VIN -0.5 to VCC +0.5 V DC Output Voltage (Referenced to GND) VOUT -0.5 to VCC +0.5 V DC Input Current, per pad IIN ±20 mA DC Output Current, per pad IOUT ±35 mA DC Supply Current, VCC or GND ICC ±75 mA Power Dissipation in Still Air2 P D 750 mW Storage Temperature Range TSTG -65 to 150 °C 3. This device contains protection circuitry to guard against dama ge due to high static voltages or electric fields. However, pr ecautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance ci rcuit. For proper operation, VIN and V OUT should be constrained to the range GND ≤ (V IN or VOUT) ≤ VCC. Unused inputs must always be tied to an appropriate logic vo ltage level (e.g., either GND or V CC). Unused outputs must be left open. 1. Operation above the absolute maximum rating may cause device failure. Operation at the absolute maximum ratings, for extended periods, may reduce device reliability. 2. Measured in plastic DIP package, results in die form are dependent on die attach and assembly method. LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE4 UNITS 4.5V 2.0 2.0 2.0 Minimum High-Level Input Voltage VIH 5.5V VOUT = 0.1V or VCC -0.1V │IOUT│≤ 20µA 2.0 2.0 2.0 V 4.5V 0.8 0.8 0.8 Maximum Low-Level Input Voltage VIL 5.5V VOUT = 0.1V or VCC -0.1V │IOUT│≤ 20µA 0.8 0.8 0.8 V 4.5V 4.4 4.4 4.4 5.5V VIN = VIH or VIL │IOUT│≤ 20µA 5.4 5.4 5.4 Minimum High-Level Output Voltage VOH 4.5V VIN = VIH or VIL │IOUT│≤ 6.0mA 3.98 3.84 3.70 V 4.5V 0.1 0.1 0.1 5.5V VIN = VIH or VIL │IOUT│≤ 20µA 0.1 0.1 0.1 Maximum Low-Level Output Voltage VOL 4.5V VIN = VIH or VIL │IOUT│≤ 6.0mA 0.26 0.33 0.40 V A ll data sheet.com
www.siliconsupplies.com High Speed CMOS TTL Input – 54HCT373 Rev 1.0 07/02/19 LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE4 UNITS Maximum Input Leakage Current IIN 5.5V VIN = VCC or GND ±0.1 ±1.0 ±1.0 µA Maximum 3-State Leakage Current IOZ 5.5V High Z Output, VIN = VIL or VIH, VOUT=VCC or GND ±0.5 ±5 ±10 µA Maximum Quiescent Supply Leakage Current5 ICC 5.5V VIN = VCC or GND │IOUT│≤ 0µA 4 40 160 µA ≥ -55°C 25°C to 125°C Additional Quiescent Supply Current5 ΔICC 5.5V VIN = 2.4V, Any One Input. VIN = VCC or GND, Other Inputs IOUT = 0µA 2.9 2.4 mA 4. -55˚C ≤ TJ ≤ +125˚C 5. Total Supply Current = ICC + ΣΔICC. LIMITS PARAMETER SYMBOL V CC CONDITIONS 25°C 85°C FULL RANGE 4 UNITS Maximum Propagation Delay, D to Q (Figure 1,5) tPLH, tPHL 5V ±10% CL = 50pF, Input tr = tf = 6ns 28 35 42 ns Maximum Propagation Delay, LE to Q (Figure 2,5) tPLH, tPHL 5V ±10% CL = 50pF, Input tr = tf = 6ns 32 40 48 ns Maximum Propagation Delay, OE to Q (Figure 3,6) tPLZ, tPHZ 5V ±10% CL = 50pF, Input tr = tf = 6ns 30 38 45 ns Maximum Propagation Delay, OE to Q (Figure 3,6) tPZL, tPZH 5V ±10% CL = 50pF, Input tr = tf = 6ns 35 44 53 ns Maximum Output Transition Time, Any Output (Figure 1,5) tTLH, tTHL 5V ±10% CL = 50pF, Input tr = tf = 6ns 12 15 18 pF 6. Not production tested in die form, characterized by chip design and tested in package. A ll data sheet.com
www.siliconsupplies.com High Speed CMOS TTL Input – 54HCT373 Rev 1.0 07/02/19 LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE4 UNITS Maximum Input Capacitance CIN 5V ±10% CL = 50pF, Input tr = tf = 6ns 10 10 10 pF Maximum 3-State Output Capacitance COUT 5V ±10% CL = 50pF, Input tr = tf = 6ns 15 15 15 pF TYPICAL Power Dissipation Capacitance per Latch7 CPD - TJ = 25°C, VCC =5.0V 65 pF 6. Not production tested in die form, characterized by chip design and tested in package. 7. Used to determine the no-load dynamic power consumption: PD = CPD VCC f + ICC VCC. Timing Requirements6 LIMITS PARAMETER SYMBOL V CC CONDITIONS 25°C 85°C FULL RANGE 4 UNITS Minimum Setup Time, D to LE (Figure 4) tSU 5V ±10% Input tr = tf =6ns 10 13 15 ns Minimum Hold Time, LE to D (Figure 4) th 5V ±10% Input tr = tf =6ns 10 13 15 ns Minimum Pulse Width, LE (Figure 4) tw 5V ±10% Input tr = tf =6ns 12 15 18 ns Maximum Input Rise & Fall Times (Figure 4) tr, tf 5V ±10% Input tr = tf =6ns 500 500 500 ns A ll data sheet.com