74HCT00_V01 SS | Alldatasheet
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High Speed CMOS TTL Input – 74HCT00 Quad 2-Input NAND Gates with LSTTL compatible inputs in bare die form Rev 1.0 07/02/19 /g3 74HCT00 provides x4 independent 2-input NAND gates performing the Boolean function Y = A • B or Y = A + B. The device is fabricated using a 2.5µm 5V CMOS process combining high speed LSTTL performance with CMOS low power. Internal circuitry comprises of 3 stages and includes buffered outputs for high noise immunity and stability. Device inputs directly accept both standard CMOS and LSTTL outputs. All inputs are equipped with protection circuits against static discharge and transient excess voltage. Description Features: Output Drive Capability: 10 LSTTL Loads Low Input Current: 1µA Outputs directly inter face CMOS, NMOS and TTL Operating Voltage Range: 4.5V to 5.5V TTL / CMOS compatible Input Levels Function compatible with 74LS00. Ordering Information Die Dimensions in µm (mils) The following part suffixes apply: 1250 (49) No suffix - MIL-STD-883 /2010B Visual Inspection 1350 (53) For High Reliability versions of this product please see 54HCT00 Supply Formats: Mechanical Specification Default – Die in Waffle Pack (400 per tray capacity) 1250 x 1350 µm Die Size (Unsawn) 49 x 53 mils Sawn Wafer on Tape – On request 96 x 96 µm Minimum Bond Pad Size 3.78 x 3.78 mils Unsawn Wafer – On request 350 (±20) µm Die Thickness 13.78 (±0.79) mils Die Thickness <> 350µm(14 Mils) – On request Top Metal Composition Al 1%Si 1.1µm Assembled into Ceramic Package – On request Back Metal Composition N/A – Bare Si Page 1 of 5 www.siliconsupplies.com
www.siliconsupplies.com d High Speed CMOS TTL Input – 74HCT00 Rev 1.0 07/02/19 COORDINATES (mm) PAD FUNCTION X Y 1 1A 0.104 0.354 2 1B 0.232 0.115 3 1Y 0.450 0.115 4 2A 0.658 0.115 5 2B 0.924 0.115 6 2Y 1.051 0.424 7 GND 1.051 0.595 8 3Y 1.051 0.830 9 3A 0.923 1.140 10 3B 0.658 1.140 11 4Y 0.450 1.140 12 4A 0.232 1.140 13 4B 0.104 0.900 14 VCC 0.104 0.637 CONNECT CHIP BACK TO VCC OR FLOAT Pad Layout and Functions Logic Diagram Function Table INPUTS OUTPUT A B Y L L H H L H L H H H H L H = High level (steady state) L = Low level (steady state) Pad 14 = V CC Pad 7 = GND 1250µm (49.21 mils) 1350µm (53.14 mils) 0,0 2 3 4 5 9 10 11 12 DIE ID
www.siliconsupplies.com High Speed CMOS TTL Input – 74HCT00 Rev 1.0 07/02/19 PARAMETER SYMBOL MIN MAX UNITS Supply Voltage VCC 4.5 5.5 V DC Input or Output Voltage VIN ,VOUT 0 VCC V Operating Temperature Range TJ 0 +85 °C Input Rise or Fall Times tr, tf - 500 ns Recommended Operating Conditions3 (Voltages referenced to GND) Absolute Maximum Ratings1 PARAMETER SYMBOL VALUE UNIT DC Supply Voltage (Referenced to GND) VCC -0.5 to +7.0 V DC Input Voltage (Referenced to GND) VIN -0.5 to VCC +0.5 V DC Output Voltage (Referenced to GND) VOUT -0.5 to VCC +0.5 V DC Input Current IIN ±20 mA DC Output Current, per pad IOUT ±25 mA DC Supply Current, VCC or GND, per pad ICC ±50 mA Power Dissipation in Still Air2 P D 750 mW Storage Temperature Range TSTG -65 to 150 °C 3. This device contains protection circuitry to guard against dama ge due to high static voltages or electric fields. However, pr ecautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance ci rcuit. For proper operation, VIN and V OUT should be constrained to the range GND ≤ (V IN or VOUT) ≤ VCC. Unused inputs must always be tied to an appropriate logic vo ltage level (e.g., either GND or V CC). Unused outputs must be left open. 1. Operation above the absolute maximum rating may cause device failure. Operation at the absolute maximum ratings, for extended periods, may reduce device reliability. 2. Measured in plastic DIP package, results in die form are dependent on die attach and assembly method. LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE4 UNITS 4.5V 2.0 2.0 2.0 Minimum High-Level Input Voltage VIH 5.5V VOUT = 0.1V or VCC -0.1V │IOUT│≤ 20µA 2.0 2.0 2.0 V 4.5V 0.8 0.8 0.8 Maximum Low-Level Input Voltage VIL 5.5V VOUT = 0.1V or VCC -0.1V │IOUT│≤ 20µA 0.8 0.8 0.8 V 4.5V 4.4 4.4 4.4 5.5V VIN = VIH or VIL │IOUT│≤ 20µA 5.4 5.4 5.4 Minimum High-Level Output Voltage VOH 4.5V VIN = VIH or VIL │IOUT│≤ 4.0mA 3.98 3.84 3.84 V 4.5V 0.1 0.1 0.1 5.5V VIN = VIH or VIL │IOUT│≤ 20µA 0.1 0.1 0.1 Maximum Low-Level Output Voltage VOL 4.5V VIN = VIH or VIL │IOUT│≤ 4.0mA 0.26 0.33 0.33 V
High Speed CMOS TTL Input – 74HCT00 Rev 1.0 07/02/19 LIMITS PARAMETER SYMBOL VCC CONDITIONS FULL RANGE4 25°C 85°C UNITS Maximum Input Leakage Current IIN 5.5V VIN = VCC or GND ±0.1 ±1.0 ±1.0 µA Maximum Quiescent Supply Leakage Current5 ICC 5.5V VIN = VCC or GND │IOUT│≤ 0µA 1 10 10 µA ≥ 0°C 25°C to 85°C Additional Quiescent Supply Current5 ΔICC 5.5V VIN = 2.4V, Any One Input. VIN = VCC or GND, Other Inputs IOUT = 0µA 2.9 2.4 mA LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE4 UNITS Maximum Propagation Delay, Input A to Input Y (Figure 1,2) tPLH, tPHL 5V ±10% CL = 50pF, tr = tf = 6ns 19 24 24 ns Maximum Output Rise and Fall Time (Figure 1,2) tTLH, tTHL 5V ±10% CL = 50pF, tr = tf = 6ns 15 19 19 ns Maximum Input Capacitance CIN - - 10 10 10 pF TYPICAL Power Dissipation Capacitance Per Gate7 CPD - TJ = 25°C, VCC =5.0V 15 pF 6. Not production tested in die form, characterized by chip design and tested in package. 4. 0˚C ≤ TJ ≤ +85˚C 5. Total Supply Current = ICC + ΣΔICC. 7. Used to determine the no-load dynamic power consumption: PD = CPD VCC f + ICC VCC. Page 4 of 5 www.siliconsupplies.com
High Speed CMOS TTL Input – 74HCT00 Rev 1.0 07/02/19 Page 5 of 5 www.siliconsupplies.com Switching Waveform DISCLAIMER: The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Silicon Supplies Ltd hereby disclaims any and all warranties and liabilities of any kind. LIFE SUPPORT POLICY: Silicon Supplies Ltd components may be used in life support devices or systems only with the express written approval of Silicon Supplies Ltd, if a failure of such components can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. DUT CL* OUTPUT TEST POINT Test Circuit * Includes all probe and jig capacitance Figure 1 – Propagation Delay & Output Transition Time Figure 2