74HC4060 SS | Alldatasheet
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Technical content
High Speed CMOS Logic – 74HC4060 14-Stage Binary Ripple Counter / Divider with Oscillator in bare die form Rev 1.0 26/11/17 Output Drive Capability: 10 LSTTL Loads Low Input Current: 1µA Outputs directly inter face CMOS, NMOS and TTL Operating Voltage Range: 2V to 6V CMOS High Noise Immunity Function compatible with CD4060B. Features:
Ordering Information
The following part suffixes apply: The 74HC4060 is produced on a 2.5µm 5V CMOS process with high speed LSTTL performance combined with CMOS low power consumption. The device consists of 14 master– slave flip–flops & an oscillator with frequency controlled either by crystal or by external RC circuit. Each flip–flop output feeds the next where each output frequency is half the preceding one. A high-to-low transition on the clock input increments the counter. The active–high Reset is asynchronous & disables the oscillator for low standby power consumption. Ten kinds of divided output are provided; 4 to 10 & 12 to 14 stage inclusive. Maximum division available at Q12 is 1/16384 of oscillator frequency.
Description
Die Dimensions in µm (mils) 1610 (63) No suffix - MIL-STD-883 /2010B Visual Inspection For High Reliability versions of this product please see 1610 (63) 54HC4060 Supply Formats: Die Size (Unsawn) 1610 x 1610 63 x 63 µm mils Minimum Bond Pad Size 110 x 110 4 x 4 µm mils Die Thickness 350 (±20) 13.78 (±0.79) µm mils Mechanical Specification Default – Die in Waffle Pack (100 per tray capacity) Sawn Wafer on Tape – On request Unsawn Wafer – On request Die Thickness <> 350µm(14 Mils) – On request Top Metal Composition Al 1%Si 1.1µm Back Metal Composition N/A – Bare Si Assembled into Ceramic Package – On request Page 1 of 7 www.siliconsupplies.com A ll data sheet.com
www.siliconsupplies.com d High Speed CMOS Logic – 74HC4060 Rev 1.0 26/11/17 COORDINATES (mm) PAD FUNCTION X Y 1 Q12 0.610 1.350 2 Q13 0.190 1.140 3 Q14 0.190 0.970 4 Q6 0.190 0.790 5 Q5 0.190 0.620 6 Q7 0.190 0.440 7 Q4 0.190 0.270 8 GND 0.590 0.150 9 OSC OUT2 0.950 0.150 10 OSC OUT1 1.270 0.150 11 OSC IN 1.310 0.340 12 MR 1.310 0.650 13 Q9 1.310 0.860 14 Q8 1.310 1.050 15 Q10 1.310 1.220 16 VCC 0.880 1.350 CONNECT CHIP BACK TO VCC OR FLOAT Pad Layout and Functions Logic Diagram 1610µm (63.38 mils) 0,0 Function Table 1610µm (63.38 mils) 109 8 DIE ID Pad 14 = VCC Pad 7 = GND A ll data sheet.com
www.siliconsupplies.com PARAMETER SYMBOL MIN MAX UNITS DC Supply Voltage VCC 24 6 V DC Input or Output Voltage VIN ,VOUT 0 VCC V Operating Temperature Range TJ 0 +85 °C VCC = 2.0V 0 1000 ns VCC = 4.5V 0 500 Input Rise or Fall Times VCC = 6.0V tr, tf 0 400 Recommended Operating Conditions3 (Voltages referenced to GND) Absolute Maximum Ratings1 PARAMETER SYMBOL VALUE UNIT DC Supply Voltage (Referenced to GND) VCC -0.5 to +7.0 V DC Input Voltage (Referenced to GND) VIN -0.5 to VCC +0.5 V DC Output Voltage VOUT -0.5 to VCC +0.5 V DC Input Current, per pad IIN ±20 mA DC Output Current, per pad IOUT ±25 mA DC VCC or GND Current, per pad ICC ±50 mA Power Dissipation in Still Air2 P D 750 mW Storage Temperature Range TSTG -65 to 150 °C High Speed CMOS Logic – 74HC4060 Rev 1.0 26/11/17 1. Operation above the absolute maximum rating may cause device failure. Operation at the absolute maximum ratings, for extended periods, may reduce device reliability. 2. Measured in plastic DIP package, results in die form are dependent on die attach and assembly method. Pad Descriptions INPUTS Osc IN (Pad 11) Negative–edge triggering clock input. A high–to–low transition on this input advances the state of the counter. Osc IN may be driven by an external clock source. CONTROL INPUTS MR (Pad 12) Active–high reset. A high level applied to this input asynchronously resets the counter to its zero state (forcing all Q outputs low) and disables the oscillator. OUTPUTS Q4—Q10, Q12–Q14 (Pads 7, 5, 4, 6, 13, 15, 1, 2, 3) Active–high outputs. Each Qn output divides the Clock input frequency by 2 The user should note the Q1, Q2, Q3 and Q11 are not available as outputs. Osc OUT1, Osc OUT2 (Pads 9, 10) Oscillator outputs. These pads are used in conjunction with Osc IN and the external components to form an oscillator. When Osc IN is being driven with an external clock source, Osc OUT1 and Osc OUT2 must be left open circuited. With the crystal oscillator in RC configuration, Osc OUT2 must be left open circuited. 3. This device contains protection circuitry to guard against dama ge due to high static voltages or electric fields. However, pr ecautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance ci rcuit. For proper operation, VIN and V OUT should be constrained to the range GND ≤ (V IN or VOUT) ≤ VCC. Unused inputs must always be tied to an appropriate logic vo ltage level (e.g., either GND or V CC). Unused outputs must be left open. A ll data sheet.com
www.siliconsupplies.com High Speed CMOS Logic – 74HC4060 Rev 1.0 26/11/17 LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE5 UNITS 2.0V 1.5 1.5 1.5 3.0V 2.1 2.1 2.1 4.5V 3.15 3.15 3.15 Minimum High-Level Input Voltage VIH 6.0V VOUT = 0.1V or VCC -0.1V │IOUT│≤ 20µA 4.2 4.2 4.2 V 2.0V 0.5 0.5 0.5 3.0V 0.9 0.9 0.9 4.5V 1.35 1.35 1.35 Maximum Low-Level Input Voltage VIL 6.0V VOUT = 0.1V or VCC -0.1V │IOUT│≤ 20µA 1.8 1.8 1.8 V 2.0V 1.9 1.9 1.9 4.5V 4.4 4.4 4.4 6.0V VIN = VIH or VIL │IOUT│≤ 20µA 5.9 5.9 5.9 V 3.0V VIN = VIH or VIL │IOUT│≤ 2.4mA 2.48 2.34 2.34 4.5V VIN = VIH or VIL │IOUT│≤ 4.0mA 3.98 3.84 3.84 Minimum High-Level Output Voltage (Q4–Q10, Q12–Q14) VOH 6.0V VIN = VIH or VIL │IOUT│≤ 5.2mA 5.48 5.34 5.34 V 2.0V 0.1 0.1 0.1 4.5V 0.1 0.1 0.1 6.0V VIN = VIH or VIL │IOUT│≤ 20µA 0.1 0.1 0.1 V 3.0V VIN = VIH or VIL │IOUT│≤ 2.4mA 0.26 0.33 0.33 4.5V VIN = VIH or VIL │IOUT│≤ 4.0mA 0.26 0.33 0.33 Maximum Low-Level Output Voltage (Q4–Q10, Q12–Q14) VOL 6.0V VIN = VIH or VIL │IOUT│≤ 5.2mA 0.26 0.33 0.33 V 2.0V 1.9 1.9 1.9 4.5V 4.4 4.4 4.4 6.0V VIN = VCC or GND │IOUT│≤ 20µA 5.9 5.9 5.9 V 3.0V VIN = VCC or GND │IOUT│≤ 0.7mA 2.48 2.34 2.34 4.5V VIN = VCC or GND │IOUT│≤ 1.0mA 3.98 3.84 3.84 Minimum High-Level Output Voltage (OSCOUT1, OSCOUT2) VOH 6.0V VIN = VCC or GND │IOUT│≤ 1.3mA 5.48 5.34 5.34 V A ll data sheet.com
www.siliconsupplies.com High Speed CMOS Logic – 74HC4060 Rev 1.0 26/11/17 LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE5 UNITS 2.0V 6 9 9 3.0V 10 14 14 4.5V 30 28 28 Maximum Clock Frequency (50% Duty Cycle) (Figure 1,4) fmax 6.0V CL = 50pF, tr = tf = 6ns 50 45 45 MHz 2.0V 300 375 375 3.0V 180 200 200 4.5V 60 75 75 Maximum Propagation Delay, OSC IN to Q47 (Figure 1,4) tPLH, tPHL 6.0V CL = 50pF, tr = tf = 6ns 51 64 64 ns 2.0V 500 750 750 3.0V 350 450 450 4.5V 250 275 275 Maximum Propagation Delay, OSC IN to Q147 (Figure 1,4) tPLH, tPHL 6.0V CL = 50pF, tr = tf = 6ns 200 220 220 ns 2.0V 195 245 245 3.0V 75 100 100 4.5V 39 49 49 Maximum Propagation Delay, Reset to any Q (Figure 2,4) tPHL 6.0V CL = 50pF, tr = tf = 6ns 33 42 42 ns LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE5 UNITS 2.0V 0.1 0.1 0.1 4.5V 0.1 0.1 0.1 6.0V VIN = VCC or GND │IOUT│≤ 20µA 0.1 0.1 0.1 V 3.0V VIN = VCC or GND │IOUT│≤ 0.7mA 0.26 0.33 0.33 4.5V VIN = VCC or GND │IOUT│≤ 1.0mA 0.26 0.33 0.33 Maximum Low-Level Output Voltage (OSCOUT1, OSCOUT2) VOL 6.0V VIN = VCC or GND │IOUT│≤ 1.3mA 0.26 0.33 0.33 V Maximum Input Leakage Current IIN 6.0V VIN = VCC or GND ±0.1 ±1.0 ±1.0 µA Maximum Quiescent Supply Current ICC 6.0V VIN = VCC or GND, IOUT = 0µA 4 80 80 µA 6. Not production tested in die form, characterized by chip design and tested in package. 7. For TJ = 25°C and CL = 50 pF, typical propagation delay from Clock to other Q outputs may be calculated with the following equations: A ll data sheet.com
www.siliconsupplies.com High Speed CMOS Logic – 74HC4060 Rev 1.0 26/11/17 8. Used to determine the no-load dynamic power consumption: PD = CPD VCC f + ICC VCC LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE5 UNITS 2.0V 75 95 95 3.0V 60 75 75 4.5V 15 19 19 Maximum Propagation Delay, Qn to Qn+1 (Figure 3,4) tPLH, tPHL 6.0V CL = 50pF, tr = tf = 6ns 13 16 16 ns 2.0V 75 95 95 3.0V 27 32 32 4.5V 15 19 19 Maximum Output Transition Time, any output (Figure 1,4) tTLH, tTHL 6.0V CL = 50pF, tr = tf = 6ns 13 16 16 ns Maximum Input Capacitance CIN - - 10 10 10 pF TYPICAL Power Dissipation Capacitance8 CPD - TA = 25°C, VCC = 5.0V 35 pF Timing Requirements6 LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE5 UNITS 2.0V 100 125 125 3.0V 75 100 100 4.5V 20 25 25 Minimum Recovery Time, Reset Inactive to Clock (Figure 2) trec 6.0V tr = tf = 6ns 17 21 21 ns 2.0V 75 95 95 3.0V 27 32 32 4.5V 15 19 19 Minimum Pulse Width, Clock (Figure 1) tw 6.0V tr = tf = 6ns 13 16 16 ns 2.0V 75 95 95 3.0V 27 32 32 4.5V 15 19 19 Minimum Pulse Width, Reset (Figure 2) tw 6.0V tr = tf = 6ns 13 16 16 ns 2.0V 1000 1000 1000 3.0V 800 800 800 4.5V 500 500 500 Maximum Input Rise and Fall Times (Figure 1) tr, tf 6.0V tr = tf = 6ns 400 400 400 ns A ll data sheet.com