54HC4040

54HC4040 SS | Alldatasheet

Document overview

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Technical content

www.siliconsupplies.com Die Size (Unsawn) 760 x 560 30 x 22 µm mils Minimum Bond Pad Size 70 x 70 2.76 x 2.76 µm mils Die Thickness 280 (±20) 11.02 (±0.79) µm mils Top Metal Composition Al-Si-Cu Back Metal Composition N/A – Bare Si High Speed CMOS Logic – 54HC4040 12-Stage Binary Ripple Counter in bare die form  Output Drive Capability: 10 LSTTL Loads  Low Input Current: 1µA  Outputs directly interface CMOS, NMOS and TTL  Operating Voltage Range: 2V to 6V  CMOS High Noise Immunity  Function compatible with CD4040B  Full Military Temperature Range. Rev 1.0 15 /09 /25 Features: The following part suffixes apply:  No suffix - MIL-STD-883 /2010B Visual Inspection  “ H” - MIL-STD-883 /2010B Visual Inspection + MIL-PRF-38534 Class H LAT  “ K” - MIL-STD-883 /2010A Visual Inspection (Space) + MIL-PRF-38534 Class K LAT LAT = Lot Acceptance Test. For further information on LAT process flows see below. www.siliconsupplies.com\\quality\\bare-die-lot-qualification Supply Formats: Mechanical Specification  Default – Die in Waffle Pack (400 per tray capacit y)  Sawn Wafer on Tape – On request  Unsawn Wafer – On request  Die Thickness <> 280µm(11 Mils) – On request  Assembled into Ceramic Package – On request The 54HC4040 is fabricated using an advanced 5V CMOS process to combine high speed LSTTL performance with CMOS low power. The device is a 12-stage asynchronous binary counter with a clock input, an overriding asynchronous master reset input and twelve parallel outputs (Q1 to Q12). A high-to-low transition on the clock input increments the counter. The active–high reset clears all counter stages and forces all outputs low, independent of clock state. Device inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of V CC .

Description

Die Dimensions in µm (mils) 760 (30) 560 (22) Ordering Guide

www.siliconsupplies.com Rev 1.0 15/09/25 COORDINATES (µm) PAD FUNCTION X Y

1 Q12 -276 -66

2 Q6 -270 -176

3 Q5 -162 -176

4 Q7 -54 -176

5 Q4 54 -176

6 Q3 162 -176

7 Q2 270 -176

8 GND 280 -53

9 Q1 276 55.5

10 CLOCK 270 176

11 RESET 162 176

12 Q9 54 176

13 Q8 -54 176

14 Q10 -162 176

15 Q11 -270 176

16 V CC -276 56.7 CONNECT CHIP BACK TO V CC OR FLOAT Pad Layout and Functions Logic Diagram 560µm (22.05 mils) Function Table 760µm (29.92 mils) 3 4 5 6 7 2 15 14 13 12 11 10 0,0 Pad 16 = V CC Pad 8 = GND High Speed CMOS Logic – 54HC4040

www.siliconsupplies.com PARAMETER SYMBOL MIN MAX UNITS DC Supply Voltage VCC 2 6 V DC Input or Output Voltage VIN ,V OUT 0 V CC V Operating Temperature Range TJ -55 +125 °C VCC = 2.0V 0 1000 VCC = 4.5V 0 500 Input Rise or Fall Times VCC = 6.0V tr, t f 0 400 ns Recommended Operating Conditions 3 (Voltages referenced to GND) Absolute Maximum Ratings 1 PARAMETER SYMBOL VALUE UNIT DC Supply Voltage (Referenced to GND) V CC -0.5 to +7.0 V DC Input Voltage (Referenced to GND) V IN -0.5 to V CC +0.5 V DC Output Voltage VOUT -0.5 to V CC +0.5 V DC Input Current, per pad I IN ±20 mA DC Output Current, per pad I OUT ±25 mA DC V CC or GND Current, per pad I CC ±50 mA Power Dissipation in Still Air 2 P D 750 mW Storage Temperature Range T STG -65 to 150 °C Rev 1.0 15/09/25 1. Operation above the absolute maximum rating may cause device failure. Operation at the absolute maximum ratings, for extended periods, may reduce device reliability. 2. Measured in plastic DIP package, r esults in die form are dependent on die attach and assembly method . Pad Descriptions INPUTS Clock (Pad 10) Negative–edge triggering clock input. A high–to–low transition on this input advances the state of the counter, Reset (Pad 11) Active–high reset. A high level applied to this inp ut asynchronously resets the counter to its zero state (forcing all Q outputs low). OUTPUTS Active–high outputs. Each Qn output divides the Clo ck input frequency by 2 3. This device contains protection circuitry to guard against damage due to high static voltages or electr ic fields. However, precautions must be taken to avoid applications of any voltage higher than max imum rated voltages to this high-impedance circuit. Fo r proper operation, V IN and V OUT should be constrained to the range GND ≤ (V IN or V OUT ) ≤ VCC . Unused inputs must always be tied to an appropria te logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open. High Speed CMOS Logic – 54HC4040

www.siliconsupplies.com Rev 1.0 15/09/25 LIMITS PARAMETER SYMBOL V CC CONDITIONS 25°C 85°C FULL RANGE 4 UNITS 2.0V 5.5 4.3 3.7 4.5V 28 22 19 Maximum Clock Frequency (Figure 1) fmax 6.0V CL = 50pF, tr = t f = 6ns 33 25 22 MHz 2.0V 150 190 225 4.5V 30 38 45 Maximum Propagation Delay, Clock to Output Q1 (Figure 1) tpd 6.0V CL = 50pF, tr = t f = 6ns 26 32 38 ns High Speed CMOS Logic – 54HC4040 LIMITS PARAMETER SYMBOL V CC CONDITIONS 25°C 85°C FULL RANGE 4 UNITS 2.0V 1.5 1.5 1.5 4.5V 3.15 3.15 3.15 Minimum High-Level Input Voltage VIH 6.0V VOUT = 0.1V or VCC -0.1V │IOUT │≤ 20µA 4.2 4.2 4.2 V 2.0V 0.5 0.5 0.5 4.5V 1.35 1.35 1.35 Maximum Low-Level Input Voltage VIL 6.0V VOUT = 0.1V or VCC -0.1V │IOUT │≤ 20µA 1.8 1.8 1.8 V 2.0V 1.9 1.9 1.9 4.5V 4.4 4.4 4.4 6.0V VIN = V IH or V IL │IOUT │≤ 20µA 5.9 5.9 5.9 4.5V VIN = V IH or V IL │IOUT │≤ 4.0mA 3.98 3.84 3.70 Minimum High-Level Output Voltage VOH 6.0V VIN = V IH or V IL │IOUT │≤ 5.2mA 5.48 5.34 5.20 V 2.0V 0.1 0.1 0.1 4.5V 0.1 0.1 0.1 6.0V VIN = V IH or V IL │IOUT │≤ 20µA 0.1 0.1 0.1 4.5V VIN = V IH or V IL │IOUT │≤ 4.0mA 0.26 0.33 0.40 Maximum Low-Level Output Voltage VOL 6.0V VIN = V IH or V IL │IOUT │≤ 5.2mA 0.26 0.33 0.40 V Maximum Input Leakage Current IIN 6.0V VIN = V CC or GND ±0.1 ±1.0 ±1.0 µA Maximum Quiescent Supply Current ICC 6.0V VIN = V CC or GND, IOUT = 0µA 8 80 160 µA

www.siliconsupplies.com x Rev 1.0 15/09/25 LIMITS PARAMETER SYMBOL V CC CONDITIONS 25°C 85°C FULL RANGE 4 UNITS 2.0V 140 175 210 4.5V 28 35 42 Maximum Propagation Delay, Reset to Output Q (Any) (Figure 2) tPHL 6.0V CL = 50pF, tr = t f = 6ns 24 30 36 ns 2.0V 75 95 110 4.5V 15 19 22 Maximum Output Transition Time (Figure 1) tTLH, t THL 6.0V CL = 50pF, tr = t f = 6ns 13 16 19 ns Maximum Input Capacitance CIN - - 10 10 10 pF TYPICAL Power Dissipation Capacitance 6 CPD - TA = 25°C, VCC = 5.0V 88 pF 5. Not production tested in die form, characterized by chip design and tested in package. 6. Used to determine the no-load dynamic power consumption: P D = C PD V CC 2f + I CC V CC Timing Requirements 5 LIMITS PARAMETER SYMBOL V CC CONDITIONS 25°C 85°C FULL RANGE 4 UNITS 2.0V 90 115 135 4.5V 18 23 27 Minimum Pulse Width, Clock High or Low (Figure 1) tw 6.0V tr = t f = 6ns 15 20 23 ns 2.0V 70 90 105 4.5V 14 18 21 Minimum Pulse Width, Reset High (Figure 1) tw 6.0V tr = t f = 6ns 12 15 18 ns 2.0V 60 75 90 4.5V 12 15 18 Minimum Setup Time, Reset Inactive to Clock tsu 6.0V tr = t f = 6ns 10 13 15 ns High Speed CMOS Logic – 54HC4040

www.siliconsupplies.com x Timing Diagram Expanded Logic Diagram Rev 1.0 15/09/25 High Speed CMOS Logic – 54HC4040