54HC373

54HC373 SS | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 7

Technical content

High Speed CMOS Logic – 54HC373 8-bit transparent D-Type Latch with 3-State Outputs in bare die form Rev 1.0 10/03/21  Output Drive Capability: 15 LSTTL Loads Die Size (Unsawn) 1460 x 1550 57 x 61 µm mils Minimum Bond Pad Size 108 x 108 4.25 x 4.25 µm mils Die Thickness 350 (±20) 13.78 (±0.79) µm mils Top Metal Composition Al 1%Si 1.1µm Back Metal Composition N/A – Bare Si  Low Input Current: 1µA  Outputs directly inter face CMOS, NMOS and TTL  Operating Voltage Range: 2V to 6V  CMOS High Noise Immunity  Function compatible with 54LS373  Full Military Temperature Range. Features:

Ordering Information

The following part suffixes apply: The 54HC373 consists of eight D-type transparent latches fabricated using a 2.5µm 5V CMOS process to combine high speed performance LSTTL performance with CMOS low power consumption. Each latch is equipped with separate D-Type inputs and 3-State outputs for bus oriented applications. Data output changes asynchronously and data may be latched even when the outputs are not enabled. Device inputs accept standard CMOS outputs or LSTTL outputs using pull-up resistors. All inputs are equipped with protection circuits against static discharge and transient excess voltage.

Description

Die Dimensions in µm (mils) 1460 (57)  No suffix - MIL-STD-883 /2010B Visual Inspection 1550 (61)  “ H” - MIL-STD-883 /2010B Visual Inspection + MIL-PRF-38534 Class H LAT  “ K” - MIL-STD-883 /2010A Visual Inspection (Space) + MIL-PRF-38534 Class K LAT LAT = Lot Acceptance Test. For further information on LAT process flows see below. www.siliconsupplies.com\\quality\\bare-die-lot-qualification Supply Formats: Mechanical Specification  Default – Die in Waffle Pack (100 per tray capacity)  Sawn Wafer on Tape – On request  Unsawn Wafer – On request  Die Thickness <> 350µm(14 Mils) – On request  Assembled into Ceramic Package – On request Page 1 of 7 www.siliconsupplies.com A ll data sheet.com

www.siliconsupplies.com d High Speed CMOS Logic – 54HC373 Rev 1.0 10/03/21Pad Layout and Functions 1460µm (57.48 mils) 1550µm (61.02 mils) 0,0 Logic Diagram DIE ID 9 131415 16 17 18 3 4 5 6 7 7 COORDINATES (mm) PAD FUNCTION X Y 1 OE 0.1205 0.597 2 1Q 0.1205 0.3595 3 1D 0.1205 0.122 4 2D 0.413 0.1225 5 2Q 0.582 0.1225 6 3Q 0.7415 0.1225 7 3D 0.913 0.1225 8 4D 1.234 0.116 9 4Q 1.232 0.29 10 GND 1.232 0.51 11 LE 1.232 0.842 12 5Q 1.232 1.0795 13 5D 1.232 1.317 14 6D 0.9395 1.3165 15 6Q 0.7705 1.3165 16 7Q 0.611 1.3165 17 7D 0.4395 1.3165 18 8D 0.1185 1.323 19 8Q 0.1205 1.149 20 VCC 0.1205 0.929 CONNECT CHIP BACK TO VCC OR FLOAT INPUTS OUTPUT OE LE D Q L L L H H H L X H L X X H L No Change Z H = High level (steady state) L = Low level (steady state) Z = High Impedance X = Don’t care Truth Table Pad 10 = GND, Pad 20 = VCC A ll data sheet.com

www.siliconsupplies.com High Speed CMOS Logic – 54HC373 Rev 1.0 10/03/21Absolute Maximum Ratings1 PARAMETER SYMBOL VALUE UNIT DC Supply Voltage (Referenced to GND) VCC -0.5 to +7.0 V DC Input Voltage (Referenced to GND) VIN -1.5 to VCC +1.5 V DC Output Voltage (Referenced to GND) VOUT -0.5 to VCC +0.5 V DC Input Current, per pad IIN ±20 mA DC Output Current, per pad IOUT ±35 mA DC Supply Current, VCC or GND ICC ±75 mA Power Dissipation in Still Air2 P D 750 mW Storage Temperature Range TSTG -65 to 150 °C 1. Operation above the absolute maximum rating may cause device failure. Operation at the absolute maximum ratings, for extended periods, may reduce device reliability. 2. Measured in plastic DIP package, results in die form are dependent on die attach and assembly method. Recommended Operating Conditions3 (Voltages referenced to GND) 3. This device contains protection circuitry to guard against dama ge due to high static voltages or electric fields. However, pr ecautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance ci rcuit. For proper operation, VIN and V OUT should be constrained to the range GND ≤ (V IN or VOUT) ≤ VCC. Unused inputs must always be tied to an appropriate logic vo ltage level (e.g., either GND or V CC). Unused outputs must be left open. PARAMETER SYMBOL MIN MAX UNITS Supply Voltage VCC 2 6 V DC Input or Output Voltage VIN ,VOUT 0 V CC V Operating Temperature Range TJ -55 +125 °C VCC = 2V 0 1000 VCC = 4.5V 0 500 Input Rise or Fall Times tr, tf VCC = 6.0V 0 400 ns LIMITS PARAMETER SYMBOL V CC CONDITIONS 25°C 85°C FULL RANGE 4 UNITS 2.0V 1.5 1.5 1.5 4.5V 3.15 3.15 3.15 Minimum High-Level Input Voltage VIH 6.0V VOUT = 0.1V or VCC -0.1V │IOUT│≤ 20µA 4.2 4.2 4.2 V 2.0V 0.5 0.5 0.5 4.5V 1.35 1.35 1.35 Maximum Low-Level Input Voltage VIL 6.0V VOUT = 0.1V or VCC -0.1V │IOUT│≤ 20µA 1.8 1.8 1.8 V 2V 1.9 1.9 1.9 4.5V 4.4 4.4 4.4 6.0V VIN = VIH or VIL │IOUT│≤ 20µA 5.9 5.9 5.9 V 4.5V VIN = VIH or VIL │IOUT│≤ 6.0mA 3.98 3.84 3.70 Minimum High-Level Output Voltage VOH 6.0V VIN = VIH or VIL │IOUT│≤ 7.8mA 5.48 5.34 5.20 V A ll data sheet.com

www.siliconsupplies.com High Speed CMOS Logic – 54HC373 Rev 1.0 10/03/21DC Electrical Characteristics Continued (Voltages referenced to GND) LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE4 UNITS 2V 0.1 0.1 0.1 4.5V 0.1 0.1 0.1 6.0V VIN = VIH or VIL │IOUT│≤ 20µA 0.1 0.1 0.1 V 4.5V VIN = VIH or VIL │IOUT│≤ 6.0mA 0.26 0.33 0.40 V Maximum Low-Level Output Voltage VOL 6.0V VIN = VIH or VIL │IOUT│≤ 7.8mA 0.26 0.33 0.40 V Maximum Input Leakage Current IIN 6.0V VIN = VCC or GND ±0.1 ±1.0 ±1.0 µA Maximum Quiescent Supply Current ICC 6.0V VIN = VCC or GND, IOUT = 0µA 4 40 160 µA Maximum Three-State Leakage Current IOZ 6.0V Output in High- Impedance State, VIN = VIH or VIL, VOUT = VCC or GND ±0.5 ±5.0 ±10.0 µA LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE4 UNITS 2.0V 125 155 190 4.5V 25 31 38 Maximum Propagation Delay, D to Q, (Figure 1,5) tPLH, tPHL 6.0V CL = 50pF, Input tr = tf = 6ns 21 26 32 ns 2.0V 140 175 210 4.5V 28 35 42 Maximum Propagation Delay, LE to Q, (Figure 2,5) tPLH, tPHL 6.0V CL = 50pF, Input tr = tf = 6ns 24 30 36 ns 2.0V 150 190 225 4.5V 30 38 45 Maximum Propagation Delay, OE to Q (Figure 3,6) tPLZ, tPHZ 6.0V CL = 50pF, Input tr = tf = 6ns 26 33 38 ns 2.0V 150 190 225 4.5V 30 38 45 Maximum Propagation Delay, OE to Q (Figure 3,6) tPZL, tPZH 6.0V CL = 50pF, Input tr = tf = 6ns 26 33 38 ns

5 Not production tested in die form, characterized by chip design

A ll data sheet.com

www.siliconsupplies.com High Speed CMOS Logic – 54HC373 Rev 1.0 10/03/21 Timing Requirements6 LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE4 UNITS 2.0V 25 30 40 4.5V 5.0 6.0 8.0 Minimum Setup Time, D to LE (Figure 4) tSU 6.0V CL = 50pF, Input tr = tf = 6ns 5.0 6.0 7.0 ns 2.0V 5.0 5.0 5.0 4.5V 5.0 5.0 5.0 Minimum Hold Time, LE to D (Figure 4) th 6.0V CL = 50pF, Input tr = tf = 6ns 5.0 5.0 5.0 ns 2.0V 60 75 90 4.5V 12 15 18 Minimum Pulse Width, LE (Figure 4) tw 6.0V CL = 50pF, Input tr = tf = 6ns 10 13 15 ns 2.0V 1000 1000 1000 4.5V 500 500 500 Maximum Input Rise & Fall Times (Figure 4) tr, tf 6.0V CL = 50pF, Input tr = tf = 6ns 400 400 400 ns LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE4 UNITS 2.0V 60 75 90 4.5V 12 15 18 Maximum Output Transition Time, Any Output (Figure 1,5) tTLH, tTHL 6.0V CL = 50pF, Input tr = tf = 6ns 10 13 15 pF Maximum Input Capacitance CIN - CL = 50pF, Input tr = tf = 6ns 10 10 10 pF Maximum 3-State Output Capacitance COUT - CL = 50pF, Input tr = tf = 6ns High Z state 15 15 15 pF TYPICAL Power Dissipation Capacitance (Per latch)7 CPD 5V - pF 7. Used to determine the no-load dynamic power consumption: PD = CPD VCC f + ICC VCC. A ll data sheet.com