74HC244 SS | Alldatasheet
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Technical content
High Speed CMOS Logic – 74HC244 Octal 3-State Non-Inverting Buffer / Line Driver / Line Receiver in bare die form Rev 1.1 01/05/18 Output Drive Capability: 15 LSTTL Loads Low Input Current: 1µA Outputs directly inter face CMOS, NMOS and TTL Operating Voltage Range: 2V to 6V CMOS High Noise Immunity Function compatible with 74LS244. Features:
Ordering Information
The following part suffixes apply: No suffix - MIL-STD-883 /2010B Visual Inspection The 74HC244 is fabricated using a 2.5µm 5V CMOS process and has the same high speed performance of LSTTL combined with CMOS low power consumption. The device can be used as two 4-bit buffers or one 8-bit buffer and features non-inverting inputs with two output enables, each controlling four of the 3-state outputs. The device is specifically designed to improve performance and density in clock drivers, 3-state memory address drivers and bus orientated transmitters and receivers. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of V CC
Description
Die Dimensions in µm (mils) 1900 (75) Die Size (Unsawn) 1900 x 2050 75 x 81 µm mils Minimum Bond Pad Size 100 x 100 3.94 x 3.94 µm mils Die Thickness 350 (±20) 13.78 (±0.79) µm mils Top Metal Composition Al 1%Si 1.1µm Back Metal Composition N/A – Bare Si For High Reliability versions of this product please see 54HC244 Supply Formats: Mechanical Specification 2050 (81) Default – Die in Waffle Pack (100 per tray capacity) Sawn Wafer on Tape – On request Unsawn Wafer – On request Die Thickness <> 350µm(14 Mils) – On request Assembled into Ceramic Package – On request Page 1 of 6 www.siliconsupplies.com A ll data sheet.com
www.siliconsupplies.com d High Speed CMOS Logic – 74HC244 Rev 1.1 01/05/18 PAD FUNCTION
1 ENABLE A
3 YB4
5 YB3
7 YB2
9 YB1
10 GND
12 YA4
14 YA3
16 YA2
18 YA1
19 ENABLE B
20 VCC
CONNECT CHIP BACK TO VCC OR FLOAT Pad Layout and Functions Truth Table Logic Diagram INPUTS OUTPUTS ENABLE A ENABLE B A, B YA, YB L L H L H X L H Z H = High level (steady state) L = Low level (steady state) X = Don’t care Z = High impedance Pad 20 = VCC Pad 10 = GND 1900µm (74.80 mils) 2050µm (80.71 mils) 0,0 1 20 2 8 9 10 11 12 1819 DIE ID A ll data sheet.com
www.siliconsupplies.com PARAMETER SYMBOL MIN MAX UNITS DC Supply Voltage VCC 2 6 V DC Input or Output Voltage VIN ,VOUT 0 VCC V Operating Temperature Range TA 0 +85 °C VCC = 2.0V 0 1000 VCC = 4.5V 0 500 Input Rise and Fall Time VCC = 6.0V tr, tf 0 400 ns Recommended Operating Conditions3 (Voltages referenced to GND) Absolute Maximum Ratings1 PARAMETER SYMBOL VALUE UNIT DC Supply Voltage (Referenced to GND) VCC -0.5 to +7.0 V DC Input Voltage (Referenced to GND) VIN -1.5 to VCC +1.5 V DC Output Voltage (Referenced to GND) VOUT -0.5 to VCC +0.5 V DC Input Current, per pin IIN ±20 mA DC Output Current, per pin IOUT ±35 mA DC VCC or GND Current, per pin ICC ±75 mA Power Dissipation in Still Air2 P D 750 mW Storage Temperature Range TSTG -65 to 150 °C High Speed CMOS Logic – 74HC244 Rev 1.1 01/05/18 1. Operation above the absolute maximum rating may cause device failure. Operation at the absolute maximum ratings, for extended periods, may reduce device reliability. 2. Measured in plastic DIP package, results in die form are dependent on die attach and assembly method. Pad Descriptions ADDRESS INPUTS A1, A2, A3, A4, B1, B2, B3, B4 Data input pins. Data on these pins appear in non-inverted form on the corresponding Y outputs, when the outputs are enabled. CONTROL INPUTS Enable A, Enable B (Pads 1, 19) Output enables (active–low). When a low level is applied to these pins, the outputs are enabled and the devices function as non- inverting buffers. When a high level is applied, the outputs assume the high impedance state. OUTPUTS YA1, YA2, YA3, YA4, YB1, YB2, YB3, YB4 Device outputs. Depending upon the state of the output– enable pins, these outputs are either non-inverting outputs or high– impedance outputs. 3. This device contains protection circuitry to guard against dama ge due to high static voltages or electric fields. However, pr ecautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-im pedance circuit. For proper opera tion, VIN and V OUT should be constrained to the range GND ≤ (V IN or VOUT) ≤ VCC. Unused inputs must always be tied to an appropriate logic vo ltage level (e.g., either GND or VCC). Unused outputs must be left open. A ll data sheet.com
High Speed CMOS Logic – 74HC244 Rev 1.1 01/05/18 LIMITS PARAMETER SYMBOL VCC CONDITIONS FULL RANGE4 UNITS 25°C 85°C 2.0V 1.5 1.5 1.5 3.0V 2.1 2.1 2.1 4.5V 3.15 3.15 3.15 Minimum High-Level Input Voltage VIH 6.0V VOUT = VCC -0.1V │IOUT│≤ 20µA V 4.2 4.2 4.2 2.0V 0.5 0.5 0.5 3.0V 0.9 0.9 0.9 4.5V 1.35 1.35 1.35 VOUT = 0.1V Maximum Low-Level Input Voltage VIL V │IOUT│≤ 20µA 6.0V 1.8 1.8 1.8 2.0V 1.9 1.9 1.9 4.5V 4.4 4.4 4.4 6.0V VIN = VIH │IOUT│≤ 20µA 5.9 5.9 5.9 V 3.0V VIN = VIH │IOUT│≤ 2.4mA 2.48 2.34 2.34 4.5V VIN = VIH │IOUT│≤ 6.0mA 3.98 3.84 3.84 Minimum High-Level Output Voltage VOH 6.0V VIN = VIH │IOUT│≤ 7.8mA 5.48 5.34 5.34 V 2.0V 0.1 0.1 0.1 4.5V 0.1 0.1 0.1 6.0V VIN = VIL │IOUT│≤ 20µA 0.1 0.1 0.1 V 3.0V VIN = VIL │IOUT│≤ 2.4mA 0.26 0.33 0.33 4.5V VIN = VIL │IOUT│≤ 6.0mA 0.26 0.33 0.33 Maximum Low-Level Output Voltage VOL 6.0V VIN = VIL │IOUT│≤ 7.8mA 0.26 0.33 0.33 V Maximum Input Leakage Current IIN 6.0V VIN = VCC or GND ±0.1 ±1.0 ±1.0 µA Maximum 3-State leakage current IOZ 6.0V VOUT = VCC or 0 VIN = VIL or VIH ±0.5 ±5.0 ±5.0 µA Maximum Quiescent Supply Leakage Current ICC 6.0V VIN = VCC or GND IOUT = 0µA 4 40 40 µA Page 4 of 6 www.siliconsupplies.com A ll data sheet.com
High Speed CMOS Logic – 74HC244 Rev 1.1 01/05/18 AC Electrical Characteristics5 LIMITS PARAMETER SYMBOL VCC CONDITIONS FULL RANGE4 25°C 85°C UNITS 2.0V 96 115 115 3.0V 50 60 60 4.5V 18 23 23 Maximum Propagation Delay, CL = 50pF, A to YA or B to YB (Figure 1, 3) tPLH, tPHL ns tr = tf = 6ns 6.0V 15 20 20 2.0V 110 140 140 3.0V 60 70 70 4.5V 22 28 28 Maximum Propagation Delay, CL = 50pF, Output Enable to YA or YB (Figure 2,4) tPLZ, tPHZ ns tr = tf = 6ns 6.0V 19 24 24 2.0V 110 140 140 3.0 60 70 70 4.5V 22 28 28 Maximum Propagation Delay, CL = 50pF, Output Enable to YA or YB (Figure 2,4) tPZL, tPZH ns tr = tf = 6ns 6.0V 19 24 24 2.0V 60 75 75 3.0V 23 27 27 4.5V 12 15 15 Maximum Output Rise CL = 50pF, and Fall Time (Figure 1, 3) tTLH, tTHL ns tr = tf = 6ns 6.0V 10 13 13 Maximum Input Capacitance CIN - - 10 10 10 pF Maximum Three-State Output Capacitance (Output in High- Impedance State) COUT - - 15 15 15 pF TYPICAL Power Dissipation TA = 25°C, pF Capacitance (Per Buffer)5 CPD - VCC = 5.0V 34 5. Not production tested in die form, characterized by chip design and tested in package LAT. 6. Used to determine the no-load dynamic power consumption: PD = CPD VCC f + ICC VCC. Page 5 of 6 www.siliconsupplies.com A ll data sheet.com